Datasheet MTP40N10E Datasheet (Motorola)

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SEMICONDUCTOR TECHNICAL DATA

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N–Channel Enhancement–Mode Silicon Gate

This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

• Avalanche Energy Specified

• Source–to–Drain Diode Recovery Time Comparable to a

Discrete Fast Recovery Diode

• Diode is Characterized for Use in Bridge Circuits

• I

DSS

and V

Specified at Elevated Temperature

DS(on)

G

N–Channel

D

S



TMOS POWER FET

40 AMPERES

100 VOL TS

R



CASE 221A–06, Style 5

DS(on)

TO–220AB

= 0.04 OHM

MAXIMUM RATINGS

Drain–to–Source Voltage V
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
Gate–to–Source Voltage — Continuous

Gate–to–Source Voltage — Non–Repetitive (tp ≤ 10 ms)

Drain Current — Continuous

Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)

Total Power Dissipation

Derate above 25°C
Operating and Storage Temperature Range TJ, T
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 75 Vdc, VGS = 10 Vdc, PEAK IL = 40 Apk, L = 1.0 mH, RG = 25 W)
Thermal Resistance — Junction to Case

Thermal Resistance — Junction to Ambient

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T

This document contains information on a new product. Specifications and information herein are subject to change without notice.

E–FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

(TC = 25°C unless otherwise noted)

Rating

Symbol Value Unit

DSS

DGR

V

GS

V

GSM

I

D

I

D

I

DM
P

D

stg

E

AS

R

θJC

R

θJA

L

100 Vdc
100 Vdc

±20
±40

40
29

140
169

1.35

–55 to 150 °C

800 mJ

0.74

62.5
260 °C

Vdc
Vpk

Adc

Apk

Watts

W/°C

°C/W

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

 Motorola, Inc. 1997

1

MTP40N10E

)

f = 1.0 MHz)

V

G

)

(

DS

,

D

,

(

S

,

GS

,

ELECTRICAL CHARACTERISTICS

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage

(VGS = 0 Vdc, ID = 0.25 mAdc)
T emperature Coef ficient (Positive) (Cpk ≥ 2.0)

Zero Gate Voltage Drain Current

(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ =125°C)

Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) I

ON CHARACTERISTICS

Gate Threshold Voltage (Cpk ≥ 2.0)

(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)

Static Drain–to–Source On–Resistance (Cpk ≥ 2.0)

(VGS = 10 Vdc, ID = 20 Adc)

Drain–to–Source On–Voltage

(VGS = 10 Vdc, ID = 40 Adc)
(VGS = 10 Vdc, ID = 20 Adc, TJ = 125°C)

Forward Transconductance (VDS = 8.4 Vdc, ID = 20 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance

Transfer Capacitance

SWITCHING CHARACTERISTICS

Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge

(See Figure 8)

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage

Reverse Recovery Time

(See Figure 14)

Reverse Recovery Stored Charge Q

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.

(3) Reflects typical values.

(1)

Cpk

(T

= 25°C unless otherwise noted)

J

Characteristic

(VDS = 25 Vdc, VGS = 0 Vdc,

(2)

(IS = 40 Adc, VGS = 0 Vdc, TJ = 125°C)

Max limit – Typ

Ť

+

3 sigma

f = 1.0 MHz

(VDD = 50 Vdc, ID = 40 Adc,

(VDS = 80 Vdc, ID = 40 Adc,

(IS = 40 Adc, VGS = 0 Vdc)

(IS = 40 Adc, VGS = 0 Vdc,

= 10 Vdc,

GS

RG = 9.1 Ω)

VGS = 10 Vdc)

dIS/dt = 100 A/µs)

Ť

(3)

(3)

(3)

Symbol Min Typ Max Unit

V

(BR)DSS

I

DSS

GSS

V

GS(th)

R

DS(on)

V

DS(on)

FS

C

iss

C

oss

C

rss

t

d(on)

t

r

t

d(off)

t

f

Q

T

Q

1

Q

2

Q

3

V

SD

t

rr

t

a

t

b

RR

L

D

L

S

100

—

—
—

— — 100 nAdc

2.0
—

— 0.033 0.04

—
—

17 21 — mhos

— 2305 3230 pF
— 620 1240
— 205 290

— 19 40 ns
— 165 330
— 75 150
— 97 190
— 80 110 nC
— 15 —
— 40 —
— 29 —

—
—

— 152 —
— 117 —
— 35 —
— 1.0 — µC

—
—

— 7.5 —

—

112

—
—

2.9

6.7

—
—

0.96

0.88

3.5

4.5

—
—

10

100

4.0
—

1.9

1.7

1.0
—

—
—

mV/°C

mV/°C

Ohms

Vdc

µAdc

Vdc

Vdc

Vdc

ns

nH

2

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

MTP40N10E

80

VGS = 10 V TJ = 25°C

70
60
50
40
30

, DRAIN CURRENT (AMPS)

20

D

I

10

0

012345678910

VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

8 V

9 V

Figure 1. On–Region Characteristics

0.07
VGS = 10 V

0.06

0.05

0.04

0.03

0.02

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

0.01

0

DS(on)

R

01020304050607080

TJ = 100°C

25°C

–55°C

ID, DRAIN CURRENT (AMPS)

7 V

6 V

5 V

80

VDS ≥ 10 V

70
60
50
40
30

, DRAIN CURRENT (AMPS)

20

D

I

10

0

23 4 5 67 8

VGS, GATE–T O–SOURCE VOLTAGE (VOLTS)

100°C

25°C

TJ = –55°C

Figure 2. Transfer Characteristics

0.050
TJ = 25°C

0.045

0.040

0.035

0.030

0.025

0.020

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

0.015

0.010

DS(on)

R

01020304050607080

VGS = 10 V

15 V

ID, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus Drain Current

and T emperature

2.0

1.8

VGS = 10 V
ID = 20 A

1.6

1.4

1.2

1.0

0.8

(NORMALIZED)

0.6

, DRAIN–TO–SOURCE RESIST ANCE

0.4

0.2

DS(on)

R

0

–50 –25 0 25 50 75 100 125 150

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On–Resistance Variation with

Temperature

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

1000

, LEAKAGE (nA)

DSS

I

VGS = 0 V

100

10

1.0
010203040 607080 100

VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

TJ = 125°C

100°C

50 90

Figure 6. Drain–T o–Source Leakage

Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

3

MTP40N10E

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter­mined by how fast the FET input capacitance can be charged
by current from the generator.

The published capacitance data is difficult to use for calculat­ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I

) can be made from a rudimentary analysis of

G(A V)

the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a resis­tive load, VGS remains virtually constant at a level known as
the plateau voltage, V

. Therefore, rise and fall times may

SGP

be approximated by the following:
tr = Q2 x RG/(VGG – V
tf = Q2 x RG/V

GSP

GSP

)

where
VGG = the gate drive voltage, which varies from zero to V

GG

RG = the gate drive resistance
and Q2 and V

are read from the gate charge curve.

GSP

During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val­ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

t

d(off)

= RG C

= RG C

In [VGG/(VGG – V

iss

In (VGG/V

iss

GSP

)]

GSP

)

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off–state condition when cal­culating t
on–state when calculating t

and is read at a voltage corresponding to the

d(on)

d(off)

.

At high switching speeds, parasitic circuit elements com­plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func­tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea­sure and, consequently , is not specified.

The resistive switching time variation versus gate resis­tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op­erated into an inductive load; however, snubbing reduces
switching losses.

C, CAPACITANCE (pF)

8000
7000
6000
5000
4000
3000
2000
1000

0

VDS = 0 V

C

iss

C

rss

–10 –5 0 5 10 25

GATE–T O–SOURCE OR DRAIN–TO–SOURCE VOL TAGE (VOLTS)

VGS = 0 V

C

rss

15 20

V

GS

V

DS

Figure 7. Capacitance Variation

TJ = 25

°C

C

iss

C

oss

4

Motorola TMOS Power MOSFET Transistor Device Data

, GATE–T O–SOURCE VOLTAGE (VOLTS)

GS

V

10

9
8
7
6
5
4
3
2
1

0

0

Q3

10 20 30 40 50

QG, TOTAL GATE CHARGE (nC)

QT

Q2Q1

MTP40N10E

V

DS

, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

10,000

VDD = 50 V
ID = 40 A
VGS = 10 V
TJ = 25

°

1000

t, TIME (ns)

100

10

1.0 10 100

C

t

r

t

f

t

d(off)

t

d(on)

RG, GATE RESISTANCE (OHMS)

V

GS

ID = 40 A
TJ = 25

°

V

DS

60 70 80

80
72
64
56
48
40
32
24

C

16
8

0

Figure 8. Gate–T o–Source and Drain–To–Source

V oltage versus Total Charge

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

40
35

30
25
20
15
10

, SOURCE CURRENT (AMPS)

S

I

5

VGS = 0 V
TJ = 25

°

C

0

0.60 0.65 0.70 0.75 0.80 1.0
VSD, SOURCE–TO–DRAIN VOL TAGE (VOLTS)

Figure 10. Diode Forward V oltage versus Current

SAFE OPERATING AREA

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

0.85 0.90 0.95

The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for­ward biased. Curves are based upon maximum peak junc­tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”

Switching between the off–state and the on–state may tra­verse any load line provided neither rated peak current (IDM)
nor rated voltage (V

) is exceeded and the transition time

DSS

(tr,tf) do not exceed 10 µs. In addition the total power aver­aged over a complete switching cycle must not exceed
(T

J(MAX)

– TC)/(R

θJC

).

A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dis­sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem­perature.

Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur­rent (ID), in accordance with industry custom. The energy rat­ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur­rents below rated continuous ID can safely be assumed to
equal the values indicated.

5

MTP40N10E

SAFE OPERATING AREA

1000

VGS = 20 V
SINGLE PULSE
TC = 25

°

C

100

10

, DRAIN CURRENT (AMPS)

D

I

1.0

0.1 1.0 1000
VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

1.0 ms

100 ms

10 ms

R

DS(on)

THERMAL LIMIT
PACKAGE LIMIT

10 ms

dc

100

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

1.0
D = 0.5

0.2

0.1

0.1

0.05

0.02

r(t), NORMALIZED EFFECTIVE

TRANSIENT THERMAL RESISTANCE

0.0
SINGLE PULSE

0.01

1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01

LIMIT

800
700
600
500
400
300
200

AVALANCHE ENERGY (mJ)

, SINGLE PULSE DRAIN–TO–SOURCE

100

AS

E

0

25 50 75 100 12510

Figure 12. Maximum Avalanche Energy versus

P

(pk)

t

1

t

DUTY CYCLE, D = t1/t

TJ, STARTING JUNCTION TEMPERATURE (°C)

Starting Junction T emperature

R

(t) = r(t) R

θ

JC

D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t

2

T

J(pk)

2

– TC = P

θ

(pk)

JC

1

R

θ

JC

ID = 40 A

150

(t)

t, TIME (seconds)

Figure 13. Thermal Response

di/dt

I

S

t

rr

t

t

a

b

TIME

t

p

0.25 I

S

I

S

Figure 14. Diode Reverse Recovery Waveform

6

Motorola TMOS Power MOSFET Transistor Device Data

MTP40N10E

P ACKAGE DIMENSIONS

NOTES:

SEATING

–T–

PLANE

B

4

Q

123

F

T

A

U

H

K

C

S

STYLE 5:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

Z

L

V

R
J

G

D

N

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.

DIM MIN MAX MIN MAX

A 0.570 0.620 14.48 15.75
B 0.380 0.405 9.66 10.28
C 0.160 0.190 4.07 4.82
D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73

G 0.095 0.105 2.42 2.66

H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33

Q 0.100 0.120 2.54 3.04

R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
V 0.045 ––– 1.15 –––
Z ––– 0.080 ––– 2.04

MILLIMETERSINCHES

CASE 221A–06

ISSUE Y

Motorola TMOS Power MOSFET Transistor Device Data

7

MTP40N10E

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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Motorola TMOS Power MOSFET Transistor Device Data

Mfax is a trademark of Motorola, Inc.

MTP40N10E/D