Page 1
1
Motorola TMOS Power MOSFET Transistor Device Data
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resistance area product about one–half that of standard MOSFET s. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low R
DS(on)
Technology
• Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETS
• Avalanche Energy Specified
• I
DSS
and V
DS(on)
Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and
TMOS E–FET
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–to–Source Voltage V
DSS
60 Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
DGR
60 Vdc
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage — Non–repetitive (tp ≤ 10 ms)
V
GS
V
GSM
± 20
± 25
Vdc
Vpk
Drain Current — Continuous @ 25 °C
Drain Current — Continuous @ 100 °C
Drain Current — Single Pulse (tp ≤ 10 µs)
I
D
I
D
I
DM
32
22.6
112
Adc
Apk
Total Power Dissipation @ 25 °C
Derate above 25 °C
P
D
90
0.6
Watts
W/°C
Operating and Storage Temperature Range TJ, T
stg
–55 to 175 °C
Single Pulse Drain–to–Source Avalanche Energy — STARTING TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 32 Apk, L = 0.1 mH, RG = 25 Ω)
E
AS
205 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
R
θJC
R
θJA
1.67
62.5
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 seconds T
L
260 °C
Designer’s Data for “Worst Case” Conditions —The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
Order this document
by MTP36N06V/D
SEMICONDUCTOR TECHNICAL DATA
TM
D
S
G
TMOS POWER FET
32 AMPERES
60 VOLTS
R
DS(on)
= 0.04 OHM
Motorola Preferred Device
CASE 221A–06, Style 5
TO–220AB
Motorola, Inc. 1996
Page 2
MTP36N06V
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(T
J
= 25 °C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V
(BR)DSS
60
—
—
61
—
—
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150 °C)
I
DSS
—
—
—
—
10
100
µAdc
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) I
GSS
— — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
V
GS(th)
2.0
—
2.6
6.0
4.0
—
Vdc
mV/°C
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 16 Adc) R
DS(on)
— 0.034 0.04 Ohm
Drain–to–Source On–Voltage
(VGS = 10 Vdc, ID = 32 Adc)
(VGS = 10 Vdc, ID = 16 Adc, TJ = 150 °C)
V
DS(on)
—
—
1.25
—
1.54
1.47
Vdc
Forward Transconductance (VDS = 7.6 Vdc, ID = 16 Adc) g
FS
5.0 7.83 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 1220 1700 pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
C
oss
— 337 470
Reverse Transfer Capacitance
f = 1.0 MHz)
C
rss
— 74.8 150
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
d(on)
— 14 30 ns
Rise Time
t
r
— 138 270
Turn–Off Delay Time
VGS = 10 Vdc,
RG = 9.1 Ω)
t
d(off)
— 54 100
Fall Time
G
= 9.1 Ω)
t
f
— 91 180
Q
T
— 39 50 nC
(See Figure 8)
DS
= 48 Vdc, ID = 32 Adc,
Q
1
— 7.0 —
(VDS = 48 Vdc, ID = 32 Adc,
VGS = 10 Vdc)
Q
2
— 17 —
Q
3
— 13 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 32 Adc, VGS = 0 Vdc)
(IS = 32 Adc, VGS = 0 Vdc, TJ = 150 °C)
V
SD
—
—
1.03
0.94
2.0
—
Vdc
t
rr
— 92 —
S
= 32 Adc, VGS = 0 Vdc,
t
a
— 64 —
(IS = 32 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
t
b
— 28 —
Reverse Recovery Stored Charge Q
RR
— 0.332 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
L
D
—
3.5
4.5
—
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
— 7.5 —
nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
Gate Charge
Reverse Recovery Time
(VDD = 30 Vdc, ID = 32 Adc,
(V
(I
ns
Page 3
MTP36N06V
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
0 1 2 3
0
18
72
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
I
D
, DRAIN CURRENT (AMPS)
1 3 5 7 9
0
18
54
72
I
D
, DRAIN CURRENT (AMPS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0 18 36 72
0.02
0.06
0.04
0.1
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
0 36 54 72
0.028
0.036
0.044
0.052
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
ID, DRAIN CURRENT (AMPS)
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
0 10 20 40 50 60
10
100
Figure 5. On–Resistance Variation with
Temperature
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
I
DSS
, LEAKAGE (nA)
TJ = 25
°C
VGS = 10 V
9 V
8 V
6 V
5 V
7 V
VGS = 10 V
TJ = 100
°C
25
°C
– 55
°C
25
°C
TJ = 25
°C
VGS = 10 V
15 V
VGS = 0 V
TJ = 125
°C
36
54
4
36
54 18
30
VDS ≥ 10 V
TJ = 100
°C
–55
°C
4 V
2
4 6 8
0.08
0
1000
1
100
°C
25°C
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
– 50
0.6
0.8
1.2
1.6
1.8
TJ, JUNCTION TEMPERATURE (
°
C)
– 25 0 25 50 75 100 125 150
VGS = 10 V
ID = 16 A
1
1.4
175
Page 4
MTP36N06V
4
Motorola TMOS Power MOSFET Transistor Device Data
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
G(AV)
) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, V
SGP
. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – V
GSP
)
tf = Q2 x RG/V
GSP
where
VGG = the gate drive voltage, which varies from zero to V
GG
RG = the gate drive resistance
and Q2 and V
GSP
are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= RG C
iss
In [VGG/(VGG – V
GSP
)]
t
d(off)
= RG C
iss
In (VGG/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off–state condition when calculating t
d(on)
and is read at a voltage corresponding to the
on–state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The M OSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
10 5 0 10 20 25
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
Figure 7. Capacitance Variation
V
GS
V
DS
4000
3000
2000
1000
0
TJ = 25
°C
VDS = 0 V
C
iss
C
oss
C
rss
5 15
VGS = 0 V
C
iss
C
rss
Page 5
MTP36N06V
5
Motorola TMOS Power MOSFET Transistor Device Data
V
DS
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
V
GS
, GATE–TO–SOURCE VOLTAGE (VOLTS)
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
0.5 0.7 0.950.85 0.9 1.05
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
I
S
, SOURCE CURRENT (AMPS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
RG, GATE RESISTANCE (OHMS)
1 10 100
t, TIME (ns)
TJ = 25°C
ID = 32 A
VDD = 30 V
VGS = 10 V
TJ = 25°C
VGS = 0 V
Figure 10. Diode Forward Voltage versus Current
0
QT, TOTAL CHARGE (nC)
5 10 20 2515
TJ = 25°C
ID = 32 A
0
16
24
32
1000
100
10
1
10
6
2
0
12
8
4
30
25
20
15
10
5
0
t
f
t
d(off)
t
d(on)
t
r
V
GS
Q2
8
Q3
QT
Q1
V
DS
10.80.750.55 0.650.6
30 35 40
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum s imultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (V
DSS
) is exceeded and the transition time
(tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed
(T
J(MAX)
– TC)/(R
θJC
).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in a valanche a nd peak junction
temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating m ust be d erated f or t emperature as shown i n the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.
Page 6
MTP36N06V
6
Motorola TMOS Power MOSFET Transistor Device Data
SAFE OPERATING AREA
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
0.1 100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
I
D
, DRAIN CURRENT (AMPS)
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10
VGS = 20 V
SINGLE PULSE
TC = 25°C
1
Figure 13. Thermal Response
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
R
θ
JC
(t) = r(t) R
θ
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
– TC = P
(pk)
R
θ
JC
(t)
P
(pk)
t
1
t
2
DUTY CYCLE, D = t1/t
2
Figure 14. Diode Reverse Recovery Waveform
di/dt
t
rr
t
a
t
p
I
S
0.25 I
S
TIME
I
S
t
b
10
100
1000
1
dc
100 µs
1 ms
10 ms
10 µs
t, TIME (s)
1.00
0.10
0.01
0.2
D = 0.5
0.05
0.01
SINGLE PULSE
0.1
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
0.02
TJ, STARTING JUNCTION TEMPERATURE (°C)
E
AS
, SINGLE PULSE DRAIN–TO–SOURCE
AVALANCHE ENERGY (mJ)
25 50 75 100 125
ID = 32 A
150
0
175
50
25
225
75
100
125
150
200
175
Page 7
MTP36N06V
7
Motorola TMOS Power MOSFET Transistor Device Data
PACKAGE DIMENSIONS
CASE 221A–06
ISSUE Y
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.570 0.620 14.48 15.75
B 0.380 0.405 9.66 10.28
C 0.160 0.190 4.07 4.82
D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73
G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33
Q 0.100 0.120 2.54 3.04
R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
V 0.045 ––– 1.15 –––
Z ––– 0.080 ––– 2.04
B
Q
H
Z
L
V
G
N
A
K
F
1 2 3
4
D
SEATING
PLANE
–T–
C
S
T
U
R
J
Page 8
MTP36N06V
8
Motorola TMOS Power MOSFET Transistor Device Data
How to reach us:
USA / EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE (602) 244–6609 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different
applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MTP36N06V/D
*MTP36N06V/D*
◊
Loading...