Page 1
MTP2P50E
Power MOSFET
2 Amps, 500 Volts
P−Channel TO−220
This high voltage MOSFET uses an advanced termination scheme
to provide enhanced voltage−blocking capability without degrading
performance over time. In addition, this Power MOSFET is designed
to withstand high energy in the avalanche and commutation modes.
The energy efficient design also offers a drain−to−source diode with a
fast recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters and PWM motor controls,
these devices are particularly well suited for bridge circuits where
diode speed and commutating safe operating areas are critical and
offer additional safety margin against unexpected voltage transients.
Features
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I
and V
DSS
• This is a Pb−Free Device*
MAXIMUM RATINGS (T
Drain−Source Voltage V
Drain−Gate Voltage (RGS = 1.0 MW)
Gate−Source Voltage
− Continuous
− Non−Repetitive (t
Drain Current − Continuous
Drain Current − Continuous @ 100°C
Drain Current − Single Pulse (t
Total Power Dissipation
Derate above 25°C
Operating and Storage Temperature Range TJ, T
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(V
= 100 Vdc, VGS = 10 Vdc,
DD
= 4.0 Apk, L = 10 mH, RG = 25 W)
I
L
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 sec
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
Specified at Elevated Temperature
DS(on)
= 25°C unless otherwise noted)
C
Rating
≤ 10 ms)
p
≤ 10 ms)
p
Symbol Value Unit
500 Vdc
500 Vdc
± 20
± 40
2.0
1.6
6.0
75
0.6
−55 to 150 °C
80 mJ
1.67
62.5
260 °C
Vdc
Vpk
Adc
Apk
W
W/°C
°C/W
V
V
R
R
DSS
DGR
V
GSM
I
I
I
DM
P
E
T
q
q
GS
D
D
D
stg
AS
JC
JA
L
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2 AMPERES, 500 VOLTS
R
DS(on)
G
4
TO−220AB
CASE 221A
STYLE 5
1
2
3
MTP2P50E = Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
Device Package Shipping
MTP2P50EG TO−220AB
= 6 W
P−Channel
D
S
MARKING DIAGRAM
AND PIN ASSIGNMENT
4
Drain
MTP
2P50EG
AYWW
1
Gate
(Pb−Free)
2
Drain
50 Units/Rail
3
Source
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2010
May, 2010 − Rev. 6
1 Publication Order Number:
MTP2P50E/D
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MTP2P50E
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
J
Characteristic
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
= 0 Vdc, ID = 250 mAdc)
(V
GS
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
= 500 Vdc, VGS = 0 Vdc)
DS
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) I
ON CHARACTERISTICS (Note 1)
Gate Threshold Voltage
= VGS, ID = 250 mAdc)
(V
DS
Temperature Coefficient (Negative)
Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 1.0 Adc) R
Drain−Source On−Voltage (VGS = 10 Vdc)
(I
= 2.0 Adc)
D
(ID = 1.0 Adc, TJ = 125°C)
Forward Transconductance (VDS = 15 Vdc, ID = 1.0 Adc) g
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance C
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Reverse Transfer Capacitance C
SWITCHING CHARACTERISTICS (Note 2)
Turn−On Delay Time
Rise Time t
Turn−Off Delay Time t
(VDD = 250 Vdc, ID = 2.0 Adc,
= 10 Vdc, RG = 9.1 W)
V
GS
Fall Time t
Gate Charge (See Figure 8)
(VDS = 400 Vdc, ID = 2.0 Adc,
V
= 10 Vdc)
GS
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 1)
(IS = 2.0 Adc, VGS = 0 Vdc)
(I
= 2.0 Adc, VGS = 0 Vdc, TJ = 125°C)
S
Reverse Recovery Time
(See Figure 14)
(IS = 2.0 Adc, VGS = 0 Vdc,
/dt = 100 A/ms)
dI
S
Reverse Recovery Stored Charge Q
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
1. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
2. Switching characteristics are independent of operating junction temperature.
Symbol Min Typ Max Unit
V
(BR)DSS
I
DSS
GSS
V
GS(th)
DS(on)
V
DS(on)
FS
C
iss
oss
rss
t
d(on)
r
d(off)
f
Q
T
Q
1
Q
2
Q
3
V
SD
t
rr
t
a
t
b
RR
L
D
L
S
500
−
−
564
−
Vdc
−
mV/°C
mAdc
−
−
−
10
−
100
− − 100 nAdc
2.0−3.0
4.0
4.0
Vdc
−
mV/°C
− 4.5 6.0
Vdc
−
9.5−14.4
−
12.6
0.5 − − mhos
− 845 1183 pF
− 100 140
− 26 52
− 12 24 ns
− 14 28
− 21 42
− 19 38
− 19 27 nC
− 3.7 −
− 7.9 −
− 9.9 −
Vdc
−
2.3
−
1.85
− 223 −
3.5
−
ns
− 161 −
− 62 −
− 1.92 −
mC
nH
−
3.5
−
4.5
−
−
− 7.5 − nH
W
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MTP2P50E
TYPICAL ELECTRICAL CHARACTERISTICS
4
TJ = 25°C VDS ≥ 10 V
3.5
3
2.5
2
1.5
, DRAIN CURRENT (AMPS)
1
D
I
0.5
0
04 8 28
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
V
DS
VGS = 10 V
12 16
6 V
5 V
4 V
20 24
Figure 1. On−Region Characteristics
10
VGS = 10 V
8
6
4
2
, DRAIN‐TO‐SOURCE RESISTANCE (OHMS)
DS(on)
0
R
0 1 2 2.5 3.5 4
I
D
TJ = 100°C
25°C
-55°C
31.50.5
, DRAIN CURRENT (AMPS)
7 V
8 V
4
3.5
3
2.5
2
1.5
, DRAIN CURRENT (AMPS)
1
D
I
0.5
0
23456 7
2.5 3.5 4.5 5.5 6.5
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
TJ = - 55°C
100°C
25°C
Figure 2. Transfer Characteristics
6
5.75
5.5
5.25
4.75
4.5
, DRAIN‐TO‐SOURCE RESISTANCE (OHMS)
4.25
DS(on)
R
TJ = 25°C
5
4
0.5 1.5 2.5 3.5
01 2 3 4
VGS = 10 V
15 V
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
2
VGS = 10 V
I
= 1 A
D
1.5
(NORMALIZED)
1
, DRAIN‐TO‐SOURCE RESISTANCE
DS(on)
R
0.5
- 50 - 25 0 25 50 75 100 125 150 0 10050 150 200 250 500300 350 400 450
T
, JUNCTION TEMPERATURE (°C)
J
Figure 5. On−Resistance Variation with
Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1000
100
, LEAKAGE (nA)
DSS
I
VGS = 0 V
TJ = 125°C
100°C
10
25°C
1
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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MTP2P50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
known as the plateau voltage, V
remains virtually constant at a level
GS
. Therefore, rise and fall
SGP
times may be approximated by the following:
t
= Q2 x RG/(VGG − V
r
tf = Q2 x RG/V
GSP
GSP
)
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
RG = the gate drive resistance
and Q
and V
2
are read from the gate charge curve.
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
t
d(off)
= RG C
= RG C
In [VGG/(V
iss
In (VGG/V
iss
GG
GSP
− V
)
GSP
)]
The capacitance (C
) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
on−state when calculating t
and is read at a voltage corresponding to the
d(on)
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
1800
1600
1400
1200
1000
C, CAPACITANCE (pF)
VDS = 0 V
C
iss
800
600
C
rss
400
200
0
10 5 0 5 10 15 20 25
V
GS
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VGS = 0 V
C
rss
V
DS
C
iss
C
oss
Figure 7a. Capacitance Variation
TJ = 25°C
C, CAPACITANCE (pF)
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4
1000
VGS = 0 V
T
= 25°C
J
100
10
1
10 100 1000
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
C
iss
C
oss
C
rss
Figure 7b. High Voltage Capacitance
Variation
Page 5
MTP2P50E
, GATE‐TO‐SOURCE VOLTAGE (VOLTS)
GS
V
12
10
8
Q
1
6
4
2
Q
0
0
2
3
4 68 10 121416 1820
Q
T
Q
T
Q
2
, TOTAL CHARGE (nC)
V
GS
ID = 2 A
T
= 25°C
J
V
DS
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
2
VGS = 0 V
T
= 25°C
1.6
1.2
J
300
250
200
150
100
50
0
DS
V
, DRAIN‐TO‐SOURCE VOLTAGE (VOLTS)
1000
VDD = 250 V
I
= 2 A
D
= 10 V
V
GS
T
= 25°C
J
100
t, TIME (ns)
10
1 10 100
RG, GATE RESISTANCE (OHMS)
t
d(off)
t
f
t
d(on)
t
r
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
0.8
0.4
, SOURCE CURRENT (AMPS)
S
I
0
0.6 1 1.4 1.8 2.4
0.8 1.2 1.6
, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
V
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain−to−source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
temperature and a case temperature (T
) of 25°C. Peak
C
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance−General
Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I
) nor rated voltage (V
DM
transition time (t
r,tf
) do not exceed 10 ms. In addition the total
) is exceeded and the
DSS
power averaged over a complete switching cycle must not
exceed (T
J(MAX)
− TC)/(R
).
JC
q
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
2 2.2
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I
continuous current (I
), the energy rating is specified at rated
DM
), in accordance with industry
D
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous I
can safely be
D
assumed to equal the values indicated.
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Page 6
MTP2P50E
SAFE OPERATING AREA
10
VGS = 20 V
SINGLE PULSE
TC = 25°C
10 ms
80
60
1
100 ms
1 ms
0.1
, DRAIN CURRENT (AMPS)
D
I
R
DS(on)
10 ms
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1 10 1000
1 100 150
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
V
DS
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
dc
40
20
AVALANCHE ENERGY (mJ)
, SINGLE PULSE DRAIN-TO-SOURCE
AS
E
0
25 50 75 100 125
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1
D = 0.5
0.2
0.1
P
0.1
0.05
0.02
0.01
r(t), NORMALIZED EFFECTIVE
SINGLE PULSE
TRANSIENT THERMAL RESISTANCE
0.01
1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01
(pk)
t
1
t
2
DUTY CYCLE, D = t1/t
R
(t) = r(t) R
q
JC
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
T
- TC = P
J(pk)
2
(pk)
1
R
t, TIME (s)
ID = 2 A
(t)
q
JC
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
t
a
b
TIME
t
p
0.25 I
S
I
S
Figure 14. Diode Reverse Recovery Waveform
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MTP2P50E
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
SEATING
−T−
PLANE
B
4
Q
123
F
T
A
U
C
S
H
K
Z
L
V
R
J
G
D
N
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM MIN MAX MIN MAX
A 0.570 0.620 14.48 15.75
B 0.380 0.405 9.66 10.28
C 0.160 0.190 4.07 4.82
D 0.025 0.035 0.64 0.88
F 0.142 0.161 3.61 4.09
G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93
J 0.014 0.025 0.36 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33
Q 0.100 0.120 2.54 3.04
R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
V 0.045 --- 1.15 ---
Z --- 0.080 --- 2.04
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERSINCHES
E−FET is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MTP2P50E/D
7
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