Datasheet MTP2311N3 Datasheet (CYStech) [ru]

Page 1
CYStech Electronics Corp.
-60V P-CHANNEL Enhancement Mode MOSFET
Spec. No. : C733N3 Issued Date : 2011.12.27 Revised Date : Page No. : 1/8
MTP2311N3
Features
Low gate charge
Compact and low profile SOT-23 package
Advanced trench process technology
High density cell design for ultra low on resistance
Pb-free lead plating package
ID -3.5A RDSON@VGS=-10V, ID=-2A
RDSON@VGS=-4.5V,ID=-1.7A
Symbol Outline
MTP2311N3
BVDSS -60V
72mΩ(typ) 98mΩ(typ)
SOT-23
D
GGate SSource DDrain
G
S
Absolute Maximum Ratings (Ta=25°C)
Parameter
Drain-Source Voltage VDS -60 V Gate-Source Voltage VGS ±20 V
Continuous Drain Current @ TA=25°C (Note 3) Continuous Drain Current @ TA=100°C (Note 3) Pulsed Drain Current (Notes 1, 2) IDM -14 A
Maximum Power Dissipation (Note 3)
Linear Derating Factor
Operating Junction and Storage Temperature Range Tj ; Tstg -55~+150
Note : 1. Pulse width limited by maximum junction temperature.
2. Pulse width 300μs, duty cycle≤2%.
3. Surface mounted on 1 in² copper pad of FR-4 board; 270°C/W when mounted on minimum copper pad
Symbol Limits Unit
ID
PD 1.38 W
0.01
-3.5 A
-2.2 A
W/°C
°C
Page 2
Thermal Performance
Parameter Symbol Limit Unit
CYStech Electronics Corp.
Spec. No. : C733N3 Issued Date : 2011.12.27 Revised Date : Page No. : 2/8
Thermal Resistance, Junction-to-Ambient(PCB mounted) Rth,ja 90
Note : Surface mounted on 1 in² copper pad of FR-4 board; 270°C/W when mounted on minimum copper pad
Electrical Characteristics (Tj=25°C, unless otherwise noted)
Symbol Min. Typ. Max. Unit Test Conditions
Static
BV
BV
V
*R
Dynamic
Source-Drain Diode
-60 - - V VGS=0, ID=-250μA
DSS
/Tj - 0.04 -
DSS
-1.0 -1.8 -3.0 V VDS=VGS, ID=-250μA
GS(th)
±
I
- -
GSS
I
DSS
- - -1 VDS=-48V, VGS=0
- - -25
100
V/°C Reference to 25°C, ID=-1mA
V
nA
μA
=±20V, VDS=0
GS
VDS=-48V, VGS=0 (Tj=70
- 72 90 ID=-2A, VGS=-10V
DS(ON)
- 98 120
mΩ
ID=-1.7A, VGS=-4.5V
*GFS - 5.8 - S VDS=-5V, ID=-3A
Ciss - 962 -
Coss - 56 -
pF VDS=-20V, VGS=0, f=1MHz
Crss - 40 -
t
- 5.9 -
d(ON)
V
=-20V, ID=-1A, VGS=-10V
tr - 5.7 -
t
- 19.2 -
d(OFF)
ns
DS
RG=6Ω
tf - 6 -
Qg - 11 -
Qgs - 3.4 -
nC V
=-30V, ID=-3.5A, VGS=-10V
DS
Qgd - 3.4 -
*IS - - -3.5
*ISM - - -14 A
*VSD - - -1.3 V VGS=0V, IF=IS
Trr - 12 - ns
Qrr - 7 - nC
VGS=0V, IF=-3.5A, dI/dt=100A/μs
*Pulse Test : Pulse Width ≤300μs, Duty Cycle≤2%
°C)
°C/W
Ordering Information
Device Package Shipping Marking
MTP2311N3
(Pb-free lead plating package)
SOT-23
3000 pcs / Tape & Reel 2311
Page 3
CYStech Electronics Corp.
V
V
GS
V
Typical Characteristics
Spec. No. : C733N3 Issued Date : 2011.12.27 Revised Date : Page No. : 3/8
Typical Output Characteristics
20
15
10
Drain Current (A)
,
D
-I
1000
100
Resistance(mΩ)
, Static Drain-Source On-State
DS( on )
R
10V 9V 8V 7V 6V
4.5
5
0
012345
Drain-Source Voltage(V)
-V
,
DS
Static Drain-Source On-State resistance vs Drain Current
VGS=-3.5V
VGS=-3V
VGS=-4.5V
10
0.001 0.01 0.1 1 10
-I
, Drain Current(A)
D
-VGS=4V
-VGS=3.5V
-VGS=3
-VGS=2.5V
VGS=-4
VGS=-10V
Brekdown Voltage vs Ambient Temperature
80
75
70
(V)
65
60
, Drain-Source Breakdown Voltage
DSS
55
-BV
ID=-250μA,
=0V
V
50
-75 -50 -25 0 25 50 75 100 125 150 175 Tj, Junction Temperature(°C)
Reverse Drain Current vs Source-Drain Voltage
1.2
VGS=0V
1
Tj=25°C
0.8
0.6
Tj=150°C
, Source-Drain Voltage(V)
SD
0.4
-V
0.2 024681
, Reverse Drain Current (A)
-I
DR
0
Drain-Source On-State Resistance vs Junction Tempearture
160 150 140 130
VGS=-4.5V, ID=-1.7A
120 110 100
90 80 70
Resistance(mΩ)
60
VGS=-10V, ID=-2A
50 40 30 20
-60 -20 20 60 100 140 180 Tj, Junction Temperature(°C)
, Static Drain-Source On-
R
DS( ON)
Static Drain-Source On-State Resistance vs Gate-Source
Voltage
200
180
160
140
120
100
ID=-2A I
=-1.7A
D
80
60
State Resistance(mΩ)
40
20
0
024681
-V
, Gate-Source Voltage(V)
GS
0
, Static Drain-Source On-State
DS( ON)
R
Page 4
CYStech Electronics Corp.
μ

Typical Characteristics(Cont.)

Spec. No. : C733N3 Issued Date : 2011.12.27 Revised Date : Page No. : 4/8
Capacitance vs Drain-to-Source Voltage
10000
1000
100
Capacitance---(pF)
Crss
10
0.1 1 10 100 , Drain-Source Voltage(V)
-V
DS
Forward Transfer Admittance vs Drain Current
10
1
Ciss
C
oss
Threshold Voltage vs Junction Tempearture
2.2
2
1.8
1.6
1.4
,Threshold Voltage-(V)
1.2
GS( th)
-V 1
0.8
-60 -40 -20 0 20 40 60 80 100 120 140 160
Tj, Junction Temperature(°C)
Gate Charge Characteristics
10
8
VDS=-30V
6
=-3.5A
I
D
ID=-250μA
0.1
, Forward Transfer Admittance-(S)
FS
G
0.01
0.001 0.01 0.1 1 10
-I
, Drain Current(A)
D
Maximum Safe Operating Area
100
10
1
, Drain Current (A)
D
-I
0.1
0.01
TA=25°C, Tj=150°C
=-10V
V
GS
Single Pulse
0.01 0.1 1 10 100
-V
, Drain-Source Voltage(V)
DS
VDS=-10V Pulsed Ta=25°C
100
10ms
100m
DC
1ms
10μs
, Gate-Source Voltage(V)
GS
-V
, Maximum Drain Current(A)
D
I
4
2
0
02468101214
Qg, Total Gate C harge(nC)
Maximum Drain Current vs JunctionTemperature
4.5
4
3.5
3
2.5
2
1.5
1
0.5
TA=25°C, VGS=-10V
0
25 50 75 100 125 150 175
Tj, Junction Temperature(°C)
Page 5
CYStech Electronics Corp.
p
Typical Characteristics(Cont.)
Power Derating Curve
1.6
Spec. No. : C733N3 Issued Date : 2011.12.27 Revised Date : Page No. : 5/8
1.4
1.2
1
0.8
0.6
, Power Dissipation(W)
D
0.4
P
0.2
0
0 20 40 60 80 100 120 140 160
T
1
D=0.5
0.2
0.1
0.1
Resistance
0.05
Mounted on FR-4 board
²
with 1 in
, Ambient Temperature(℃)
A
ad area
Transient Thermal Response Curves
JA
1.R
(t)=r(t)*R
θ
2.Duty Factor, D=t1/t
3.TJM-TA=PDM*R
4.R
θJA
=270
°C/W
θJA
2
JA
(t)
θ
0.02
0.01
r(t), Norma lized Effec tiveTra nsient The rmal
0.01
1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02
Single Pulse
t
, Square Wave Pulse Duration(s)
1
Page 6
Reel Dimension
CYStech Electronics Corp.
Spec. No. : C733N3 Issued Date : 2011.12.27 Revised Date : Page No. : 6/8
Carrier Tape Dimension
Page 7
CYStech Electronics Corp.

Recommended wave soldering condition

Product Peak Temperature Soldering Time
Pb-free devices

Recommended temperature profile for IR reflow

260 +0/-5 °C
Spec. No. : C733N3 Issued Date : 2011.12.27 Revised Date : Page No. : 7/8
5 +1/-1 seconds
Profile feature Sn-Pb eutectic Assembly
Average ramp-up rate
(Tsmax to Tp)
Preheat
Temperature Min(T
S min)
Temperature Max(TS max)
Time(ts min to ts max)
Time maintained above:
Temperature (TL)
Time (tL)
Peak Temperature(TP)
Time within 5°C of actual peak
temperature(tp)
Ramp down rate
Time 25 °C to peak temperature
Note : All temperatures refer to topside of the package, measured on the package body surface.
3°C/second max. 3°C/second max.
100°C 150°C
60-120 seconds
183°C
60-150 seconds
240 +0/-5 °C 260 +0/-5 °C
10-30 seconds 20-40 seconds
6°C/second max. 6°C/second max.
6 minutes max. 8 minutes max.
Pb-free Assembly
150°C 200°C
60-180 seconds
217°C
60-150 seconds
Page 8
SOT-23 Dimension
CYStech Electronics Corp.
Spec. No. : C733N3 Issued Date : 2011.12.27 Revised Date : Page No. : 8/8
Marking:
DIM
A
L
3
S
B
1
V
C
D
G
Inches
2
H
Millimeters Inches Millimeters
Min. Max. Min. Max.
Style: Pin 1.Gate 2.Source 3.Drain
K
J
DIM
Min. Max. Min. Max.
TE
2311
3-Lead SOT-23 Plastic
Surface Mounted Package
CYStek Package Code: N3
*: Typical
A 0.1102 0.1204 2.80 3.04 J 0.0034 0.0070 0.085 0.177 B 0.0472 0.0630 1.20 1.60 K 0.0128 0.0266 0.32 0.67 C 0.0335 0.0512 0.89 1.30 L 0.0335 0.0453 0.85 1.15 D 0.0118 0.0197 0.30 0.50 S 0.0830 0.1161 2.10 2.95 G 0.0669 0.0910 1.70 2.30 V 0.0098 0.0256 0.25 0.65 H 0.0005 0.0040 0.013 0.10
Notes: 1.Controlling dimension: millimeters.
Material:
Lead: Pure tin plated.
Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0.
2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material.
3.If there is any question with packing specification or packing method, please contact your local CYStek sales office.
Important Notice:
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek.
CYStek reserves the right to make changes to its products without notice.
CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems.
CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance.
Page 9
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