Datasheet MTP10N10E Datasheet (Motorola)

1

Motorola TMOS Power MOSFET Transistor Device Data

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N–Channel Enhancement–Mode Silicon Gate

This advanced “E” series of TMOS power MOSFETs is designed
to withstand high energy in the avalanche and commutation
modes. These new energy efficient devices also offer drain–to–
source diodes with fast recovery times. Designed for low voltage,
high speed switching applications in power supplies, converters
and PWM motor controls, these devices are particularly well suited
for b ridge circuits where diode speed a nd commutating safe
operating area are c ritical, a nd offer a dditional safety margin
against unexpected voltage transients.

• Internal Source–to–Drain Diode Designed to Replace External

Zener Transient Suppressor — Absorbs High Energy in the
Avalanche Mode — Unclamped Inductive Switching (UIS)
Energy Capability Specified at 100°C

• Commutating Safe Operating Area (CSOA) Specified for Use

in Half and Full Bridge Circuits

• Source–to–Drain Diode Recovery Time Comparable to a Discrete

Fast Recovery Diode

• Diode is Characterized for Use in Bridge Circuits

MAXIMUM RATINGS

(TC = 25°C unless otherwise noted)

Rating

Symbol Value Unit

Drain–Source Voltage V

DSS

100 Vdc

Drain–Gate Voltage (RGS = 1.0 MΩ) V

DGR

100 Vdc

Gate–Source Voltage V

GS

±20 Vdc

Drain Current — Continuous

Drain Current — Pulsed

I

D

I

DM

10
25

Adc

Total Power Dissipation

Derate above 25°C

P

D

75

0.6

Watts

W/°C

Operating and Storage Temperature Range TJ, T

stg

–65 to 150 °C

THERMAL CHARACTERISTICS

Thermal Resistance — Junction to Case

Thermal Resistance — Junction to Ambient°

R

θJC

R

θJA

1.67

62.5

°C/W

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 5 seconds T

L

275 °C

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics— are given to facilitate “worst case” design.

Designer’s is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

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SEMICONDUCTOR TECHNICAL DATA



TMOS POWER FETs

10 AMPERES

100 VOLTS

R

DS(on)

= 0.25 OHM



D

S

G

CASE 221A–06, Style 5

TO–220AB

 Motorola, Inc. 1996

MTP10N10E

2

Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS

(T

C

= 25°C unless otherwise noted)

Characteristic

Symbol Min Max Unit

OFF CHARACTERISTICS

Drain–Source Breakdown Voltage

(VGS = 0, ID = 0.25 mA)

V

(BR)DSS

100 — Vdc

Zero Gate Voltage Drain Current

(VDS = Rated V

DSS

, VGS = 0)

(VDS = 0.8 Rated V

DSS

, VGS = 0, TJ = 125°C)

I

DSS

—
—

10
80

µA

Gate–Body Leakage Current, Forward (V

GSF

= 20 Vdc, VDS = 0) I

GSSF

— 100 nAdc

Gate–Body Leakage Current, Reverse (V

GSR

= 20 Vdc, VDS = 0) I

GSSR

— 100 nAdc

ON CHARACTERISTICS*

Gate Threshold Voltage

(VDS = VGS, ID = 1.0 mA)
TJ = 100°C

V

GS(th)

2.0

1.5

4.5

4.0

Vdc

Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 5.0 Adc) R

DS(on)

— 0.25 Ohm

Drain–Source On–Voltage (VGS = 10 V)

(ID = 10 Adc)

°

(ID = 5.0 Adc, TJ = 100°C)

V

DS(on)

—
—

2.7

2.4

Vdc

Forward Transconductance (VDS = 15 V, ID = 5.0 A)

g

FS

4.0 — mhos

DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS

Unclamped Drain–to–Source Avalanche Energy See Figures 14 and 15

(ID = 25 A, VDD = 25 V, TC = 25°C, Single Pulse, Non–repetitive)
(ID = 10 A, VDD = 25 V, TC = 25°C, P.W. ≤ 200 µs, Duty Cycle ≤ 1%)
(ID = 4.0 A, VDD = 25 V, TC = 100°C, P.W. ≤ 200 µs, Duty Cycle ≤ 1%)

W

DSR

—
—
—

60

100

40

mJ

DYNAMIC CHARACTERISTICS

Input Capacitance

C

iss

— 600 pF

Output Capacitance

(VDS = 25 V, VGS = 0,

f = 1.0 MHz)

C

oss

— 400

Reverse Transfer Capacitance

See Figure 16

C

rss

— 100

SWITCHING CHARACTERISTICS* (TJ = 100°C)

Turn–On Delay Time

t

d(on)

— 50 ns

Rise Time

t

r

— 80

Turn–Off Delay Time

RG = 50 Ω)

See Figure 9

t

d(off)

— 100

Fall Time t

f

— 80

Total Gate Charge

Q

g

15 (Typ) 30 nC

Gate–Source Charge

(VDS = 0.8 Rated V

DSS

,

ID = Rated ID, VGS = 10 V)

Q

gs

8.0 (Typ) —

Gate–Drain Charge

See Figures 17 and 18

Q

gd

7.0 (Typ) —

SOURCE–DRAIN DIODE CHARACTERISTICS*

Forward On–Voltage

V

SD

1.4 (Typ) 1.7 Vdc

Forward Turn–On Time

(IS = Rated I

D

V

= 0)

t

on

Limited by stray inductance

Reverse Recovery Time

VGS = 0)

t

rr

70 (Typ) — ns

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from the contact screw on tab to center of die)″
(Measured from the drain lead 0.25″ from package to center of die)

L

d

3.5 (Typ)

4.5 (Typ)

—
—

nH

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

L

s

7.5 (Typ) —

*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.

(VDD = 25 V, ID = 5.0 A,

MTP10N10E

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Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics

TJ, JUNCTION TEMPERATURE (°C)

Figure 2. Gate–Threshold Voltage Variation

With Temperature

VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 3. Transfer Characteristics

TJ, JUNCTION TEMPERATURE (°C)

Figure 4. Breakdown Voltage Variation

With Temperature

ID, DRAIN CURRENT (AMPS)

Figure 5. On–Resistance versus Drain Current

TJ, JUNCTION TEMPERATURE (°C)

Figure 6. On–Resistance Variation

With Temperature

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE (OHMS)

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE

(NORMALIZED)

I

D

, DRAIN CURRENT (AMPS)

V

GS(th)

, GATE THRESHOLD VOLTAGE (NORMALIZED)

V

BR(DSS)

, DRAIN–TO–SOURCE BREAKDOWN VOLTAGE

(NORMALIZED)

20

16

12

8

4

201612840

1.2

1.1

1

0.9

0.8

–50 –25 0 25 50 75 100 125 150

20

16

12

8

4

0

1086420

2

1.6

1.2

0.8

0.4

0

–50 0 50 100 150 200

0.5

0.4

0.3

0.2

0.1

1086420

2

1.6

1.2

0.8

0.4

0

–50 0 50 100 150

TJ = 25°C

8 V

7 V

6 V

5 V

VDS = V

GS

ID = 1 mA

VDS = 15 V

TJ = –55°C

+25°C

100°C

VGS = 0 V
ID = 0.25 mA

TJ = 100°C

25°C
–55°C

VGS = 10 V

VGS = 10 V
ID = 5 mA

I

D

, DRAIN CURRENT (AMPS)

VGS = 10 V

4 V

0.7

VDS = 10 V

200

MTP10N10E

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Motorola TMOS Power MOSFET Transistor Device Data

SAFE OPERATING AREA INFORMATION

I

D

, DRAIN CURRENT (AMPS)

I

D

, DRAIN CURRENT (AMPS)

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 7. Maximum Rated Forward Biased

Safe Operating Area

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 8. Maximum Rated Switching

Safe Operating Area

0 20 40 60 80

0

40

100

R

DS(on)

LIMIT
THERMAL LIMIT
PACKAGE LIMIT

10

VGS = 20 V
SINGLE PULSE
TC = 25°C

1

1

30

dc

10 µs

1 ms

10 ms

30

10

100

20

10

3

0.3

100 µs

TJ ≤ 150°C

FORWARD BIASED SAFE OPERATING AREA

The FBSOA curves define the maximum drain–to–source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25°C and a maxi­mum junction temperature of 150°C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, “Transient Thermal Resistance–General Data
and Its Use” provides detailed instructions.

SWITCHING SAFE OPERATING AREA

The switching safe operating area (SOA) of Figure 8 is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, IDM and the breakdown voltage, V

(BR)DSS

. The
switching SOA shown in Figure 8 is applicable for both turn–
on and turn–off of the devices for switching times less than
one microsecond.

The power averaged over a complete switching cycle must

be less than:

T

J(max)

– T

C

R

θJC

Figure 9. Resistive Switching Time

versus Gate Resistance

t, TIME (ns)

RG, GATE RESISTANCE (OHMS)

VDD = 25 V
ID = 5 A
VGS = 10 V
TJ = 25

°

C

t

f

t

r

t

d(off)

t

d(on)

1K1

1K

1

2

3

5

7

10

20

30

50

70

100

200

300

500

2 3 5 10 20 30 50 100 200 300 500

Figure 10. Thermal Response

r(t), TRANSIENT THERMAL RESISTANCE

(NORMALIZED)

R

θ

JC

(t) = r(t) R

θ

JC

R

θ

JC

= 1.67

°

C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t

1

T

J(pk)

– TC = P

(pk)

R

θ

JC

(t)

P

(pk)

t

1

t

2

DUTY CYCLE, D = t1/t

2

t, TIME (ms)

1

0.01

D = 0.5

0.05

0.01

SINGLE PULSE

0.01

0.03

0.02

0.05

0.1

0.2

0.3

0.5

0.02 0.05 0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1000

0.7

0.07

0.03 0.3 3 30 300

0.1

0.2

Figure 12. Commutating Safe Operating Area (CSOA)

0 20 40 60 80

30

25

20

15

0

10

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

+

+

–

Figure 13. Commutating Safe Operating Area

Test Circuit

V

R

V

GS

I

FM

20 V

R

GS

DUT

I

S

L

i

VR = 80% OF RATED V

DS

V

dsL

= Vf + Li

⋅

dls/dt

+

–

dIs/dt ≤ 400 A/µs

100

120

I

S

, SOURCE CURRENT (AMPS)

5

Figure 14. Unclamped Inductive Switching

Test Circuit

Figure 15. Unclamped Inductive Switching

Waveforms

t

L

V

DS

I

D

V

DD

t

P

V

(BR)DSS

V

DD

I

D(t)

C

4700

µ

F

250 V

R

GS

50

Ω

I

O

V

ds(t)

t, (TIME)

W

DSR

+

ǒ

1
2

L I

O

2

Ǔ

ǒ

V

(BR)DSS

V

(BR)DSS

– V

DD

Ǔ

V

DS

MTP10N10E

5

Motorola TMOS Power MOSFET Transistor Device Data

COMMUTATING SAFE OPERATING AREA (CSOA)

The Commutating Safe Operating Area (CSOA) of Figure
12 d efines t he limits of safe o peration for commutated
source-drain current versus re-applied drain voltage when
the source-drain diode has undergone forward bias. The
curve shows the limitations of IFM and peak VDS for a given
rate of change of source current. It is applicable when wave­forms similar to those of Figure 11 are present. Full or half­bridge PWM DC motor controllers are common applications
requiring CSOA data.

Device stresses increase with increasing rate of change of
source current so dIs/dt is specified with a maximum value.
Higher values of dIs/dt require an appropriate derating of IFM,
peak VDS or both. Ultimately dIs/dt is limited primarily by de­vice, package, and circuit impedances. Maximum device
stress occurs during trr as the diode goes from conduction to
reverse blocking.

V

DS(pk)

is the peak drain–to–source voltage that the device
must sustain during commutation; IFM is the maximum for­ward source-drain diode current just prior to the onset of
commutation.

VR is specified at 80% of V

(BR)DSS

to ensure that the

CSOA stress is maximized as IS decays from IRM to zero.

RGS should be minimized during commutation. TJ has only

a second order effect on CSOA.

Stray inductances in Motorola’s test circuit are assumed to
be practical minimums. dVDS/dt in excess of 10 V/ns was at­tained with dIs/dt of 400 A/µs.

15 V

V

GS

0

90%

I

FM

dls/dt

I

S

10%

t

rr

I

RM

t

on

V

DS

V

f

V

dsL

dVDS/dt

V

DS(pk)

MAX. CSOA
STRESS AREA

V

R

0.25 I

RM

Figure 11. Commutating Waveforms

MTP10N10E

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Motorola TMOS Power MOSFET Transistor Device Data

GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 16. Capacitance Variation

C, CAPACITANCE (pF)

V

GS

V

DS

0

C

iss

C

oss

C

rss

C

iss

1250

1000

750

500

30201001020

Figure 17. Gate Charge versus

Gate–To–Source Voltage

QG, TOTAL GATE CHARGE (nC)

10

0

0 4

8

6

4

2

8 12 16 20

250

Figure 18. Gate Charge Test Circuit

V

in

15 V

100 k

47 k

2N3904

2N3904

1 mA

+18 V V

DD

10 V

100 k

0.1

µ

F

100

FERRITE

BEAD

DUT

SAME
DEVICE TYPE
AS DUT

Vin = 15 Vpk; PULSE WIDTH

≤

100 µs, DUTY CYCLE ≤ 10%

TJ = 25°C

47 k

VDS = 30 V

50 V

V

GS

, GATE–TO–SOURCE VOLTAGE (VOLTS)

80 V

TJ = 25°C

ID = RATED I

D

C

oss

MTP10N10E

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Motorola TMOS Power MOSFET Transistor Device Data

PACKAGE DIMENSIONS

CASE 221A–06

ISSUE Y

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.

STYLE 5:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.570 0.620 14.48 15.75
B 0.380 0.405 9.66 10.28
C 0.160 0.190 4.07 4.82
D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73
G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33
Q 0.100 0.120 2.54 3.04
R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
V 0.045 ––– 1.15 –––
Z ––– 0.080 ––– 2.04

B

Q

H

Z

L

V

G

N

A

K

F

1 2 3

4

D

SEATING
PLANE

–T–

C

S

T

U

R
J

MTP10N10E

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Motorola TMOS Power MOSFET Transistor Device Data

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different
applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does
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MTP10N10E/D

*MTP10N10E/D*

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