Datasheet mtd6n15-d Datasheet

Page 1

MTD6N15

l l

Power Field Effect Transistor DPAK for Surface Mount

N−Channel Enhancement−Mode Silicon Gate

This TMOS Power FET is designed for high speed, low loss power switching applications such as switching regulators, converters, solenoid and relay drivers.

Features

• Silicon Gate for Fast Switching Speeds

• Low R

• Rugged — SOA is Power Dissipation Limited

• Source−to−Drain Diode Characterized for Use With Inductive Loads

• Low Drive Requirement — V

• Surface Mount Package on 16 mm Tape

• Pb−Free Package is Available

— 0.3 W Max

DS(on)

= 4.0 V Max

GS(th)

(BR)DSS

150 V

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MAX

DS(on)

0.3 W

N−CHANNEL

ID MAXV

6.0 A

MAXIMUM RATINGS

Rating Symbol Value Unit

Drain−Source Voltage V Drain−Gate Voltage (RGS = 1.0 MW) Gate−Source Voltage

Drain Current − Continuous

Drain Current − Pulsed

Total Power Dissipation @ TC = 25°C Derate above 25°C

Total Power Dissipation @ TA = 25°C Derate above 25°C (Note 1)

Total Power Dissipation @ TA = 25°C (Note 1) Derate above 25°C (Note 2)

Operating and Storage Junction Temperature Range

− Continuous

− Non−Repetitive (tp ≤ 50 ms)

TJ, T

DSS DGR

GSM

stg

150 Vdc 150 Vdc

± 20 ± 40

6.0 20

0.16

1.25

0.01

1.75

0.014

− 65 to +150 °C

Vdc Vpk

Adc

W/°C

THERMAL CHARACTERISTICS

Characteristic Symbol Value Unit

Thermal Resistance

− Junction−to−Case

− Junction−to−Ambient (Note 1)

− Junction−to−Ambient (Note 2)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. When surface mounted to an FR4 board using the minimum recommended pad size.

2. When surface mounted to an FR4 board using 0.5 sq. in. drain pad size.

July, 2006 − Rev. 4

6.25 100

71.4

°C/W

1 Publication Order Number:

CASE 369C

DPAK

(Surface Mount)

STYLE 2

MARKING DIAGRAM

& PIN ASSIGNMENTS

4 Drain

YWWT6N15G

Gate

Drain

Y = Year WW = Work Week 6N15 = Device Code G = Pb−Free Package

Source

ORDERING INFORMATION

Device Package Shipping

MTD6N15T4 DPAK 2500/Tape & Ree MTD6N15T4G DPAK

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

2500/Tape & Ree

†

MTD6N15/D

Page 2

MTD6N15

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

Characteristic Symbol Min Max Unit

OFF CHARACTERISTICS

Drain−Source Breakdown Voltage (V

= 0 Vdc, ID = 0.25 mAdc) V

Zero Gate Voltage Drain Current

(VDS = Rated V

TJ = 125°C Gate−Body Leakage Current, Forward (V Gate−Body Leakage Current, Reverse (V

, VGS = 0 Vdc)

DSS

= 20 Vdc, VDS = 0) I

GSF

= 20 Vdc, VDS = 0) I

GSR

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc)

TJ = 100°C Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 3.0 Adc) R Drain−Source On−Voltage (VGS = 10 Vdc)

(ID = 6.0 Adc)

(ID = 3.0 Adc, TJ = 100°C) Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance Output Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz)

(See Figure 11)

Reverse Transfer Capacitance C

SWITCHING CHARACTERISTICS* (TJ = 100°C)

Turn−On Delay Time Rise Time t Turn−Off Delay Time t

= 25 Vdc, ID = 3.0 Adc, R

(See Figures 13 and 14)

= 50 W)

Fall Time t Total Gate Charge Gate−Source Charge Q Gate−Drain Charge Q

(VDS = 0.8 Rated V

ID = Rated ID, VGS = 10 Vdc)

DSS

(See Figure 12)

SOURCE−DRAIN DIODE CHARACTERISTICS*

Forward On−Voltage Forward Turn−On Time t

(IS = 6.0 Adc, di/dt = 25 A/ms, VGS = 0 Vdc)

Reverse Recovery Time t

3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.

(BR)DSS

DSS

GSSF

GSSR

GS(th)

DS(on)

iss

oss rss

d(on)

d(off)

SD on

150 − Vdc

mAdc

−

100

− 100 nAdc

2.0

1.5

− 0.3

4.5

4.0

Vdc

−

1.8

1.5

2.5 − mhos

− 1200 pF

− 500

− 120

− 50 ns

− 180

− 200

− 100

15 (Typ) 30 nC

8.0 (Typ) −

7.0 (Typ) −

1.3 (Typ) 2.0 Vdc Limited by stray inductance

325 (Typ) − ns

, POWER DISSIPATION (WATTS)

2.5

1.5

0.5

TAT

T, TEMPERATURE (°C)

150125100755025

Figure 1. Power Derating

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Page 3

MTD6N15

TYPICAL ELECTRICAL CHARACTERISTICS

, DRAIN CURRENT (AMPS)

10 V

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

9 V

TJ = 25°C

8 V

7 V

6 V

5 V

Figure 2. On−Region Characteristics

VDS = 10 V

TJ = 25°C

3.6

VDS = V

3.2

2.8

2.4

, GATE THRESHOLD VOLTAGE (VOLTS)

GS(th)

6050403020100

−50 0 50 100 150 TJ, JUNCTION TEMPERATURE (°C)

ID = 1 mA

Figure 3. Gate−Threshold Voltage Variation

With Temperature

VGS = 0 V ID = 0.25 mA

1.6

1.2

, DRAIN CURRENT (AMPS)

0.30

0.25

0.20

0.15

0.10

0.05

, DRAIN−TO−SOURCE RESISTANCE (OHMS)

DS(on)

100°C

−55°C

46810

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 4. Transfer Characteristics

VGS = 10 V

TJ = 100°C

25°C

−55°C

ID, DRAIN CURRENT (AMPS)

0.8

(NORMALIZED)

0.4

, DRAIN−TO−SOURCE BREAKDOWN VOLTAGE

−50 0 50 100 150 200

(BR)DSS

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. Breakdown Voltage Variation

With Temperature

VGS = 10 V ID = 3 A

1.6

1.2

0.8

(NORMALIZED)

, DRAIN−TO−SOURCE RESISTANCE

0.4

DS(on)

201612840

−50 0 50 100 150 200 TJ, JUNCTION TEMPERATURE (°C)

Figure 6. On−Resistance versus Drain Current

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Figure 7. On−Resistance Variation

With Temperature

Page 4

MTD6N15

SAFE OPERATING AREA

0.5

, DRAIN CURRENT (AMPS)

0.2

0.1

0.05

0.03

100 ms

1 ms

10 ms

LIMIT

DS(on)

THERMAL LIMIT PACKAGE LIMIT

TC = 25°C VGS = 20 V SINGLE PULSE

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

10 ms

3002001007050302010753210.3 0.5 0.7

Figure 8. Maximum Rated Forward Biased

Safe Operating Area

FORWARD BIASED SAFE OPERATING AREA

The FBSOA curves define the maximum drain−to−source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25°C and a maximum junction temperature of 150 °C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. Motorola Application Note, AN569, “Transient Thermal Resistance−General Data and Its Use” provides detailed instructions.

, DRAIN CURRENT (AMPS)

0 20 40 60 80 100 120 140 160

TJ ≤ 150°C

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 9. Maximum Rated Switching

Safe Operating Area

SWITCHING SAFE OPERATING AREA

The switching safe operating area (SOA) of Figure 9 is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, V

(BR)DSS

The switching SOA shown in Figure 8 is applicable for both turn−on and turn−of f of the devices for switching times less than one microsecond.

The power averaged over a complete switching cycle must be less than:

− T

J(max)

0.7

0.5

0.3

0.2

0.1

0.07

0.05

r(t), EFFECTIVE TRANSIENT

0.03

0.02

THERMAL RESISTANCE (NORMALIZED)

0.01

D = 0.5

0.2

0.1

0.05

0.02

0.01 SINGLE PULSE

(pk)

DUTY CYCLE, D = t1/t

t, TIME OR PULSE WIDTH (ms)

Figure 10. Thermal Response

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(t) = r(t) R

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN READ TIME AT t T

J(pk)

(pk)

(t) = 6.25°C/W MAX

− TC = P

(t)

10000.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1 2 3 5 10 20 50 100 200 500

Page 5

MTD6N15

2000

1600

1200

800

C, CAPACITANCE (pF)

400

VDS = 0

15 30 35

515

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 11. Capacitance Variation

PULSE GENERATOR

gen

50 W

z = 50 W

DUT

50 W

TJ = 25°C VGS = 0

TJ = 25°C ID = 6 A

iss

oss

rss

2520100510

, GATE SOURCE VOLTAGE (VOLTS)

RESISTIVE SWITCHING

d(on)

out

OUTPUT, V INVERTED

INPUT, V

out

10%

75 V

120 V

VDS = 50 V

12 16 20

Qg, TOTAL GATE CHARGE (nC)

Figure 12. Gate Charge versus

Gate−To−Source Voltage

d(off)

90%

10%

50%

off

50%

90%90%

Figure 13. Switching Test Circuit

PULSE WIDTH

Figure 14. Switching Waveforms

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Page 6

MTD6N15

PACKAGE DIMENSIONS

DPAK

CASE 369C−01

ISSUE O

SEATING

−T−

PLANE

123

2 PL

0.13 (0.005) T

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

A 0.235 0.245 5.97 6.22 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88 E 0.018 0.023 0.46 0.58 F 0.037 0.045 0.94 1.14 G 0.180 BSC 4.58 BSC H 0.034 0.040 0.87 1.01 J 0.018 0.023 0.46 0.58 K 0.102 0.114 2.60 2.89 L 0.090 BSC 2.29 BSC R 0.180 0.215 4.57 5.45 S 0.025 0.040 0.63 1.01 U 0.020 −−− 0.51 −−− V 0.035 0.050 0.89 1.27 Z 0.155 −−− 3.93 −−−

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERSINCHES

SOLDERING FOOTPRINT*

6.20

0.244

2.58

0.101

3.0

0.118

5.80

0.228

1.6

0.063

SCALE 3:1

6.172

0.243

inches

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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MTD6N15/D