Datasheet MTB75N03HDL Datasheet (Motorola)

1

Motorola TMOS Power MOSFET Transistor Device Data

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N–Channel Enhancement–Mode Silicon Gate

The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower R

DS(on)

capabilities. This advanced
high–cell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in p ower supplies, converters and PWM m otor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

• Avalanche Energy Specified

• Source–to–Drain Diode Recovery Time Comparable to a

Discrete Fast Recovery Diode

• Diode is Characterized for Use in Bridge Circuits

• I

DSS

and V

DS(on)

Specified at Elevated Temperature

• Ultra Low R

DS(on)

, High–Cell Density, HDTMOS

• Short Heatsink Tab Manufactured — Not sheared

• Specially Designed Leadframe for Maximum Power Dissipation

• Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number

MAXIMUM RATINGS

(TC = 25°C unless otherwise noted)

Rating

Symbol Value Unit

Drain–to–Source Voltage V

DSS

25 Vdc

Drain–to–Gate Voltage (RGS = 1.0 MΩ) V

DGR

25 Vdc

Gate–to–Source Voltage — Continuous

Gate–to–Source Voltage — Non–Repetitive (tp ≤ 10 ms)

V

GS

V

GSM

± 15
± 20

Vdc
Vpk

Drain Current — Continuous

Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)

I

D

I

D

I

DM

75
59

225

Adc

Apk

Total Power Dissipation

Derate above 25°C

Total Power Dissipation @ TA = 25°C (1)

P

D

125

1.0

2.5

Watts

W/°C

Watts
Operating and Storage Temperature Range – 55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 75 Apk, L = 0.1 mH, RG = 25 Ω)

E

AS

280 mJ

Thermal Resistance — Junction to Case

Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)

R

θJC

R

θJA

R

θJA

1.0

62.5
50

°C/W

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T

L

260 °C

(1) When mounted with the minimum recommended pad size.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

E–FET and HDTMOS are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Order this document

by MTB75N03HDL/D



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

D

S

G



TMOS POWER FET

LOGIC LEVEL

75 AMPERES

25 VOLTS

R

DS(on)

= 9 mOHM

Motorola Preferred Device



CASE 418B–02, Style 2

D2PAK

MTB75N03HDL

2

Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS

(TJ = 25°C unless otherwise noted)

Characteristic

Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain–Source Breakdown Voltage (Cpk ≥ 2.0) (3)

(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)

V

(BR)DSS

25 — —

Vdc

mV/°C

Zero Gate Voltage Drain Current

(VDS = 25 Vdc, VGS = 0 Vdc)
(VDS = 25 Vdc, VGS = 0 Vdc, TJ = 125°C)

I

DSS

—
—

—
—

100
500

µAdc

Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 V) I

GSS

— — 100 nAdc

ON CHARACTERISTICS (1)

Gate Threshold Voltage (Cpk ≥ 3.0) (3)

(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)

V

GS(th)

1.0 1.5 2.0

Vdc

mV/°C

Static Drain–Source On–Resistance (Cpk ≥ 2.0) (3)

(VGS = 5.0 Vdc, ID = 37.5 Adc)

R

DS(on)

— 6.0 9.0

mΩ

Drain–Source On–Voltage (VGS = 10 Vdc)

(ID = 75 Adc)
(ID = 37.5 Adc, TJ = 125°C)

V

DS(on)

—
—

—
—

0.68

0.6

Vdc

Forward Transconductance (VDS = 3 Vdc, ID = 20 Adc) g

FS

15 55 — mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

C

iss

— 4025 5635 pF

Output Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

C

oss

— 1353 1894

Reverse Transfer Capacitance

f = 1.0 MHz)

C

rss

— 307 430

SWITCHING CHARACTERISTICS (2)

Turn–On Delay Time

t

d(on)

— 24 48 ns

Rise Time

t

r

— 493 986

Turn–Off Delay Time

VGS = 5.0 Vdc,

RG = 4.7 Ω)

t

d(off)

— 60 120

Fall Time

G

= 4.7 Ω)

t

f

— 149 300

Gate Charge

Q

T

— 61 122 nC

DS

= 24 Vdc, ID = 75 Adc,

Q

1

— 14 28

(VDS = 24 Vdc, ID = 75 Adc,

VGS = 5.0 Vdc)

Q

2

— 33 66

Q

3

— 27 54

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage

(IS = 75 Adc, VGS = 0 Vdc)

(IS = 75 Adc, VGS = 0 Vdc, TJ = 125°C)

V

SD

—
—

0.97

0.87

1.1
—

Vdc

t

rr

— 58 —

S

= 75 Adc,

t

a

— 27 —

(IS = 75 Adc,

dIS/dt = 100 A/µs)

t

b

— 30 —

Reverse Recovery Stored Charge Q

RR

— 0.088 — µC

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.

Cpk =

Max limit – Typ

3 x SIGMA

Reverse Recovery Time

(VDS= 15 Vdc, ID = 75 Adc,

(V

(I

ns

MTB75N03HDL

3

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

Figure 3. On–Resistance versus Drain Current

and Temperature

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

Figure 5. On–Resistance Variation with

Temperature

Figure 6. Drain–to–Source Leakage

Current versus Voltage

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE (OHMS)

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE

(NORMALIZED)

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

I

D

, DRAIN CURRENT (AMPS)

I

D

, DRAIN CURRENT (AMPS)

VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE (OHMS)

ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)

TJ, JUNCTION TEMPERATURE (

°

C) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

I

DSS

, LEAKAGE (nA)

TJ = 25

°C

VDS ≥ 10 V

TJ = 100

°C

25

°C

–55

°C

TJ = 25

°C

VGS = 0 V

VGS = 10 V

VGS = 5 V

VGS = 5 V

VGS = 10 V
ID = 37.5 A

0.4 0.8 1.2 1.6 20 0.2 0.6 1 1.4 1.8

30

60

90

120

150

0

2 2.5 3.5 4 4.51.5

30

60

90

120

150

0

3

30 60 90 120 1500

0.01

0.002

0.008

0.006

0.004

25 50 100 125 1500

0.005

0.006

0.007

0.008

0.009

0.004
75

25 100 150–50 –25 0 50 75 125

0.4

0.8

1.2

1.6

2

0

10 20 300 5 15 25

10

100

1000

10000

1

10 V

100°C

25°C

TJ = 125°C

100°C

25°C

TJ = –55

°C

3.5 V

3 V

4 V

2.5 V

4.5 V

5 V

8 V

6 V

MTB75N03HDL

4

Motorola TMOS Power MOSFET Transistor Device Data

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter­mined by how fast the FET input capacitance can be charged
by current from the generator.

The published capacitance data is difficult to use for calculat­ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I

G(AV)

) can be made from a rudimentary analysis of

the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a resis­tive load, VGS remains virtually constant at a level known as
the plateau voltage, V

SGP

. Therefore, rise and fall times may

be approximated by the following:
tr = Q2 x RG/(VGG – V

GSP

)

tf = Q2 x RG/V

GSP

where
VGG = the gate drive voltage, which varies from zero to V

GG

RG = the gate drive resistance
and Q2 and V

GSP

are read from the gate charge curve.

During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val­ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

= RG C

iss

In [VGG/(VGG – V

GSP

)]

t

d(off)

= RG C

iss

In (VGG/V

GSP

)

The capacitance (C

iss

) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal­culating t

d(on)

and is read at a voltage corresponding to the

on–state when calculating t

d(off)

.

At high switching speeds, parasitic circuit elements com­plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func­tion of drain current, the mathematical solution is complex.
The M OSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea­sure and, consequently, is not specified.

The resistive switching time variation versus gate resis­tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op­erated into an inductive load; however, snubbing reduces
switching losses.

Figure 7. Capacitance Variation

GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

C, CAPACITANCE (pF)

V

GS

V

DS

TJ = 25

°C

VDS = 0 V VGS = 0 V

15000

12000

9000

6000

3000

0

20 2510 150 510 5

C

rss

C

iss

C

oss

C

rss

C

iss

MTB75N03HDL

5

Motorola TMOS Power MOSFET Transistor Device Data

V

DS

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

V

GS

, GATE–TO–SOURCE VOLTAGE (VOLTS)

RG, GATE RESISTANCE (OHMS)

1 10 100

t, TIME (ns)

TJ = 25°C
ID = 75 A
VDD = 15 V
VGS = 5 V

t

r

t

f

t

d(off)

t

d(on)

0

QT, TOTAL GATE CHARGE (nC)

10 20 30 40 70

TJ = 25°C
ID = 75 A

10000

1000

100

10

6

4

2

0

7

5

3

1

28

24

20

16

12

8

4

50 60

0

QT

Q1

Q3

V

GS

V

DS

Q2

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse re­covery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.

System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier de­vice, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.

The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ring­ing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diode’s negative di/dt during ta is directly con­trolled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode charac­teristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.

Compared to Motorola standard cell density low voltage
MOSFETs, high c ell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse re­covery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise gen­erated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

Figure 10. Diode Forward Voltage versus Current

VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

I

S

, SOURCE CURRENT (AMPS)

TJ = 25°C
VGS = 0 V

0.6 0.7 0.8 0.9 10.5

0

15

30

45

60

75

Figure 8. Gate–To–Source and Drain–To–Source

Voltage versus Total Charge

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

MTB75N03HDL

6

Motorola TMOS Power MOSFET Transistor Device Data

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum s imultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for­ward biased. Curves are based upon maximum peak junc­tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance – Gen­eral Data and Its Use.”

Switching between the off–state and the on–state may tra­verse any load line provided neither rated peak current (IDM)
nor rated voltage (V

DSS

) is exceeded, and that the transition
time (tr, tf) does not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
(T

J(MAX)

– TC)/(R

θJC

).

A power MOSFET designated E–FET can be safely used

in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dis­sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem­perature.

Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur­rent (ID), in accordance with industry custom. The energy rat­ing m ust be d erated f or t emperature a s shown i n the
accompanying graph (Figure 13). Maximum energy at cur­rents below rated continuous ID can safely be assumed to
equal the values indicated.

0.1 100

R

DS(on)

LIMIT
THERMAL LIMIT
PACKAGE LIMIT

10

VGS = 20 V
SINGLE PULSE
TC = 25°C

1

10

100

1000

1

dc

100 µs

1 ms

10 ms

TJ, STARTING JUNCTION TEMPERATURE (°C)

E

AS

, SINGLE PULSE DRAIN–TO–SOURCE

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

AVALANCHE ENERGY (mJ)

I

D

, DRAIN CURRENT (AMPS)

25 50 75 100 125

ID = 75 A

150

80

280

200

160

120

240

40

0

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

MTB75N03HDL

7

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

r(t), EFFECTIVE TRANSIENT THERMAL RESIST

ANCE

(NORMALIZED)

Figure 13. Thermal Response

Figure 14. Diode Reverse Recovery Waveform

di/dt

t

rr

t

a

t

p

I

S

0.25 I

S

TIME

I

S

t

b

0

0.5

1

1.5

2.0

2.5

3

25 50 75 100 125 150

TA, AMBIENT TEMPERATURE (

°

C)

P

D

, POWER DISSIPATION (WATTS)

Figure 15. D2PAK Power Derating Curve

R

θJA

= 50°C/W
Board material = 0.065 mil FR–4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size ≈ 450 mils x 350 mils

R

θ

JC

(t) = r(t) R

θ

JC

D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t

1

T

J(pk)

– TC = P

(pk)

R

θ

JC

(t)

P

(pk)

t

1

t

2

DUTY CYCLE, D = t1/t

2

t, TIME (s)

1.0

0.1

0.01

0.2

D = 0.5

0.05

0.01

SINGLE PULSE

0.1

1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01

0.02

MTB75N03HDL

8

Motorola TMOS Power MOSFET Transistor Device Data

INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE

RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface

between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.

mm

inches

0.74

18.79

0.065

1.651

0.07

1.78

0.14

3.56

0.330

8.38

0.420

10.66

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE

The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by T

J(max)

, the maximum rated

junction temperature of the die, R

θJA

, the thermal resistance
from the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data sheet,
PD can be calculated as follows:

PD =

T

J(max)

– T

A

R

θJA

The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device. For a D2PAK
device, PD is calculated as follows.

= 2.5 Watts

The 50°C/W for the D2PAK package assumes the use of the
recommended footprint on a glass epoxy printed circuit board
to achieve a power dissipation of 2.5 Watts. There are other
alternatives to achieving higher power dissipation from the
surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the power

dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
of using surface mount technology. For example, a graph of
R

θJA

versus drain pad area is shown in Figure 17.

A, AREA (SQUARE INCHES)

60

70

50

40

30

20

1614121086420

TO AMBIENT ( C/W)

°

R

JA

, THERMAL RESISTANCE, JUNCTION

θ

5 Watts

3.5 Watts

2.5 Watts

Board Material = 0.0625

″

G–10/FR–4, 2 oz Copper

TA = 25°C

Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.

150°C – 25°C

PD =

50°C/W

Figure 16. Thermal Resistance versus Drain Pad

Area for the D2PAK Package (Typical)

MTB75N03HDL

9

Motorola TMOS Power MOSFET Transistor Device Data

SOLDER STENCIL GUIDELINES

Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. Solder
stencils are used to screen the optimum amount. These
stencils are typically 0.008 inches thick and may be made of
brass or stainless steel. For packages such as the SC–59,
SC–70/SOT–323, SOD–123, SOT–23, SOT–143, SOT–223,
SO–8, SO–14, SO–16, and SMB/SMC diode packages, the
stencil opening should be the same as the pad size or a 1:1
registration. This is not the case with the DPAK and D2PAK
packages. If one uses a 1:1 opening to screen solder onto the
drain pad, misalignment and/or “tombstoning” may occur due
to an excess of solder. For these two packages, the opening
in the stencil for the paste should be approximately 50% of the
tab area. The opening for the leads is still a 1:1 registration.
Figure 18 shows a typical stencil for the DPAK and D2PAK
packages. The pattern of the opening in the stencil for the
drain pad is not critical as long as it allows approximately 50%
of the pad to be covered with paste.

Figure 17. Typical Stencil for DPAK and

D2PAK Packages

SOLDER PASTE
OPENINGS

STENCIL

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.

• Always preheat the device.

• The delta temperature between the preheat and soldering

should be 100°C or less.*

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.

• The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

• When shifting from preheating to soldering, the maximum

temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should be

allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied during

cooling.

* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.

* Due to shadowing and the inability to set the wave height to
incorporate other surface mount components, the D2PAK is
not recommended for wave soldering.

MTB75N03HDL

10

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of control
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a figure
for belt speed. T aken together , these control settings make up
a heating “profile” for that particular circuit board. On
machines controlled by a computer, the computer remembers
these profiles from one operating session to the next. Figure
19 shows a typical heating profile for use when soldering a
surface mount device to a printed circuit board. This profile will
vary among soldering systems but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
type of solder used, and the type of board or substrate material
being used. This profile shows temperature versus time. The

line on the graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/in­frared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 177–189°C. When this type of
furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder joints.

STEP 1

PREHEAT

ZONE 1

“RAMP”

STEP 2

VENT

“SOAK”

STEP 3

HEATING

ZONES 2 & 5

“RAMP”

STEP 4

HEATING

ZONES 3 & 6

“SOAK”

STEP 5

HEATING

ZONES 4 & 7

“SPIKE”

STEP 6

VENT

STEP 7

COOLING

200

°

C

150

°

C

100

°

C

50

°

C

TIME (3 TO 7 MINUTES TOTAL)

T

MAX

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

MASS OF ASSEMBLY)

205

°

TO 219°C
PEAK AT
SOLDER JOINT

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

100°C

150°C

160

°

C

170°C

140

°

C

DESIRED CURVE FOR HIGH

MASS ASSEMBLIES

Figure 18. Typical Solder Heating Profile

MTB75N03HDL

11

Motorola TMOS Power MOSFET Transistor Device Data

PACKAGE DIMENSIONS

CASE 418B–02

ISSUE B

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

SEATING
PLANE

B

S

G

D

–T–

M

0.13 (0.005) T

2 31

4

3 PL

K

J

H

V

E

C

A

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.340 0.380 8.64 9.65
B 0.380 0.405 9.65 10.29
C 0.160 0.190 4.06 4.83
D 0.020 0.035 0.51 0.89

E 0.045 0.055 1.14 1.40
G 0.100 BSC 2.54 BSC
H 0.080 0.110 2.03 2.79
J 0.018 0.025 0.46 0.64
K 0.090 0.110 2.29 2.79
S 0.575 0.625 14.60 15.88
V 0.045 0.055 1.14 1.40

MTB75N03HDL

12

Motorola TMOS Power MOSFET Transistor Device Data

How to reach us:
USA /EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,

P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315

MFAX: [e-mail] – TOUCHTONE (602) 244–6609 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different
applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
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associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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MTB75N03HDL/D

*MTB75N03HDL/D*

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