Datasheet MTB6N60E1 Datasheet (Motorola)

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SEMICONDUCTOR TECHNICAL DATA

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by MTB6N60E1/D

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N–Channel Enhancement–Mode Silicon Gate

This advanced TMOS E–FET is designed to withstand high

energy in the avalanche and commutation modes. The new energy

TMOS POWER FET

6.0 AMPERES
600 VOL TS

R

DS(on)

= 1.2 OHM

efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits



where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

• Robust High Voltage Termination

D

• Avalanche Energy Specified

• Source–to–Drain Diode Recovery Time Comparable to a

Discrete Fast Recovery Diode

• Diode is Characterized for Use in Bridge Circuits

• I

DSS

and V

Specified at Elevated Temperature

DS(on)

• Short Heatsink Tab Manufactured — Not Sheared

G

S

CASE 418C–01, Style 2

D2PAK–SL

• Specially Designed Leadframe for Maximum Power Dissipation

MAXIMUM RATINGS

Drain–to–Source Voltage V
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V

Gate–Source Voltage — Continuous

Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)

Drain Current — Continuous

Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)

Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C

Operating and Storage Temperature Range TJ, T
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 10 mH, RG = 25 Ω)
Thermal Resistance — Junction to Case

Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T

(1) When surface mounted to an FR4 board using the minimum recommended pad size.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

E–FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Preferred devices are Motorola recommended choices for future use and best overall value.

(TC = 25°C unless otherwise noted)

Rating

(1)

(1)

Symbol Value Unit

600 Vdc
600 Vdc

± 20
± 40

6.0

4.6
18

125

1.0

2.5

– 55 to 150 °C

405

1.0

62.5
50

260 °C

V

V

I

E

R
R
R

DSS

DGR

GS

GSM

I

D

I

D

DM
P

D

stg

AS

θJC
θJA
θJA

L

Vdc
Vpk

Adc

Apk

Watts

W/°C

Watts

mJ

°C/W

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

 Motorola, Inc. 1997

1

MTB6N60E1

)

f = 1.0 MHz)

V

G

)

(

DS

,

D

,

(

S

,

GS

,

ELECTRICAL CHARACTERISTICS

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage

(VGS = 0 Vdc, ID = 250 µAdc)
T emperature Coef ficient (Positive)

Zero Gate Voltage Drain Current

(VDS = 600 Vdc, VGS = 0 Vdc)
(VDS = 600 Vdc, VGS = 0 Vdc, TJ = 125°C)

Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) I

ON CHARACTERISTICS (1)

Gate Threshold Voltage

(VDS = VGS, ID = 250 µAdc)
T emperature Coef ficient (Negative)

Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 3.0 Adc) R
Drain–to–Source On–Voltage

(VGS = 10 Vdc, ID = 6.0 Adc)
(VGS = 10 Vdc, ID = 3.0 Adc, TJ = 125°C)

Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance
Reverse Transfer Capacitance

SWITCHING CHARACTERISTICS (2)

Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage (1)

Reverse Recovery Time

Reverse Recovery Stored Charge Q

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from the drain lead 0.25″ from package to center of die)

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.

(T

= 25°C unless otherwise noted)

J

Characteristic

(VDS = 25 Vdc, VGS = 0 Vdc,

(VDS = 300 Vdc, ID = 6.0 Adc,

(VDS = 300 Vdc, ID = 6.0 Adc,

(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125°C)

f = 1.0 MHz

= 10 Vdc,

GS

RG = 9.1 Ω)

VGS = 10 Vdc)

(IS = 6.0 Adc, VGS = 0 Vdc)

(IS = 6.0 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/µs)

Symbol Min Typ Max Unit

V

(BR)DSS

I

DSS

GSS

V

GS(th)

DS(on)

V

DS(on)

FS

C

iss

C

oss

C

rss

t

d(on)

t

r

t

d(off)

t

f

Q

T

Q

1

Q

2

Q

3

V

SD

t

rr

t

a

t

b

RR

L

D

L

S

600

—

—
—

— — 100 nAdc

2.0
—

— 0.94 1.2 Ohms

—
—

2.0 5.5 — mhos

— 1498 2100 pF
— 158 217
— 29 56

— 14 30 ns
— 19 40
— 40 80
— 26 50
— 35.5 50 nC
— 8.1 —
— 14.1 —
— 15.8 —

—
—

— 266 —
— 166 —
— 100 —
— 2.5 — µC

— 4.5 —

— 7.5

—

689

—
—

3.0

7.1

6.0
—

0.83

0.72

—
—

1.0
50

4.0
—

8.6

7.6

1.5
—

— nH

mV/°C

mV/°C

Vdc

µAdc

Vdc

Vdc

Vdc

ns

nH

2

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

MTB6N60E1

12

TJ = 25°C

10

8

6

4

, DRAIN CURRENT (AMPS)

D

I

2

0

2 6 10 14 6.0

04 81216

VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

VGS = 10 V

7 V

8 V

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

2.5
VGS = 10 V

2.0

1.5

1.0

0.5

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

TJ = 100°C

25°C

–55°C

6 V

5 V

4 V

18

12

VDS ≥ 10 V

10

8

6

4

, DRAIN CURRENT (AMPS)

D

I

2

0

2.5 3.5 4.5 5.5

2.0 3.0 4.0 5.0
VGS, GATE–T O–SOURCE VOLTAGE (VOLTS)

1.4
TJ = 25°C

1.3

1.2

1.1

1.0

0.9

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

VGS = 10 V

15 V

100°C

25°C

TJ = –55°C

DS(on)

0

R

02 6 10

48

ID, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus Drain Current

and T emperature

2.5
VGS = 10 V
ID = 3 A

2

1.5

1

(NORMALIZED)

, DRAIN–TO–SOURCE RESIST ANCE

0.5

DS(on)

R

0

–50 0 50 100 150125–25 25 75

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On–Resistance Variation with

Temperature

12

0.8

DS(on)

R

0

26481210

ID, DRAIN CURRENT (AMPS)

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

10000

VGS = 0 V

1000

100

, LEAKAGE (nA)

DSS

I

10

1

0 200 400

100 300 600500

VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

TJ = 125°C

100°C

25°C

Figure 6. Drain–T o–Source Leakage

Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

3

MTB6N60E1

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter­mined by how fast the FET input capacitance can be charged
by current from the generator.

The published capacitance data is difficult to use for calculat­ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
the drive circuit so that

t = Q/I

G(AV)

During the rise and fall time interval when switching a resis­tive load, VGS remains virtually constant at a level known as
the plateau voltage, V
be approximated by the following:

tr = Q2 x RG/(VGG – V
tf = Q2 x RG/V
where
VGG = the gate drive voltage, which varies from zero to V
RG = the gate drive resistance
and Q2 and V
During the turn–on and turn–off delay times, gate current is

not constant. The simplest calculation uses appropriate val­ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

= RG C

d(on)

t

= RG C

d(off)

) can be made from a rudimentary analysis of

G(A V)

. Therefore, rise and fall times may

SGP

)

GSP

GSP

are read from the gate charge curve.

GSP

In [VGG/(VGG – V

iss

In (VGG/V

iss

GSP

)

GSP

)]

GG

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off–state condition when cal­culating t
on–state when calculating t

and is read at a voltage corresponding to the

d(on)

d(off)

.

At high switching speeds, parasitic circuit elements com­plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func­tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea­sure and, consequently , is not specified.

The resistive switching time variation versus gate resis­tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op­erated into an inductive load; however, snubbing reduces
switching losses.

3200

2400

1600

C, CAPACITANCE (pF)

800

VDS = 0 V VGS = 0 V

C

iss

C

C

iss

oss

C

rss

C

GS

V

rss

DS

0

10 0 10 15 25

55

V

GATE–T O–SOURCE OR DRAIN–TO–SOURCE VOL TAGE (VOLTS)

Figure 7a. Capacitance Variation

TJ = 25

20

°C

10000

TJ=25°C
VGS=0 V

1000

100

C, CAPACITANCE (pF)

10

1

10 100 1000

VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

C

iss

C

oss

C

rss

Figure 7b. High V oltage Capacitance Variation

4

Motorola TMOS Power MOSFET Transistor Device Data

12

10

MTB6N60E1

300

Q

T

8

V

GS

DS

200

V

, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

100

VDD = 300 V
ID = 6 A
VGS = 10 V
TJ = 25

°

C

, GATE–T O–SOURCE VOLTAGE (VOLTS)

GS

V

Q

6

4

2

0

1

Q

3

0

612 2430

Q

2

18

QT, TOTAL CHARGE (nC)

V

DS

Figure 8. Gate–T o–Source and Drain–To–Source

V oltage versus Total Charge

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

6

VGS = 0 V
TJ = 25

°

5

4

3

2

, SOURCE CURRENT (AMPS)

S

I

1

C

ID = 6 A
TJ = 25

t

10

t, TIME (ns)

100

°

C

36

0

1

1 10 100

d(off)

t

f

t

r

t

d(on)

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

0

0.50 0.70 0.80
VSD, SOURCE–TO–DRAIN VOL TAGE (VOL TS)

0.65 0.75 0.850.55 0.60

Figure 10. Diode Forward V oltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for­ward biased. Curves are based upon maximum peak junc­tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–Gener­al Data and Its Use.”

Switching between the off–state and the on–state may tra­verse any load line provided neither rated peak current (IDM)
nor rated voltage (V
(tr,tf) do not exceed 10 µs. In addition the total power aver­aged over a complete switching cycle must not exceed
(T

J(MAX)

– TC)/(R

A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-

) is exceeded and the transition time

DSS

).

θJC

able operation, the stored energy from circuit inductance dis­sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con­stant. The energy rating decreases non–linearly with an in­crease of peak current in avalanche and peak junction
temperature.

Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur­rent (ID), in accordance with industry custom. The energy rat­ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur­rents below rated continuous ID can safely be assumed to
equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

5

MTB6N60E1

SAFE OPERATING AREA

100

VGS = 20 V
SINGLE PULSE
TC = 25

°

C

10

100 µs

1 ms

1.0

, DRAIN CURRENT (AMPS)

D

I

0.1

0.1 1 10 100 1000
VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

10 ms

R

LIMIT

DS(on)

THERMAL LIMIT
PACKAGE LIMIT

10 µs

dc

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

1

D = 0.5

0.2

0.1

0.1

0.05

0.02

r(t), NORMALIZED EFFECTIVE

TRANSIENT THERMAL RESISTANCE

SINGLE PULSE

0.01

0.00001 0.0001 0.001 0.01 0.1 1 10

0.01

450
400
350

300
250
200
150

AVALANCHE ENERGY (mJ)

100

, SINGLE PULSE DRAINN–TO–SOURCE

50

AS

E

0

25 50 75 100 125

TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Avalanche Energy versus

P

(pk)

t

1

t

2

DUTY CYCLE, D = t1/t

t, TIME (SECONDS)

Figure 13. Thermal Response

Starting Junction T emperature

R

(t) = r(t) R

θ

JC

D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
T

J(pk)

2

– TC = P

θ

(pk)

JC

1

R

θ

ID = 6 A

(t)

JC

150

di/dt

I

S

t

rr

t

t

a

b

t

p

0.25 I

S

I

S

Figure 14. Diode Reverse Recovery Waveform

6

TIME

3

2.5

2.0

1.5

1

, POWER DISSIPATION (WATTS)

0.5

D

P

0

25 50 75 100 125 150

R

= 50°C/W

θJA

Board material = 0.065 mil FR–4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size ≈ 450 mils x 350 mils

°

TA, AMBIENT TEMPERATURE (

C)

Figure 15. D2PAK Power Derating Curve

Motorola TMOS Power MOSFET Transistor Device Data

–T–

SEATING
PLANE

MTB6N60E1

P ACKAGE DIMENSIONS

C

E

–B–

4

W

123

F

K

S

G

D 3 PL

0.13 (0.005) T

M

M

B

V

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

A

DIM MIN MAX MIN MAX

A 0.340 0.380 8.64 9.65
B 0.380 0.405 9.65 10.29
C 0.160 0.190 4.06 4.83
D 0.020 0.035 0.51 0.89
E 0.045 0.055 1.14 1.40
F 0.039 REF 1.00 REF
G 0.100 BSC 2.54 BSC
H 0.080 0.110 2.03 2.79
J 0.018 0.025 0.46 0.64

J

H

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

K 0.280 0.360 7.11 9.14
S 0.276 REF 7.00 REF
V 0.045 0.055 1.14 1.40

W 0.423 0.462 10.75 11.75

MILLIMETERSINCHES

CASE 418C–01

ISSUE O

Motorola TMOS Power MOSFET Transistor Device Data

7

MTB6N60E1

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
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Motorola TMOS Power MOSFET Transistor Device Data

Mfax is a trademark of Motorola, Inc.

MTB6N60E1/D