Datasheet MTB4N80E1 Datasheet (Motorola)

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SEMICONDUCTOR TECHNICAL DATA

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N–Channel Enhancement–Mode Silicon Gate

This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

• Robust High Voltage Termination

• Avalanche Energy Specified

• Source–to–Drain Diode Recovery Time Comparable to a

Discrete Fast Recovery Diode

• Diode is Characterized for Use in Bridge Circuits

• I

DSS

and V

Specified at Elevated Temperature

DS(on)

• Short Heatsink Tab Manufactured — Not Sheared

• Specially Designed Leadframe for Maximum Power Dissipation

G

TMOS POWER FET

4.0 AMPERES
800 VOL TS

R

DS(on)

= 3.0 OHM



D

CASE 418C–01, Style 2

S

D2PAK–SL

MAXIMUM RATINGS

Drain–Source Voltage V
Drain–Gate Voltage (RGS = 1.0 MΩ) V
Gate–Source Voltage — Continuous

Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)

Drain Current — Continuous

Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)

Total Power Dissipation

Derate above 25°C

Total Power Dissipation @ TA = 25°C, when mounted with the minimum recommended pad size
Operating and Storage Temperature Range TJ, T
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 100 Vdc, VGS = 10 Vdc, IL = 8.0 Apk, L = 10 mH, RG = 25 Ω)

Thermal Resistance — Junction to Case

Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

E–FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Preferred devices are Motorola recommended choices for future use and best overall value.

(TC = 25°C unless otherwise noted)

Rating

Symbol Value Unit

800 Vdc
800 Vdc

± 20
± 40

4.0

2.9
12

125

1.0

2.5

– 55 to 150 °C

320 mJ

1.0

62.5
50

260 °C

V

V

I

E

R
R
R

DSS

DGR

GS

GSM

I

D

I

D

DM
P

D

stg

AS

θJC
θJA
θJA

L

Vdc
Vpk

Adc

Apk

Watts

W/°C

Watts

°C/W

Motorola TMOS Power MOSFET Transistor Device Data

 Motorola, Inc. 1997

1

MTB4N80E1

)

f = 1.0 MHz)

V

G

)

(

DS

,

D

,

(

S

,

GS

,

ELECTRICAL CHARACTERISTICS

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain–Source Breakdown Voltage

(VGS = 0 Vdc, ID = 250 µAdc)
T emperature Coef ficient (Positive)

Zero Gate Voltage Drain Current

(VDS = 800 Vdc, VGS = 0 Vdc)
(VDS = 800 Vdc, VGS = 0 Vdc, TJ = 125°C)

Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) I

ON CHARACTERISTICS (1)

Gate Threshold Voltage

(VDS = VGS, ID = 250 µAdc)

T emperature Coef ficient (Negative)
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 2.0 Adc) R
Drain–Source On–Voltage (VGS = 10 Vdc)

(ID = 4.0 Adc)

(ID = 2.0 Adc, TJ = 125°C)
Forward Transconductance (VDS = 15 Vdc, ID = 2.0 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance
Reverse Transfer Capacitance

SWITCHING CHARACTERISTICS (2)

Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge

(See Figure 8)

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage (1)

Reverse Recovery Time

(See Figure 14)

Reverse Recovery Stored Charge Q

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.

(TJ = 25°C unless otherwise noted)

(VDS = 25 Vdc, VGS = 0 Vdc,

(VDD = 400 Vdc, ID = 4.0 Adc,

(VDS = 400 Vdc, ID = 4.0 Adc,

(IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125°C)

f = 1.0 MHz

= 10 Vdc,

GS
RG = 9.1 Ω)

VGS = 10 Vdc)

(IS = 4.0 Adc, VGS = 0 Vdc)

(IS = 4.0 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/µs)

V

(BR)DSS

I

DSS

GSS

V

GS(th)

DS(on)

V

DS(on)

FS

C

iss

C

oss

C

rss

t

d(on)

t

r

t

d(off)

t

f

Q
Q
Q
Q

V

SD

t

rr

t

a

t

b

RR

L

D

L

S

800

—

—
—

— — 100 nAdc

2.0
—

— 1.95 3.0 Ohm

—
—

2.0 4.3 — mhos

— 1320 2030 pF
— 187 400
— 72 160

— 13 30 ns
— 36 90
— 40 80
— 30 75

T
1
2
3

— 36 80 nC
— 7.0 —
— 16.5 —
— 12 —

—
—

— 557 —
— 100 —
— 457 —
— 2.33 — µC

— 4.5 — nH

— 7.5 — nH

—

1.02

—
—

3.0

7.0

8.24
—

0.812

0.7

—
—

10

100

4.0
—

12
10

1.5
—

Vdc

mV/°C

µAdc

Vdc

mV/°C

Vdc

Vdc

ns

2

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

MTB4N80E1

8

TJ = 25°C

7
6
5
4
3

, DRAIN CURRENT (AMPS)

2

D

I

1
0

048121620

2 6 10 14 18

VDS, DRAIN–TO–SOURCE VOL TAGE (VOL TS)

VGS = 10 V

6 V

5 V

4 V

Figure 1. On–Region Characteristics

4.6
VGS = 10 V

3.8

3.0

2.2

TJ = 100°C

25°C

8

VDS ≥ 10 V

7
6
5
4
3

, DRAIN CURRENT (AMPS)

2

D

I

1
0

2.0 2.8 3.6 4.4 5.22.4 3.2 4.0 4.8
VGS, GATE–T O–SOURCE VOLTAGE (VOLTS)

25°C

Figure 2. Transfer Characteristics

2.6
TJ = 25°C

2.5

2.4

2.3

2.2

2.1

VGS = 10 V

100°C

TJ = –55°C

5.6

1.4

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

0.6

DS(on)

R

13 7

24 86

–55°C

5

ID, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus Drain Current

and T emperature

2.2
VGS = 10 V
ID = 2 A

1.8

1.4

1.0

(NORMALIZED)

, DRAIN–TO–SOURCE RESIST ANCE

0.6

DS(on)

R

0.2

–50

–25 0 25 50 75 100 125 150

TJ, JUNCTION TEMPERATURE (°C)

2.0

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

1.9

1.8

DS(on)

R

13 7524 86

15 V

ID, DRAIN CURRENT (AMPS)

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

10000

VGS = 0 V

1000

100

, LEAKAGE (nA)

DSS

I

10

1

100 300 600500

0 200 400

VDS, DRAIN–TO–SOURCE VOL TAGE (VOL TS)

TJ = 125°C

100°C

25°C

800700

Figure 5. On–Resistance Variation with

Temperature

Motorola TMOS Power MOSFET Transistor Device Data

Figure 6. Drain–T o–Source Leakage

Current versus Voltage

3

MTB4N80E1

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter­mined by how fast the FET input capacitance can be charged
by current from the generator.

The published capacitance data is difficult to use for calculat­ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I

) can be made from a rudimentary analysis of

G(A V)

the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a resis­tive load, VGS remains virtually constant at a level known as
the plateau voltage, V

. Therefore, rise and fall times may

SGP

be approximated by the following:
tr = Q2 x RG/(VGG – V
tf = Q2 x RG/V

GSP

GSP

)

where
VGG = the gate drive voltage, which varies from zero to V

GG

RG = the gate drive resistance
and Q2 and V

are read from the gate charge curve.

GSP

During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val­ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

t

d(off)

= RG C

= RG C

In [VGG/(VGG – V

iss

In (VGG/V

iss

GSP

)]

GSP

)

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off–state condition when cal­culating t
on–state when calculating t

and is read at a voltage corresponding to the

d(on)

d(off)

.

At high switching speeds, parasitic circuit elements com­plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func­tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea­sure and, consequently , is not specified.

The resistive switching time variation versus gate resis­tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op­erated into an inductive load; however, snubbing reduces
switching losses.

2800

2400
2000

1600

1200

800

C, CAPACITANCE (pF)

400

0

10 0 10152025

GATE–T O–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

VDS = 0 V

C

iss

C

rss

C

55

V

GS

rss

V

VGS = 0 V

DS

TJ = 25°C

C

iss

C

oss

Figure 7a. Capacitance Variation

10000

V

= 0 V

GS

C

1000

100

10

C, CAPACITANCE (pF)

1

10 100 1000

VDS, DRAIN–TO–SOURCE VOL TAGE (VOL TS)

iss

C

oss

C

rss

Figure 7b. High Voltage Capacitance

Variation

TJ = 25°C

4

Motorola TMOS Power MOSFET Transistor Device Data

10

QT

8

Q1 Q2

6

4

2

, GATE–T O–SOURCE VOLTAGE (VOLTS)

GS

V

0

01218

Q3

62430

QG, TOTAL GATE CHARGE (nC)

V

GS

V

DS

500

V

DS

, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

400

300

I

= 4 A

D

TJ = 25

200

°

C

100

0

36

MTB4N80E1

1000

VDD = 400 V
ID = 4 A
VGS = 10 V
TJ = 25

°

C

100

t, TIME (ns)

t

d(off)

t

10

1 10 100

d(on)

RG, GATE RESISTANCE (OHMS)

t

f

t

r

Figure 8. Gate–T o–Source and Drain–To–Source

V oltage versus Total Charge

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

4.0

3.6

VGS = 0 V
TJ = 25

°

3.2

2.8

2.4

2.0

1.6

1.2

, SOURCE CURRENT (AMPS)

0.8

S

I

0.4
0

0.50 0.70 0.78

Figure 10. Diode Forward V oltage versus Current

C

VSD, SOURCE–TO–DRAIN VOL TAGE (VOL TS)

0.66 0.74

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

0.820.580.54 0.62

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for­ward biased. Curves are based upon maximum peak junc­tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–Gener­al Data and Its Use.”

Switching between the off–state and the on–state may tra­verse any load line provided neither rated peak current (IDM)
nor rated voltage (V
(tr,tf) do not exceed 10 µs. In addition the total power aver­aged over a complete switching cycle must not exceed
(T

J(MAX)

– TC)/(R

A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

) is exceeded and the transition time

DSS

).

θJC

able operation, the stored energy from circuit inductance dis­sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con­stant. The energy rating decreases non–linearly with an in­crease of peak current in avalanche and peak junction
temperature.

Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur­rent (ID), in accordance with industry custom. The energy rat­ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur­rents below rated continuous ID can safely be assumed to
equal the values indicated.

5

MTB4N80E1

SAFE OPERATING AREA

100

VGS = 20 V
SINGLE PULSE
TC = 25

°

10

1.0

, DRAIN CURRENT (AMPS)

0.1

D

I

0.01

0.1 1.0 1000

C

100

µ

s

1ms

10 ms

R

LIMIT

DS(on)

THERMAL LIMIT
PACKAGE LIMIT

10

VDS, DRAIN–TO–SOURCE VOL TAGE (VOL TS)

dc

100

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

1.0
D = 0.5

0.2

0.1

0.1

0.05

r(t), NORMALIZED EFFECTIVE

TRANSIENT THERMAL RESISTANCE

0.01

1.0E–05 1.0E–04 1.0E–02

0.02

0.01

SINGLE PULSE

1.0E–03

10µs

350

300

250

200

150

100

AVALANCHE ENERGY (mJ)

50

, SINGLE PULSE DRAIN–TO–SOURCE

AS

E

0

P

(pk)

t, TIME (s)

ID = 4 A

25 150

50 100 12575

TJ, STARTING JUNCTION TEMPERATURE (

°

C)

Figure 12. Maximum Avalanche Energy versus

Starting Junction T emperature

R

(t) = r(t) R

θ

t

1

t

2

DUTY CYCLE, D = t1/t

1.0E–01 1.0E+00

JC

D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
T

J(pk)

2

– TC = P

θ

(pk)

1

JC

R

(t)

θ

JC

1.0E+01

di/dt

I

S

t

rr

t

t

a

b

t

p

0.25 I

S

I

S

Figure 14. Diode Reverse Recovery Waveform

6

Figure 13. Thermal Response

3

2.5

2.0

1.5

1

TIME

, POWER DISSIPATION (WATTS)

0.5

D

P

0

25 50 75 100 125 150

Figure 15. D2PAK Power Derating Curve

Motorola TMOS Power MOSFET Transistor Device Data

R

= 50°C/W

θJA

Board material = 0.065 mil FR–4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size ≈ 450 mils x 350 mils

°

TA, AMBIENT TEMPERATURE (

C)

–T–

SEATING
PLANE

MTB4N80E1

P ACKAGE DIMENSIONS

C

E

–B–

4

W

123

F

K

S

G

D 3 PL

0.13 (0.005) T

M

M

B

V

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

A

DIM MIN MAX MIN MAX

A 0.340 0.380 8.64 9.65
B 0.380 0.405 9.65 10.29
C 0.160 0.190 4.06 4.83
D 0.020 0.035 0.51 0.89
E 0.045 0.055 1.14 1.40
F 0.039 REF 1.00 REF
G 0.100 BSC 2.54 BSC
H 0.080 0.110 2.03 2.79
J 0.018 0.025 0.46 0.64

J

H

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

K 0.280 0.360 7.11 9.14
S 0.276 REF 7.00 REF
V 0.045 0.055 1.14 1.40
W 0.423 0.462 10.75 11.75

MILLIMETERSINCHES

CASE 418C–01

ISSUE O

Motorola TMOS Power MOSFET Transistor Device Data

7

MTB4N80E1

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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Motorola TMOS Power MOSFET Transistor Device Data

Mfax is a trademark of Motorola, Inc.

MTB4N80E1/D