Datasheet MTB40N10E Datasheet (Motorola)

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Page 1

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SEMICONDUCTOR TECHNICAL DATA

  

 



   

N–Channel Enhancement–Mode Silicon Gate

This advanced TMOS E–FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.

• Avalanche Energy Specified

• Source–to–Drain Diode Recovery Time Comparable to a

Discrete Fast Recovery Diode

• Diode is Characterized for Use in Bridge Circuits

• I

DSS

and V

Specified at Elevated Temperature

DS(on)

N–Channel

Order this document

by MTB40N10E/D



TMOS POWER FET

40 AMPERES

100 VOL TS



DS(on)

= 0.04 OHM

MAXIMUM RATINGS

Drain–to–Source Voltage V Drain–to–Gate Voltage (RGS = 1.0 MΩ) V Gate–to–Source Voltage — Continuous

Gate–to–Source Voltage — Non–Repetitive (tp ≤ 10 ms)

Drain Current — Continuous

Drain Current — Continuous @ 100°C Drain Current — Single Pulse (tp ≤ 10 µs)

Total Power Dissipation

Derate above 25°C

Total Power Dissipation @ TA = 25°C Operating and Storage Temperature Range TJ, T Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 75 Vdc, VGS = 10 Vdc, PEAK IL = 40 Apk, L = 1.0 mH, RG = 25 Ω)

Thermal Resistance — Junction to Case

Thermal Resistance — Junction to Ambient Thermal Resistance — Junction to Ambient

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T

(1) When surface mounted to an FR4 board using the minimum recommended pad size.

(TC = 25°C unless otherwise noted)

Rating

(1)

CASE 418B–03, Style 2

Symbol Value Unit

DSS

DGR

GSM

DM P

stg

θJC

θJA

D2PAK

100 Vdc 100 Vdc

± 20 ± 40

40 29

140 169

1.35

2.5

– 55 to 150 °C

800

0.74

62.5 50

260 °C

Vdc Vpk

Adc

Apk

Watts

W/°C

Watts

°C/W

This document contains information on a new product. Specifications and information herein are subject to change without notice.

E–FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

 Motorola, Inc. 1997

Page 2

MTB40N10E

)

f = 1.0 MHz)

)

(

ELECTRICAL CHARACTERISTICS

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage

(VGS = 0 Vdc, ID = 0.25 mAdc) T emperature Coef ficient (Positive) (Cpk ≥ 2.0)

Zero Gate Voltage Drain Current

(VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125°C)

Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) I

ON CHARACTERISTICS

Gate Threshold Voltage (Cpk ≥ 2.0)

(VDS = VGS, ID = 250 µAdc) Threshold Temperature Coefficient (Negative)

Static Drain–to–Source On–Resistance

(VGS = 10 Vdc, ID = 20 Adc) (Cpk ≥ 2.0)

Drain–to–Source On–Voltage (VGS = 10 Vdc)

(ID = 40 Adc) (ID = 20 Adc, TJ = 125°C)

Forward Transconductance (VDS = 8.4 Vdc, ID = 20 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance Output Capacitance

Transfer Capacitance

SWITCHING CHARACTERISTICS

Turn–On Delay Time Rise Time Turn–Off Delay Time Fall Time Gate Charge

(See Figure 8)

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage

Reverse Recovery Time

(See Figure 14)

Reverse Recovery Stored Charge Q

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from the contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die)

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. (2) Switching characteristics are independent of operating junction temperature.

(3) Reflects typical values.

(1)

Cpk

= 25°C unless otherwise noted)

Characteristic

(VDS = 25 Vdc, VGS = 0 Vdc,

(2)

(IS = 40 Adc, VGS = 0 Vdc, TJ = 125°C)

Max limit – Typ

3 sigma

f = 1.0 MHz

(VDD = 50 Vdc, ID = 40 Adc,

(VDS = 80 Vdc, ID = 40 Adc,

(IS = 40 Adc, VGS = 0 Vdc)

(IS = 40 Adc, VGS = 0 Vdc,

= 10 Vdc,

RG = 9.1 Ω)

VGS = 10 Vdc)

dIS/dt = 100 A/µs)

(3)

Symbol Min Typ Max Unit

(BR)DSS

DSS

GSS

GS(th)

DS(on)

iss

oss

rss

d(on)

d(off)

100

—

— —

— — 100 nAdc

2.0 —

— 0.033 0.04

— —

17 21 — mhos

— 2305 3230 pF — 620 1240 — 205 290

— 19 40 ns — 165 330 — 75 150 — 97 190 — 80 110 nC — 15 — — 40 — — 29 —

— —

— 152 — — 117 — — 35 — — 1.0 — µC

— —

— 7.5 —

—

112

— —

2.9

6.7

— —

0.96

0.88

3.5

4.5

— —

100

4.0 —

1.9

1.7

1.0 —

— —

mV/°C

Ohms

Vdc

µAdc

Vdc

Motorola TMOS Power MOSFET Transistor Device Data

Page 3

TYPICAL ELECTRICAL CHARACTERISTICS

MTB40N10E

VGS = 10 V TJ = 25°C

70 60 50 40 30

, DRAIN CURRENT (AMPS)

012345678910

VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

8 V

9 V

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

0.07 VGS = 10 V

0.06

0.05

0.04

0.03

0.02

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

0.01

DS(on)

01020304050607080

TJ = 100°C

25°C

–55°C

ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus Drain Current

and T emperature

7 V

6 V

5 V

VDS ≥ 10 V

70 60 50 40 30

, DRAIN CURRENT (AMPS)

2345 6 78

VGS, GATE–T O–SOURCE VOLTAGE (VOLTS)

0.050

0.045

0.040

0.035

0.030

0.025

0.020

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

0.015

0.010

DS(on)

TJ = 25°C

VGS = 10 V

15 V

01020304050607080

100°C

25°C

TJ = –55°C

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

2.0

1.8

VGS = 10 V ID = 20 A

1.6

1.4

1.2

1.0

0.8

(NORMALIZED)

0.6

, DRAIN–TO–SOURCE RESIST ANCE

0.4

0.2

DS(on)

–50 –25 0 25 50 75 100 125 150

TJ, JUNCTION TEMPERATURE (

C) VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

Figure 5. On–Resistance Variation with

Temperature

Motorola TMOS Power MOSFET Transistor Device Data

1000

, LEAKAGE (nA)

DSS

VGS = 0 V

100

1.0 010203040 607080 100

TJ = 125°C

100°C

50 90

Figure 6. Drain–T o–Source Leakage

Current versus Voltage

Page 4

MTB40N10E

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged by current from the generator.

The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies greatly with applied voltage. Accordingly , gate charge data is used. In most cases, a satisfactory estimate of average input current (I

) can be made from a rudimentary analysis of

G(A V)

the drive circuit so that t = Q/I

G(AV)

During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, V

. Therefore, rise and fall times may

SGP

be approximated by the following: tr = Q2 x RG/(VGG – V tf = Q2 x RG/V

GSP

)

where VGG = the gate drive voltage, which varies from zero to V

RG = the gate drive resistance and Q2 and V

are read from the gate charge curve.

GSP

During the turn–on and turn–off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are:

d(on)

d(off)

= RG C

In [VGG/(VGG – V

iss

In (VGG/V

iss

GSP

)]

GSP

)

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off–state condition when calculating t on–state when calculating t

and is read at a voltage corresponding to the

d(on)

d(off)

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

C, CAPACITANCE (pF)

8000 7000 6000 5000 4000 3000 2000 1000

VDS = 0 V

iss

rss

–10 –5 0 5 10 25

GATE–T O–SOURCE OR DRAIN–TO–SOURCE VOL TAGE (VOLTS)

VGS = 0 V

rss

15 20

Figure 7. Capacitance Variation

TJ = 25

°C

iss

oss

Motorola TMOS Power MOSFET Transistor Device Data

Page 5

, GATE–T O–SOURCE VOLTAGE (VOLTS)

9 8 7 6 5 4 3 2 1

10 20 30 40 50

QG, TOTAL GATE CHARGE (nC)

Q2Q1

MTB40N10E

, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

10,000

VDD = 50 V ID = 40 A VGS = 10 V TJ = 25

1000

t, TIME (ns)

100

1.0 10 100

d(off)

d(on)

RG, GATE RESISTANCE (OHMS)

ID = 40 A TJ = 25

60 70 80

80 72 64 56 48 40 32 24

16 8

Figure 8. Gate–T o–Source and Drain–To–Source

V oltage versus Total Charge

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

40 35

30 25 20 15 10

, SOURCE CURRENT (AMPS)

VGS = 0 V TJ = 25

0.60 0.65 0.70 0.75 0.80 1.0 VSD, SOURCE–TO–DRAIN VOL TAGE (VOLTS)

Figure 10. Diode Forward V oltage versus Current

SAFE OPERATING AREA

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

0.85 0.90 0.95

The Forward Biased Safe Operating Area curves define the maximum simultaneous drain–to–source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance–General Data and Its Use.”

Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (V

) is exceeded and the transition

DSS

time (tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed (T

J(MAX)

– TC)/(R

θJC

A Power MOSFET designated E–FET can be safely used in switching circuits with unclamped inductive loads. For

Motorola TMOS Power MOSFET Transistor Device Data

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction temperature.

Although many E–FETs can withstand the stress of drain–to–source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

Page 6

MTB40N10E

SAFE OPERATING AREA

1000

VGS = 20 V SINGLE PULSE TC = 25

100

, DRAIN CURRENT (AMPS)

1.0

0.1 1.0 1000 VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

1.0 ms

100 ms

10 ms

DS(on)

THERMAL LIMIT PACKAGE LIMIT

10 ms

100

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

1.0 D = 0.5

0.2

0.1

0.05

0.02

r(t), NORMALIZED EFFECTIVE

TRANSIENT THERMAL RESISTANCE

0.0 SINGLE PULSE

0.01

1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01

LIMIT

800 700 600 500 400 300 200

AVALANCHE ENERGY (mJ)

, SINGLE PULSE DRAIN–TO–SOURCE

100

25 50 75 100 12510

Figure 12. Maximum Avalanche Energy versus

(pk)

DUTY CYCLE, D = t1/t

TJ, STARTING JUNCTION TEMPERATURE (°C)

Starting Junction T emperature

(t) = r(t) R

D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t

J(pk)

– TC = P

(pk)

ID = 40 A

150

(t)

Figure 13. Thermal Response

di/dt

TIME

0.25 I

Figure 14. Diode Reverse Recovery Waveform

t, TIME (seconds)

2.5

2.0

1.5

0.5

, POWER DISSIPATION (WATTS)

= 50°C/W

θJA

Board material = 0.065 mil FR–4 Mounted on the minimum recommended footprint Collector/Drain Pad Size ≈ 450 mils x 350 mils

25 50 75 100 125 150

TA, AMBIENT TEMPERATURE (

Figure 15. D2PAK Power Derating Curve

Motorola TMOS Power MOSFET Transistor Device Data

Page 7

INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE

RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface

0.33

8.38

0.42

10.66

MTB40N10E

between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.08

2.032

1.016

0.12

3.05

0.63

17.02

0.24

6.096

0.04

inches

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE

The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by T junction temperature of the die, R from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:

PD =

J(max)

θJA

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows.

150°C – 25°C

PD =

50°C/W

The 50°C/W for the D2P AK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power

, the maximum rated

J(max)

, the thermal resistance

θJA

– T

= 2.5 Watts

dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of R

versus drain pad area is shown in Figure 16.

θJA

TO AMBIENT ( C/W)

, THERMAL RESISTANCE, JUNCTION

2.5 Watts

Board Material = 0.0625 G–10/FR–4, 2 oz Copper

3.5 Watts

5 Watts

A, AREA (SQUARE INCHES)

″

TA = 25°C

1614121086420

Figure 16. Thermal Resistance versus Drain Pad

Area for the D2P AK Package (Typical)

Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

Motorola TMOS Power MOSFET Transistor Device Data

Page 8

MTB40N10E

SOLDER STENCIL GUIDELINES

Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC–59, SC–70/SOT–323, SOD–123, SOT–23, SOT–143, SOT–223, SO–8, SO–14, SO–16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or “tombstoning” may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected.

• Always preheat the device.

• The delta temperature between the preheat and soldering

should be 100°C or less.*

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C.

• The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

SOLDER P ASTE OPENINGS

STENCIL

Figure 17. T ypical Stencil for DPAK and

D2P AK Packages

• When shifting from preheating to soldering, the maximum

temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should be

allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied during

cooling.

* Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

* Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

Motorola TMOS Power MOSFET Transistor Device Data

Page 9

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. T aken together , these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The

MTB40N10E

line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177–189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

200

150°C

100

STEP 1

PREHEA T

ZONE 1 “RAMP”

DESIRED CURVE FOR HIGH

TIME (3 TO 7 MINUTES TOTAL)

STEP 2

VENT

“SOAK”

MASS ASSEMBLIES

150°C

100°C

Figure 18. T ypical Solder Heating Profile

STEP 3

HEATING

ZONES 2 & 5

“RAMP”

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

STEP 4

HEATING

ZONES 3 & 6

“SOAK”

160

140°C

MAX

STEP 6

VENT

205

SOLDER JOINT

STEP 5

HEATING

ZONES 4 & 7

“SPIKE”

170°C

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

MASS OF ASSEMBLY)

COOLING

TO 219°C

PEAK AT

STEP 7

Motorola TMOS Power MOSFET Transistor Device Data

Page 10

MTB40N10E

–T–

SEATING PLANE

–B–

231

3 PL

0.13 (0.005) T

P ACKAGE DIMENSIONS

CASE 418B–03

ISSUE C

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

A 0.340 0.380 8.64 9.65 B 0.380 0.405 9.65 10.29 C 0.160 0.190 4.06 4.83 D 0.020 0.035 0.51 0.89 E 0.045 0.055 1.14 1.40 G 0.100 BSC 2.54 BSC H 0.080 0.110 2.03 2.79 J 0.018 0.025 0.46 0.64 K 0.090 0.110 2.29 2.79 S 0.575 0.625 14.60 15.88 V 0.045 0.055 1.14 1.40

MILLIMETERSINCHES

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

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Motorola TMOS Power MOSFET Transistor Device Data

Mfax is a trademark of Motorola, Inc.

MTB40N10E/D