Datasheet MTB2N60E Datasheet (Motorola)

1

Motorola TMOS Power MOSFET Transistor Device Data

  

 



 # " 
  ! !

N–Channel Enhancement–Mode Silicon Gate

This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

• Robust High Voltage Termination

• Avalanche Energy Specified

• Source–to–Drain Diode Recovery Time Comparable to a

Discrete Fast Recovery Diode

• Diode is Characterized for Use in Bridge Circuits

• I

DSS

and V

DS(on)

Specified at Elevated Temperature

MAXIMUM RATINGS

(TC = 25°C unless otherwise noted)

Rating

Symbol Value Unit

Drain–to–Source Voltage V

DSS

600 Vdc

Drain–to–Gate Voltage (RGS = 1.0 MΩ) V

DGR

600 Vdc

Gate–to–Source Voltage — Continuous

— Non–Repetitive (tp ≤ 10 ms)

V

GS

V

GSM

± 20
± 40

Vdc
Vpk

Drain Current — Continuous

— Continuous @ 100°C
— Single Pulse (tp ≤ 10 µs)

I

D

I

D

I

DM

2.0

1.3

7.0

Adc

Apk

Total Power Dissipation @ 25°C

Derate above 25°C

Total Power Dissipation @ TA = 25°C

(1)

P

D

50

0.4

2.5

Watts

W/°C

Watts

Operating and Storage Temperature Range TJ, T

stg

– 55 to 150 °C

Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 50 Vdc, VGS = 10 Vdc, Peak IL = 2.0 Apk, L = 95 mH, RG = 25 Ω)

E

AS

190 mJ

Thermal Resistance — Junction to Case

— Junction to Ambient
— Junction to Ambient

(1)

R

θJC

R

θJA

R

θJA

2.5

62.5
50

°C/W

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T

L

260 °C

(1) When surface mounted to an FR4 board using the minimum recommended pad size.

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.

Preferred devices are Motorola recommended choices for future use and best overall value.

Order this document

by MTB2N60E/D



SEMICONDUCTOR TECHNICAL DATA



TMOS POWER FET

2.0 AMPERES
600 VOLTS

R

DS(on)

= 3.8 OHM

Motorola Preferred Device

CASE 418B–02, Style 2

D2PAK

D

S

G



 Motorola, Inc. 1996

MTB2N60E

2

Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS

(TJ = 25°C unless otherwise noted)

Characteristic

Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage

(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)

V

(BR)DSS

600

—

—

480

—
—

Vdc

mV/°C

Zero Gate Voltage Drain Current

(VDS = 600 Vdc, VGS = 0 Vdc)
(VDS = 480 Vdc, VGS = 0 Vdc, TJ = 125°C)

I

DSS

—
—

—
—

0.25

1.0

µAdc

Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) I

GSS

— — 100 nAdc

ON CHARACTERISTICS (1)

Gate Threshold Voltage

(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)

V

GS(th)

2.0
—

3.1

8.5

4.0
—

Vdc

mV/°C

Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 1.0 Adc) R

DS(on)

— 3.0 3.8 Ohm

Drain–to–Source On–Voltage

(VGS = 10 Vdc, ID = 2.0 Adc)
(VGS = 10 Vdc, ID = 1.0 Adc, TJ = 125°C)

V

DS(on)

—
—

—
—

8.2

8.4

Vdc

Forward Transconductance (VDS = 50 Vdc, ID = 1.0 Adc) g

FS

1.0 — — mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

C

iss

— 435 — pF

Output Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

C

oss

— 100 —

Transfer Capacitance

f = 1.0 MHz)

C

rss

— 20 —

SWITCHING CHARACTERISTICS (2)

Turn–On Delay Time

t

d(on)

— 12 — ns

Rise Time

t

r

— 21 —

Turn–Off Delay Time

VGS = 10 Vdc,

RG = 18 Ω)

t

d(off)

— 30 —

Fall Time

G

= 18 Ω)

t

f

— 24 —

Q

T

— 13 — nC

(See Figure 8)

DS

= 400 Vdc, ID = 2.0 Adc,

Q

1

— 2.0 —

(VDS = 400 Vdc, ID = 2.0 Adc,

VGS = 10 Vdc)

Q

2

— 6.0 —

Q

3

— 5.0 —

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage (IS = 2.0 Adc, VGS = 0 Vdc)

(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C)

V

SD

—
—

1.0

0.9

1.6
—

Vdc

Reverse Recovery Time (IS = 2.0 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/µs)

t

rr

— 340 —

ns

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from the drain lead 0.25″ from package to center of die)

L

D

— 3.5 —

nH

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

L

S

— 7.5 —

nH

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.

Gate Charge

(VDD = 300 Vdc, ID = 2.0 Adc,

(V

MTB2N60E

3

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE (OHMS)

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

Figure 3. On–Resistance versus Drain Current

and Temperature

ID, DRAIN CURRENT (AMPS)

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

Figure 5. On–Resistance Variation with

Temperature

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 6. Drain–To–Source Leakage

Current versus Voltage

I

DSS

, LEAKAGE (nA)

TJ = 25°C

VGS = 10 V

15 V

2.9

4.1

3.5

VGS = 0 V

0 200 400

1

100

100 300 600500

TJ = 125°C

1000

3.9

4.3

4.5

3.7

3.3

3.1

10

0.5 1.5 3.52.51 2 43

100°C

D

I , DRAIN CURRENT (AMPS)

4

3

2

1

0

0 4 8 12 16 20

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

VGS = 10 V

7 V

6 V

5.5 V

5 V

TJ = 25°C

D

I , DRAIN CURRENT (AMPS)

8

6

4

2

0

0 2 4 6 8 10

VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

VDS ≥ 10 V

–55°C

TJ = 100°C

25°C

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE (OHMS)

12

8

4

0

0 1.5 3 4.5 6

ID, DRAIN CURRENT (AMPS)

VGS = 10 V

TJ = 25°C

100°C

–55°C

2.7

2.5
0

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE

(NORMALIZED)

TJ, JUNCTION TEMPERATURE (°C)

VGS = 10 V
ID = 1 A

–50 0 50 100 150125–25 25 75

2.5

2

1.5

1

0.5

0

MTB2N60E

4

Motorola TMOS Power MOSFET Transistor Device Data

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter­mined by how fast the FET input capacitance can be charged
by current from the generator.

The published capacitance data is difficult to use for calculat­ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I

G(AV)

) can be made from a rudimentary analysis of

the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a resis­tive load, VGS remains virtually constant at a level known as
the plateau voltage, V

SGP

. Therefore, rise and fall times may

be approximated by the following:
tr = Q2 x RG/(VGG – V

GSP

)

tf = Q2 x RG/V

GSP

where
VGG = the gate drive voltage, which varies from zero to V

GG

RG = the gate drive resistance
and Q2 and V

GSP

are read from the gate charge curve.

During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val­ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

= RG C

iss

In [VGG/(VGG – V

GSP

)]

t

d(off)

= RG C

iss

In (VGG/V

GSP

)

The capacitance (C

iss

) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal­culating t

d(on)

and is read at a voltage corresponding to the

on–state when calculating t

d(off)

.

At high switching speeds, parasitic circuit elements com­plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func­tion of drain current, the mathematical solution is complex.
The M OSFET output capacitance also c omplicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea­sure and, consequently, is not specified.

The resistive switching time variation versus gate resis­tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op­erated into an inductive load; however, snubbing reduces
switching losses.

GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Figure 7b. High Voltage Capacitance

Variation

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

C, CAPACITANCE (pF)

C

rss

C

iss

C

oss

TJ= 25°C
VGS= 0

1000

100

10

1

0.1
10 100 1000

C, CAPACITANCE (pF)

10 0 10 15 25

V

GS

V

DS

TJ = 25

°C

VDS = 0 V VGS = 0 V

600

400

200

0

20

C

iss

C

oss

C

rss

5 5

C

iss

C

rss

800

500

300

100

700

MTB2N60E

5

Motorola TMOS Power MOSFET Transistor Device Data

QG, TOTAL GATE CHARGE (nC)

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

I

S

, SOURCE CURRENT (AMPS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

Figure 8. Gate–To–Source and Drain–To–Source

Voltage versus Total Charge

0.50 0.70 0.80

0

2.0

0.65 0.75 0.850.55 0.60

1.6

1.2

0.8

0.4

1.8

1.4

1.0

0.6

0.2

VGS = 0 V
TJ = 25

°

C

15

12

9

6

3

0

0 4 8 12 16 20

500

V

DS

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

V

GS

, GATE–TO–SOURCE VOLTAGE (VOLTS)

400

300

200

100

0

V

DS

TJ = 25°C
ID = 2 A

Q

T

Q

1

Q

2

Q

3

VDS = 100 V
VDS = 250 V
VDS = 400 V

V

GS

t, TIME (ns)

1000

100

10

1

1 10 100 1000

RG, GATE RESISTANCE (OHMS)

TJ = 25°C
ID = 2 A
VDS = 300 V
VGS = 10 V

t

d(off)

t

d(on)

t

f
t

r

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum simultaneous d rain–to–source voltage and
drain current that a transistor can handle safely when it is for­ward biased. Curves are based upon maximum peak junc­tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–Gener­al Data and Its Use.”

Switching between the off–state and the on–state may tra­verse any load line provided neither rated peak current (IDM)
nor rated voltage (V

DSS

) is exceeded and the transition time
(tr,tf) do not exceed 10 µs. In addition the total power aver­aged over a complete switching cycle must not e xceed
(T

J(MAX)

– TC)/(R

θJC

).

A Power MOSFET designated E–FET can be safely used

in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dis­sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con­stant. The energy rating decreases non–linearly with an in­crease of p eak current i n avalanche a nd peak junction
temperature.

Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur­rent (ID), in accordance with industry custom. The energy rat­ing m ust b e derated for t emperature a s shown i n the
accompanying graph (Figure 12). Maximum energy at cur­rents below rated continuous ID can safely be assumed to
equal the values indicated.

MTB2N60E

6

Motorola TMOS Power MOSFET Transistor Device Data

SAFE OPERATING AREA

Figure 14. Diode Reverse Recovery Waveform

di/dt

t

rr

t

a

t

p

I

S

0.25 I

S

TIME

I

S

t

b

0

0.5

1

1.5

2.0

2.5

3

25 50 75 100 125 150

TA, AMBIENT TEMPERATURE (

°

C)

P

D

, POWER DISSIPATION (WATTS)

Figure 15. D2PAK Power Derating Curve

R

θJA

= 50°C/W
Board material = 0.065 mil FR–4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size ≈ 450 mils x 350 mils

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

Figure 13. Thermal Response

, SINGLE PULSE DRAIN–TO–SOURCE

AS

E

TJ, STARTING JUNCTION TEMPERATURE (°C)

AVALANCHE ENERGY (mJ)

Peak IL = 2 A
VDD = 50 V

200

150

100

50

0

25 50 75 100 125 150

10

1

0.1

0.01

0.1 1 10 100 1000

100 µs

10 µs

1 ms

10 ms

dc

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

I

D

, DRAIN CURRENT (AMPS)

R

DS(on)

LIMIT
THERMAL LIMIT
PACKAGE LIMIT

VGS = 20 V
SINGLE PULSE
TC = 25°C

1

0.1

0.01

0.00001 0.0001 0.001 0.01 0.1 1 10
t, TIME (SECONDS)

D = 0.5

0.2

r

(t)

, EFFECTIVE TRANSIENT THERMAL RESISTANCE

(NORMALIZED)

0.1

0.05

0.02

0.01

R

θ

JC

(t) = r(t) R

θ

JC

D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t

1

T

J(pk)

– TC = P

(pk)

R

θ

JC

(t)

P

(pk)

t

1

t

2

DUTY CYCLE, D = t1/t

2

SINGLE PULSE

MTB2N60E

7

Motorola TMOS Power MOSFET Transistor Device Data

INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE

RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface

between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.

mm

inches

0.33

8.38

0.08

2.032

0.04

1.016

0.63

17.02

0.42

10.66

0.12

3.05

0.24

6.096

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE

The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by T

J(max)

, the maximum rated

junction temperature of the die, R

θJA

, the thermal resistance
from the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data sheet,
PD can be calculated as follows:

PD =

T

J(max)

– T

A

R

θJA

The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device. For a D2PAK
device, PD is calculated as follows.

= 2.5 Watts

The 50°C/W for the D2PAK package assumes the use of the
recommended footprint on a glass epoxy printed circuit board
to achieve a power dissipation of 2.5 Watts. There are other
alternatives to achieving higher power dissipation from the
surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the power

dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
of using surface mount technology. For example, a graph of
R

θJA

versus drain pad area is shown in Figure 16.

Thermal Resistance versus Drain Pad

Area for the D2PAK Package (Typical)

2.5 Watts

A, Area (square inches)

Board Material = 0.0625

″

G–10/FR–4, 2 oz Copper

TA = 25°C

R , Thermal Resistance, Junction

to Ambient ( C/W)

θ

JA

°

60

70

50

40

30

20

1614121086420

3.5 Watts

5 Watts

Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.

PD =

150°C – 25°C

50°C/W

Figure 16.

MTB2N60E

8

Motorola TMOS Power MOSFET Transistor Device Data

SOLDER STENCIL GUIDELINES

Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. Solder
stencils are used to screen the optimum amount. These
stencils are typically 0.008 inches thick and may be made of
brass or stainless steel. For packages such as the SC–59,
SC–70/SOT–323, SOD–123, SOT–23, SOT–143, SOT–223,
SO–8, SO–14, SO–16, and SMB/SMC diode packages, the
stencil opening should be the same as the pad size or a 1:1
registration. This is not the case with the DPAK and D2PAK
packages. If one uses a 1:1 opening to screen solder onto the
drain pad, misalignment and/or “tombstoning” may occur due
to an excess of solder. For these two packages, the opening
in the stencil for the paste should be approximately 50% of the
tab area. The opening for the leads is still a 1:1 registration.
Figure 17 shows a typical stencil for the DPAK and D2PAK

packages. The pattern of the opening in the stencil for the
drain pad is not critical as long as it allows approximately 50%
of the pad to be covered with paste.

Figure 17. Typical Stencil for DPAK and

D2PAK Packages

SOLDER PASTE
OPENINGS

STENCIL

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.

• Always preheat the device.

• The delta temperature between the preheat and soldering

should be 100°C or less.*

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.

• The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

• When shifting from preheating to soldering, the maximum

temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should be

allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied during

cooling.

* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.

* Due to shadowing and the inability to set the wave height to
incorporate other surface mount components, the D2PAK is
not recommended for wave soldering.

MTB2N60E

9

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of control
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a figure
for belt speed. T aken together , these control settings make up
a heating “profile” for that particular circuit board. On
machines controlled by a computer, the computer remembers
these profiles from one operating session to the next. Figure
18 shows a typical heating profile for use when soldering a
surface mount device to a printed circuit board. This profile will
vary among soldering systems but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
type of solder used, and the type of board or substrate material
being used. This profile shows temperature versus time. The

line on the graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/in­frared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 177–189°C. When this type of
furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder joints.

STEP 1

PREHEAT

ZONE 1

“RAMP”

STEP 2

VENT

“SOAK”

STEP 3

HEATING

ZONES 2 & 5

“RAMP”

STEP 4

HEATING

ZONES 3 & 6

“SOAK”

STEP 5

HEATING

ZONES 4 & 7

“SPIKE”

STEP 6

VENT

STEP 7

COOLING

200

°

C

150

°

C

100

°

C

50

°

C

TIME (3 TO 7 MINUTES TOTAL)

T

MAX

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

MASS OF ASSEMBLY)

205

°

TO 219°C
PEAK AT
SOLDER JOINT

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

100°C

150°C

160

°

C

170°C

140

°

C

DESIRED CURVE FOR HIGH

MASS ASSEMBLIES

Figure 18. Typical Solder Heating Profile

MTB2N60E

10

Motorola TMOS Power MOSFET Transistor Device Data

PACKAGE DIMENSIONS

CASE 418B–02

ISSUE B

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

SEATING
PLANE

B

S

G

D

–T–

M

0.13 (0.005) T

2 31

4

3 PL

K

J

H

V

E

C

A

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.340 0.380 8.64 9.65
B 0.380 0.405 9.65 10.29
C 0.160 0.190 4.06 4.83
D 0.020 0.035 0.51 0.89
E 0.045 0.055 1.14 1.40
G 0.100 BSC 2.54 BSC
H 0.080 0.110 2.03 2.79
J 0.018 0.025 0.46 0.64
K 0.090 0.110 2.29 2.79
S 0.575 0.625 14.60 15.88
V 0.045 0.055 1.14 1.40

How to reach us:
USA /EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,

P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315

MFAX: [e-mail] – TOUCHTONE (602) 244–6609 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different
applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

MTB2N60E/D

*MTB2N60E/D

◊