Page 1
SEMICONDUCTOR TECHNICAL DATA
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N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower R
high–cell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable
to a Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I
DSS
and V
Specified at Elevated Temperature
DS(on)
• Short Heatsink Tab Manufactured — Not Sheared
• Specially Designed Leadframe for Maximum Power Dissipation
• Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
capabilities. This advanced
DS(on)
TMOS POWER FET
75 AMPERES
30 VOLTS
R
= 0.0065 OHM
DS(on)
CASE 418B–03
D2PAK
MAXIMUM RATINGS
Drain–to–Source Voltage V
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
Gate–to–Source Voltage — Continuous
Drain Current — Continuous
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C
Operating and Storage Temperature Range TJ, T
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 75 Apk, L = 0.1 mH, RG = 25 Ω)
Thermal Resistance — Junction–to–Case
Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 5.0 seconds T
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET and HDTMOS are trademarks of Motorola, Inc.
(TC = 25°C unless otherwise noted)
Rating Symbol Value Unit
— Non–Repetitive (tp ≤ 10 ms)
— Continuous @ 100°C
— Single Pulse (tp ≤ 10 µs)
(1)
— Junction–to–Ambient
— Junction–to–Ambient
(1)
V
V
I
E
R
R
R
DSS
DGR
GS
GSM
I
D
I
D
DM
P
D
stg
AS
θJC
θJA
θJA
L
30 Vdc
30 Vdc
±20
±20
75
59
225
150
1.2
2.5
–55 to 150 °C
280
0.8
62.5
50
260 °C
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
mJ
°C/W
Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1997
1
Page 2
MTB1306
)
f = 1.0 MHz)
V
G
)
(
DS
,
D
,
(
S
,
GS
,
ELECTRICAL CHARACTERISTICS
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Zero Gate Voltage Drain Current
(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) I
ON CHARACTERISTICS
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Static Drain–to–Source On–Resistance
(VGS = 10 Vdc, ID = 38 Adc)
(VGS = 5.0 Vdc, ID = 38 Adc)
Drain–to–Source On–Voltage
(VGS = 10 Vdc, ID = 75 Adc)
(VGS = 10 Vdc, ID = 38 Adc, TJ = 150°C)
Forward Transconductance (VDS = 3.0 Vdc, ID = 20 Adc) g
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
Reverse Recovery Time
Reverse Recovery Stored Charge Q
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(1)
(T
= 25°C unless otherwise noted)
J
Characteristic
(VDS = 25 Vdc, VGS = 0 Vdc,
(2)
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C)
f = 1.0 MHz
(VDD = 15 Vdc, ID = 75 Adc,
(VDS = 24 Vdc, ID = 75 Adc,
(IS = 20 Adc, VGS = 0 Vdc)
(IS = 20 Adc, VGS = 0 Vdc,
= 5.0 Vdc,
GS
RG = 4.7 Ω)
VGS = 5.0 Vdc)
dIS/dt = 100 A/µs)
Symbol Min Typ Max Unit
V
(BR)DSS
I
DSS
GSS
V
GS(th)
R
DS(on)
V
DS(on)
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
V
SD
t
rr
t
a
t
b
RR
30 — —
—
—
— — 100 nAdc
1.0 1.5 2.0
—
—
—
—
15 55 — mhos
— 2560 3584 pF
— 1305 1827
— 386 772
— 17 35 ns
— 170 340
— 68 136
— 145 290
— 50 70 nC
— 8.3 —
— 25.3 —
— 17.2 —
—
—
— 84 —
— 35 —
— 53 —
— 0.13 — µC
—
—
5.8
7.4
0.44
—
0.75
0.64
10
100
6.5
8.5
0.5
0.38
1.1
—
Vdc
µAdc
Vdc
m
W
Vdc
Vdc
ns
2
Motorola TMOS Power MOSFET Transistor Device Data
Page 3
TYPICAL ELECTRICAL CHARACTERISTICS
MTB1306
150
125
TJ = 25°C
100
75
50
, DRAIN CURRENT (AMPS)
D
I
25
0
0 0.25 0.75 1.25 1.5 2.0
VGS = 10 V
0.5 1.0 1.75
VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)
5.0 V
4.0 V
Figure 1. On–Region Characteristics
0.010
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.002
, DRAIN–TO–SOURCE RESIST ANCE (OHMS)
0.001
0
DS(on)
R
20 40 80
TJ = 100°C
25°C
–55°C
60 100 140 60 80 100
ID, DRAIN CURRENT (AMPS)
VGS ≥ 10 V
120
180
VDS ≥ 10 V
160
140
120
100
80
60
, DRAIN CURRENT (AMPS)
D
40
I
20
0
2.0 2.5 3.0 3.5 4.0 4.5
25°C
125°C
TJ = –55°C
VGS, GATE–T O–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0.009
TJ = 25°C
0.008
0.007
0.006
0.005
, DRAIN–TO–SOURCE ON–RESISTANCE (OHMS)
0.004
20 40 90
DS(on)
R
30 50 70 150120 140130110
VGS = 5.0 V
10 V
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and T emperature
2.0
VGS = 10 V
ID = 38 A
1.5
1.0
(NORMALIZED)
0.5
, DRAIN–TO–SOURCE RESIST ANCE
DS(on)
R
0
–50
–25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (
Figure 5. On–Resistance Variation with
Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
10,000
1000
, LEAKAGE (nA)
100
DSS
I
10
5.0
°
C)
10 15 20 25 30
VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)
TJ = 125°C
100°C
Figure 6. Drain–T o–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
Page 4
MTB1306
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
) can be made from a rudimentary analysis of
G(A V)
the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, V
. Therefore, rise and fall times may
SGP
be approximated by the following:
tr = Q2 x RG/(VGG – V
tf = Q2 x RG/V
GSP
GSP
)
where
VGG = the gate drive voltage, which varies from zero to V
GG
RG = the gate drive resistance
and Q2 and V
are read from the gate charge curve.
GSP
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
t
d(off)
= RG C
= RG C
In [VGG/(VGG – V
iss
In (VGG/V
iss
GSP
)]
GSP
)
The capacitance (C
) is read from the capacitance curve at
iss
a voltage corresponding to the off–state condition when calculating t
on–state when calculating t
and is read at a voltage corresponding to the
d(on)
d(off)
.
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently , is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
C, CAPACITANCE (pF)
9000
8000
7000
6000
5000
4000
3000
2000
1000
VDS = 0 V VGS = 0 V
C
iss
C
rss
0
–5.0 5.0
–10 0 10 15 20 25
V
GS
VGS OR VDS, GATE–TO–SOURCE OR DRAIN–T O–SOURCE
V
DS
VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
C
C
C
iss
oss
rss
4
Motorola TMOS Power MOSFET Transistor Device Data
Page 5
10
7.5
QT
MTB1306
V
18
15
12
V
GS
DS
, DRAIN–TO–SOURCE VOL TAGE (VOLTS)
10,000
1000
VDD = 15 V
ID = 75 A
VGS = 5.0 V
TJ = 25
°
C
5.0
2.5
, GATE–T O–SOURCE VOLTAGE (VOLTS)
GS
V
Q1
Q3
0
0
10 20 30 40
Q2
V
DS
QG, TOTAL GATE CHARGE (nC)
TJ = 25°C
ID = 75 A
50
9.0
6.0
3.0
0
60
Figure 8. Gate–T o–Source and Drain–To–Source
V oltage versus Total Charge
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high
t
t, TIME (ns)
100
10
1.0 10 100
r
t
f
t
d(off)
t
d(on)
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.
20
VGS = 0 V
18
TJ = 25
°
16
14
12
10
8.0
6.0
, SOURCE CURRENT (AMPS)
S
4.0
I
2.0
0
0.45
C
VSD, SOURCE–TO–DRAIN VOL TAGE (VOLTS)
Figure 10. Diode Forward V oltage versus Current
Motorola TMOS Power MOSFET Transistor Device Data
0.60
0.65
0.70
0.750.50 0.55
5
Page 6
MTB1306
, SOURCE CURRENT
S
I
Figure 11. Reverse Recovery T ime (trr)
Standard Cell Density
t
rr
High Cell Density
t
rr
t
b
t
a
t, TIME
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (V
) is exceeded and the transition time
DSS
(tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed
(T
J(MAX)
– TC)/(R
θJC
).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
1000
VGS = 10 V
SINGLE PULSE
TC = 25
°
100
10
C
1.0 ms
10 ms
dc
able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.
280
240
200
160
120
ID = 75 A
, DRAIN CURRENT (AMPS)
1.0
D
I
0.1
0.1 1.0 100
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
10 150
VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
6
80
AVALANCHE ENERGY (mJ)
40
, SINGLE PULSE DRAIN–TO–SOURCE
AS
E
0
25 50 75 100 125
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 13. Maximum Avalanche Energy versus
Starting Junction T emperature
Motorola TMOS Power MOSFET Transistor Device Data
Page 7
1.0
D = 0.5
0.2
0.1
0.1
0.05
0.02
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
0.01
SINGLE PULSE
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
0.01
t, TIME (s)
Figure 14. Thermal Response
di/dt
I
S
t
t
a
P
(pk)
t
1
DUTY CYCLE, D = t1/t
rr
t
b
MTB1306
R
(t) = r(t) R
θ
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
2
TIME
READ TIME AT t
T
J(pk)
t
2
– TC = P
θ
(pk)
JC
1
R
(t)
θ
JC
t
p
0.25 I
S
I
S
Figure 15. Diode Reverse Recovery Waveform
Motorola TMOS Power MOSFET Transistor Device Data
7
Page 8
MTB1306
–T–
SEATING
PLANE
–B–
G
4
231
S
D
3 PL
0.13 (0.005) T
M
P ACKAGE DIMENSIONS
C
A
K
H
M
B
CASE 418B–03
(D2P AK)
ISSUE C
E
V
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIM MIN MAX MIN MAX
A 0.340 0.380 8.64 9.65
B 0.380 0.405 9.65 10.29
C 0.160 0.190 4.06 4.83
D 0.020 0.035 0.51 0.89
E 0.045 0.055 1.14 1.40
G 0.100 BSC 2.54 BSC
H 0.080 0.110 2.03 2.79
J 0.018 0.025 0.46 0.64
K 0.090 0.110 2.29 2.79
S 0.575 0.625 14.60 15.88
V 0.045 0.055 1.14 1.40
MILLIMETERSINCHES
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
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Motorola TMOS Power MOSFET Transistor Device Data
Mfax is a trademark of Motorola, Inc.
MTB1306/D
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