Page 1
2-45
Features
• 256 x 256 channel non-blocking switch
• Programm able frame i nteg rity for w ideba nd
channels
• Automatic identification of ST-BUS/GCI
interface bac kpla nes
• Per chann el tristat e cont rol
• Patented m es sage m od e
• Non-mult iplex ed mic roproce ssor i nterfa ce
• Single +5 vol t suppl y
• Available in DIP-40 , PLCC- 44 a nd QF P-44
packages
• Pin compa tible wit h MT 8980 d evic e
Applications
• Medium si ze digi tal switch mat rices
• Hyperch annel switch ing (e.g ., ISDN H0)
• ST-BUS/MVIP
™
interface functions
• Serial bus co ntrol and m onitori ng
• Centralized voice processing systems
• Data multiplexer
Description
The MT8985 Enhanced Digital Switch device is an
upgraded version of the popular MT8980D Digital
Switch (DX). It is pin compatible with the MT8980D
and retains all of the MT8980D's functionality. This
VLSI device is designed for switching PCM-encoded
voice or data, under microprocessor control, in digital
exchanges, PBXs and any ST-BUS/MVIP
environment. It provides simultaneous connections
for up to 256 64kb/s channels. Each of the eight
serial inputs and outputs consist of 32 64 kbit/s
channels multiplexed to form a 2048 kbit/s stream.
As the main function in switching applications, the
device provides per-channel selection between
variable or constant throughput delays. The constant
throughput delay feature allows grouped channels
such as ISDN H0 to be switched through the device
maintaining its sequence integrity. The MT8985 is
ideal for medium sized mixed voice/data switch and
voice processing applications.
Figure 1 - Functional Block Diagram
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
Serial
to
Parallel
Converter
Data
Memory
Frame
Counter
Control Register
Control Interface
Output
MUX
Connection
Memory
Parallel
to
Serial
Converter
CS
R/W A5/A0DTA D7/
D0
CSTo
C4i
F0i
VDDV
SS
ODE
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
DS
ISSUE 4 May 1995
MT8985
Enhanced Digital Switch
CMOS ST-BUS FAMILY
Ordering Information
MT8985 AC 40 Pin Cerami c DIP
MT8985 AE 40 P in Pla stic DIP
MT8985 AP 44 P in PLC C
MT8985 AL 44 Pin QFP
-40°C to +85°C
Page 2
MT8985
2-46
Figure 2 - Pin Connections
Pin Description
Pin #
Name Description
40
DIP44PLCC44QFP
1240DTAData Acknowledgeme nt (Open Drain Output ). Thi s active low outp ut indica tes tha t
a data bus transfer is complete. A pull-up resistor is required at this output .
2-9 3-5
7-11
41-43
1-5
STi0-
STi7
ST-BUS Input 0 to 7 (Inputs). Serial data input streams. These stream s have 32
channels at data rates of 2.048 Mbit/s.
10 12 6 V
DD
+5 Volt Power Supply rail.
11 13 7 F0i
Frame Pulse (Input): This input accepts and autom atically ident ifies fram e
synchronization signals formatted accord ing to different backplane specifications
such as ST-BUS and GCI.
12 14 8 C4i
Clock (Input). 4.096 MHz serial clock for shifting data in and out of the data streams.
13-18 1 5-17
19-21
9-11
13-15
A0-A5 Addres s 0 to 5 (Inputs). These lines provide the address to MT8985 internal
registers.
19 22 16 DS Data S trob e (Input). This is the input for the acti ve high data strobe on the
microprocessor interface. This input operates with CS
to enable the internal read and
write generation.
20 23 17 R/W
Read/Write (Input). This input controls the direction of the data bus lines (D0-D7)
during a microprocessor access.
DTA
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
VDD
F0i
C4i
A0
A1
A2
A3
A4
A5
DS
CSTo
ODE
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
VSS
D0
D1
D2
D3
D4
D5
D6
D7
CS
16 5 4 3 2 4443424140
7
8
9
10
11
12
13
14
15
16
39
38
37
36
35
34
33
32
31
30
231819 20 2122 2425 26 2728
17
29
STi3
STi4
STi5
STi6
STi7
VDD
F0i
C4i
A0
A1
A2
STo3
STo4
STo5
STo6
STo7
VSS
D0
D1
D2
D3
D4
NC
STi1
DTA
ODE
STo1
NC
STi2
STi0
CSTo
STo0
STo2
NC
A4
DS
CS
D6
NC
A3
A5
R/W
D7
40 PIN CERDIP/PLASTIC DIP
44 PIN PLCC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
R/W
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
D5
39
4443424140
3837363534
1
2
3
4
5
6
7
8
9
10
33
32
31
30
29
28
27
26
25
24
17
1213141516
1819202122
11
23
44 PIN QFP
STi3
STi4
STi5
STi6
STi7
VDD
F0i
C4i
A0
A1
A2
NC
A4
DS
CS
D6
NC
A3
A5
R/W
D7
D5
STo3
STo4
STo5
STo6
STo7
VSS
D0
D1
D2
D3
D4
NC
STi1
DTA
ODE
STo1
NC
STi2
STi0
CSTo
STo0
STo2
Page 3
MT8985
2-47
21 24 18 CS Chip Select (Input). A cti ve low input enabling a mi croprocessor read or write of
control register or internal me mori e s.
22-29 2 5-27
29-33
19-21
23-27
D7-D0 Data Bus 7 to 0 (Bidirectional). These pins provide microprocessor access to data
in the internal control register, connect memory high, connect memory low and data
memory.
30 34 28 V
SS
Ground R ai l.
31-38 3 5-39
41-43
29-33
35-37
STo7-
STo0
ST-BUS Outputs 7 to 0 (Three-state Outp uts). Serial data output streams. These
streams are composed of 32 channels at data rates of 2.048 Mbit/s.
39 44 38 ODE Output Drive Enable (Input). This is an output enable for the STo0 to STo7 serial
outputs. If this input is low STo0-7 are high impedance. If this input is high each
channel may still be put into high impedance by software control.
40 1 39 CSTo Control ST-BUS Output (Output). This output is a 2.048 Mb/s line which cont ains
256 bits per frame. The level of each bit is controlled by the contents of the CSTo bit
in the Connect Memory high locations.
6, 18,
28,
40
12,22
34,
44
NC No Connection.
Pin Description
Pin #
Name Description
40
DIP44PLCC44QFP
Functional Description
With the integration of voice, video and data services
into the same network, there has been an increasing
demand for systems which ensure that data at N x
64 Kbit/s rates maintain frame sequence integrity
while being transported through time slot
interchange circuits. Existing requirements demand
time slot interchange devices performing switching
with constant throughput delay while guaranteeing
minimum delay for voice channels.
The MT8985 device provides both functions and
allows existing systems based on the MT8980D to
be easily upgraded to maintain the data integrity
while multiple channel data are transported. The
device is designed to switch 64 kbit/s PCM or N x 64
kbit/s data. The MT8985 can provide both frame
integrity for data applications and minimum
throughput switching delay for voice applications on
a per channel basis.
By using Mitel Message mode capability, the
microprocessor can access input and output time
slots on a per channel basis to control devices such
as the MITEL MT8972, ISDN Transceivers and T1/
CEPT trunk interfaces through the ST-BUS interface.
Different digital backplanes can be accepted by the
MT8985 device without user's intervention. The
MT8985 device provides an internal circuit that
automatically identifies the polarity and format of
frame synchronization input signals compatible to
ST-BUS and GCI in te rf ac e s.
Device Operation
A functional block diagram of the MT8985 device is
shown in Figure 1. The serial ST-BUS streams
operate continuously at 2.048 Mb/s and are arranged
in 125 µs wide frames each containing 32 8-bit
channels. Eight input (STi0-7) and eight output
(STo0-7) serial streams are provided in the MT8985
device allowing a complete 256 x 256 channel nonblocking switch matrix to be constructed. The serial
interface clock for the device is 4.096 MHz, as
required in ST-BUS and GCI specifications.
Data Memory
The received serial data is converted to parallel
format by the on-chip serial to parallel converters
and stored sequentially in a 256-position Data
Memory. The sequential addressing of the Data
Memory is generated by an internal counter that is
reset by the input 8 kHz frame pulse (F0i
) marking
the frame boundaries of the incoming serial data
streams.
Depending on the type of information to be switched,
the MT8985 device can be programmed to perform
Page 4
MT8985
2-48
time slot interchange functions with different
throughput delay capabilities on a per-channel basis.
For voice applications, the variable delay mode can
be selected ensuring minimum throughput delay
between input and output data. In multiple or
grouped channel data applications, the constant
delay mode can be selected maintaining the integrity
of the information through the switch.
Data to be output on the serial streams may come
from two sources: Data Memory or Connect Memory.
Location s in th e Con nect M emory, which is split into
HIGH and LOW parts, are associated with particular
ST-BUS output streams. When a channel is due to
be transmitted on an ST-BUS output, the data for the
channel can either be switched from an ST-BUS
input (connection mode) or it can be originated from
the microprocessor (message mode). If a channel is
configured in connection mode, the source of the
output data is the Data Memory. If a channel is
configured in message mode, the source of the
output data is the Connect Memory Low. Data
destined for a particular channel on the serial output
stream is read from the Data or Connect Memory
Low during the previous channel time slot. This
allows enough time for memory access and internal
parallel to serial conversion.
Connectio n and M essag e Mod es
In connection mode, the addresses of input source
for all output channels are stored in the Connect
memory Low. The Connect Memory Low locations
are mapped to each location corresponding to an
output 64 kb/s channel. The contents of the Data
memory at the selected address are then transferred
to the parallel to serial converters. By having the
output ch annel to specify the input cha nnel through
the connect memory, the user can route the same
input channel to several output channels, allowing
broadcasting facility in the switch.
In message mode the CPU writes data to the
Connect Memory Low locations which correspond to
the output link and channel number. The contents of
the Connect Memory Low are transferred to the
parallel to serial converter one channel before it is to
be output. The Connect Memory Low data is
transmitted each frame to the output until it is
changed by the CPU.
The per-channel functions available in the MT8985
are controlled by the Connect Memory High bits,
which determine whether individual output channels
are selected into specific conditions such as:
message or connection mode, variable or constant
throughput delay modes, output drivers enabled or in
three-state condition. In addition, the Connect
Memory High provides one bit to allow the user to
control the state of the CSTo output pin.
If an output channel is set to three-state condition,
the TDM serial stream output will be placed in high
impedance during that channel time. In addition to
the per-channel three-state control, all channels on
the TDM outputs can be placed in high impedance at
one time by pulling the ODE input pin in LOW. This
overrides the individual per-channel programming on
the Connect Memory High bits.
The Connect Memory data is received via the
Microprocessor Interface at D0-D7 lines. The
addressing of the MT8985 internal registers, Data
and Connect memories is performed through
address input pins and some bits of the device's
Control register. The higher order address bits come
from the Control register, which may be written or
read through the microprocessor interface. The
lower order address bits come directly from the
external address line inputs. For details on the
device addressing, see Software Control and Control
register description.
Serial I nterf ace Timing
The MT8985 master clock (C4i
) is a 4.096 MHz
allowing serial data link configuration at 2.048 Mb/s
to be implemented. The MT8985 frame
synchronization pulse can be formatted according to
ST-BUS or GCI interface specifications; i.e., the
frame pulse can be active in HIGH (GCI) or LOW
(ST-BUS). The MT8985 device automatically detects
the presence of an input frame pulse and identifies
the type of backplane present on the serial interface.
Upon determining the correct interface connected to
the serial port, the internal timing unit establishes the
appropriate serial data bit transmit and sampling
edges. In ST-BUS mode, every second falling edge
of the 4.096 MHz clock marks a bit boundary and the
input data is clocked in by the rising edge, three
quarters of the way into the bit cell. In GCI mode,
every second rising edge of the 4.096 MHz clock
marks the bit boundary while data sampling is
performed during the falling edge, at three quarters
of the bit boundaries.
Delay throu gh the M T89 85
The transfer of information from the input serial
streams to the output serial streams results in a
delay through the MT8985 device. The delay through
the MT8985 device varies according to the mode
selected in the V/C bit of the connect memory high.
Page 5
MT8985
2-49
Variable Delay mode
The delay in this mode is dependent only on the
combination of source and destination channels and
it is not dependent on the input and output streams.
The minimum delay achievable in the MT8985
device is 3 time slots. In the MT8985 device, the
information that is to be output in the same channel
position as the information is input (position n),
relative to frame pulse, will be output in the following
frame (channel n, frame n+1). The same occurs if
the input channel has to be output in the two
channels succeeding (n+1 and n+2) the channel
position as the information is input.
The information switched to the third timeslot after
the input has entered the device (for instance, input
channel 0 to output channel 3 or input channel 30 to
output channel 1), is always output three channels
later.
Any switching configuration that provides three or
more timeslots between input and output channels,
will have a throughput delay equal to the difference
between the output and input channels; i.e., the
throughput delay will be less than one frame. Table 1
shows the possible delays for the MT8985 device in
Variable Delay mode:
Ta ble 1
Constant Delay Mode
In this mode frame integrity is maintained in all
switching configurations by making use of a multiple
Data-Memory buffer technique where input channels
written in any of the buffers during frame N will be
read out during frame N+2. In the MT8985, the
minimum throughput delay achiev-able in Constant
Delay mode will be 32 time slots; for example, when
input time slot 32 (channel 31) is switched to output
time slot 1 (channel 0). Likewise, the maximum delay
is achieved when the first time slot in a frame
(channel 0) is switched to the last time slot in the
frame (channel 31), resulting in 94 time slots of
delay.
To summarize, any input time slot from input frame N
will be always switched to the destination time slot
Input
Channel
Output
Channel
Through pu t Del ay
n m=n, n+1 or
n+2
m-n + 32 timeslots
n m>n+2 m-n time slots
n m<n 32-(n-m) time slots
on output frame N+2. In Constant Delay mode, the
device throughput delay is calculated according to
the following formula:
DELAY = [32 + (32 - IN) + (OUT - 1)];
(expressed in number of time slots)
Where: IN is the number of the input time slot
(from 1 to 32).
OUT is the number of the output time slot
(from 1 to 32).
Microprocessor Port
The MT8985 microprocessor port has pin
compatibility with Mitel MT8980 Digital Switch device
providing a non-multiplexed bus architecture. The
parallel port consists of an 8 bit parallel data bus
(D0-D7), six address input lines (A0-A5) and four
control lines (CS
, DS, R/W and DTA). This parallel
microport allows the access to the Control registers,
Connection Memory High, Connection Memory Low
and the Data Memory. All locations are read/written
except for the data memory which can be read only.
Accesses from the microport to the connection
memory and the data memory are multiplexed with
accesses from the input and output TDM ports. This
can cause variable Data Acknowledge delays (DTA
).
In the MT8985 device, the DTA
output provides a
maximum acknowledgement delay of 800 ns for
read/write operations in the Connection Memory.
However, for operations in the Data Memory
(Message Mode), the maximum acknowledgement
delay can be 1220 ns.
Figure 3 - Ad dres s Mem ory M ap
Note: "x" Don’t care
Software Control
The address lines on the microprocessor interface
give access to the MT8985 internal registers and
memories. If the A5,A1,A0 address line inputs are
A5 A4 A3 A2 A1 A0 LOCATION
0
1
1
1
1
1
1
1
1
X
0
0
•
•
•
•
•
1
X
0
0
•
•
•
•
•
1
X
0
0
•
•
•
•
•
1
0
0
0
•
•
•
•
•
1
0
0
1
•
•
•
•
•
1
Control Register
Channel 0
Channel 1
•
•
•
•
•
Channel 31
Page 6
MT8985
2-50
Figure 4 - Control Register Bits
x = Don’t care
BIT NAME DESCRIPTION
7 SM Split Memory. When 1, all subsequent reads are from the Data Memor y and writes are to
the Connection Memory Lo w, except when the Control Register is accessed again. The
Memory Select bits need to be set to specify the m emo ry for the operat ions. When 0, the
Memory Select bits specify the m em o ry for subsequent opera tio ns. In either case, th e
Stream Address Bits select the subsection of the memory which is made available.
6 ME Message Enable. When 1, the contents of the Connection Memory Low are output on the
Serial Output streams except when in High Impedan ce. When 0, the Connection Memory
bits for each channel determine what is output.
4-3 MS1-MS0 Memory S el ect Bits. The memory sel ect bits opera te as follow s:
0-0 - Not to be used
0-1 - Data Memory (read only from the CPU)
1-0 - Connection Memory Low
1-1 - Connection Memory High
2-0 ST A2-0 Stream Address Bits 2-0. The number expressed in binary notation on these bits refers to
the input or output ST-BUS stream which corresponds to the subsection of memo ry made
accessible for subsequent operations.
SM ME X MS1 MS0 STA2 STA1 STA0
76543210
LOW, then the MT8985 Internal Control Register is
addressed (see Figure 3). If A5 input line is HIGH,
then the remaining address input lines are used to
select Memory subsections of 32 locations
corresponding to the number of channels per input or
output stream. As explained in the Control register
description, the address input lines and the Stream
Address bits (STA) of the Control register give the
user the capability of selecting all positions of the
MT8985 Data and Connect memories.
The data in the Control register consists of Split
memory and Message mode bits, Memory select and
Stream Address bits (see Figure 4). The memory
select bits allow the Connect Memory HIGH or LOW
or the Data Memory t o be chosen, and the Stream
Address bits define an internal memory subsections
corresponding to input or output ST-BUS streams.
Bit 7 (Split Memory) of the Control register allows
split memory operation whereby reads are from the
Data memory and writes are to the Connect Memory
LOW.
The Message Enable bit (bit 6) places every output
channel on every output stream in message mode;
i.e., the contents of the Connect Memory LOW
(CML) are output on the ST-BUS output streams
once every frame unless the ODE input pin is LOW.
If ME bit is HIGH, then the MT8985 behaves as if bits
2 (Message Channel) and 0 (Output Enable) of every
Connect Memory HIGH (CMH) loca tions were set to
HIGH, regardless of the actual value. If ME bit is
LOW, then bit 2 and 0 of each Connect Memory
HIGH location operates normally. In this case, if bit 2
of the CMH is HIGH, the associated ST-BUS output
channel is in Message mode. If bit 2 of the CMH is
LOW, then the contents of the CML define the source
information (stream and channel) of the time slot that
is to be switched to an output.
If the ODE input pin is LOW, then all serial outputs
are high-impedance. If ODE is HIGH, then bit 0
(Output Enable) of the CMH location enables (if
HIGH) or disables (if LOW) the output drivers for the
corresponding individual ST-BUS output stream and
channel.
The contents of bit 1 (CSTo) of each Connection
Memory High location (see Figure 5) is output on
CSTo pin once every frame. The CSTo pin is a 2048
Mbit/s outp ut wh i c h car rie s 2 56 b its. If C STo bit is set
HIGH, the corresponding bit on CSTo output is
Page 7
MT8985
2-51
Figure 5 - Connection Memory High Bits
x = Don’t care
Figure 6 - Connection Memory Low Bits
BIT NAME DESCRIPTION
6V
/C Variable/Constant Throughput Delay Mode. This bit is used to select between Variable
(LOW) and Constant Delay (HIGH) modes on a per-channel basis.
2 MC Message Ch a nne l. When 1, the content s of the corresponding locat ion in Connect ion
Memory Low are output on the corresponding channel and stream. When 0, the contents
of the programmed location in Conne ction M em or y Low act as an address for the Data
Memory and so determine the source of the connection to the location’s channel and
stream.
1 CSTo CSTo Bit. This bit drives a bit time on the CSTo output pin.
0 OE Output Enable. This bit enables the output drivers on a per-channel basis. This allows
individual channels on individual stream s to be made high-im peda nce, allo wing swit ch
matrices to be constructed. A HIGH enables the driver and a LOW disables it.
BIT NAME DESCRIPTION
7-5 SAB2-0* Source Stream Address bits. These three bits are used to select eight sou rce streams
for the connection. Bit 7 of each word is the most significant bit.
4-0* CAB4-0* Source Channel Address bits 0-4. These five bits are used to select 32 different source
channels for the connection (The ST-BUS stream where the channel is present is defined
by bits SAB2-0). B it 4 is the most signif icant bit.
*
If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire 8 bits are output
on the channel and stream associated with this location. Otherwise, the bits are used as indicated to define the source of the
connection which is output on the channel and stream associated with this location.
XV/C X X X MC CSTo OE
76543210
SAB2 SAB1 SAB0 CAB4 CAB3 CAB2 CAB1 CAB0
76543210
transmitted in HIGH. If CSTo bit is LOW, the
corresponding bit on the CSTo output is transmitted
in LOW. The contents of the 256 CSTo bits of the
CMH are transmitted sequentially on to the CSTo
output pin and are synchronous to the ST-BUS
streams. To allow for delay in any external control
circuitry the contents of the CSTo bit is output one
channel before the corresponding channel on the
ST-BUS streams. For example, the contents of CSTo
bit in position 0 (ST0, CH0) of the CMH, is
transmitted synchronously with ST-BUS channel 31,
bit 7. The contents of CSTo bit in position 32 (ST1,
CH0) of the CMH is transmitted during ST-BUS
channel 31 bit 6.
Bit V/C (Variable/Constant Delay) on the Connect
Memory High locations allow per-channel selection
between Variable and Constant throughput delay
capabilities.
Initialization of the MT8985
On initialization or power up, the contents of the
Connection Memory High can be in any state. This
is a potentially hazardous condition when multiple
MT8985 ST-BUS outputs are tied together to form
matrices, as these outputs may conflict. The ODE
pin should be held low on power up to keep all
outputs in the high impedance condition.
Page 8
MT8985
2-52
Figure 7 - Typical Exchange, PBX or Multiplexer Configuration
A
A
A
A
S/U
Basic Rate Line Card
MT8930/31
MT8910
MT8972
ST-BUS
To other lines
Layers
2 & 3
Entity
MT8940/
MT8941
ROUTING
MATRIX
MT8985’s
MH89760/
MH89790
MT8920
µC
ST-BUS
ST-BUS
T1/E1
Link
To other lines
Primary Rate Card
C
P
U
During the microprocessor initialization routine, the
microprocessor should program the desired active
paths through the matrices, and put all other
channels into the high impedance state. Care should
be taken that no two connected ST-BUS outputs
drive the bus simultaneously. When this process is
complete, the microprocessor controlling the
matrices can bring the ODE signal high to relinquish
high impedance state control to the CMH
b
0s.
Applications
Typical Exchange, PBX or Multiplexer
Figure 7 shows a typical implementation of line cards
being interconnected through a central routing matrix
that can scale up in channel capacity to
accommodate different number of ports depending
on the application. In a configuration where the
switched services utilize concatenated or grouped
time slots to carry voice, data and video (channels of
128, 256 Kb/s, ISDN H0 and others), the central
routing matrix has to guarantee constant throughput
delay to maintain the sequence integrity between
input and output channels. Figure 7 shows an
example where the MT8985 device guarantees data
integrity when data flows from the T1/E1 to the S/U
interface links and vice-versa. Modern technologies
available today such as Frame Relay network using
dedicated fractional T1 are one of the key
applications for the MT8985 device.
Low Latency Isochronous Network
In today's local working group environment, there is
an increasing demand for solutions on
interconnection of desktop and telephone systems
so that mixed voice, data and video services can be
grouped together in a reliable network allowing the
deployment of multimedia services. Existing
multimedia applications require a network with
Page 9
MT8985
2-53
Figure 8a - Private Isochronous Network
AAA
A
AAA
AAA
AA
Access to
Public
Network
Analog Connections
• • • • • •
ISDN Desktops
n x 64
Connections
(e.g. Video)
Isochronous Network
Server 1
Server 2
Server 3
Server 4
T1
T1
E1
• • • • • •
• • • • • •
T1/E1
(2B+D)
predictable data transfer delays that can be
implemented at a reasonable cost. The Low Latency
Isochronous Network is one of the alternatives that
system designers have chosen to accommodate this
requirement (see Figure 8a). This network can be
implemented using existing TDM transmission media
devices such as ISDN Basic (S or U) and Primary
rates trunks (T1 and CEPT) to transport mixed voice
and data signals in grouped time slots; for example,
2B channels in case of ISDN S or U interfaces or up
to 32 channels in case of a CEPT link.
Figure 8b shows a more detailed configuration
whereby several PCs are connected to form an
Isochronous network. Several services can be
interconnected within a single PC chassis through
the standardized Multi Vendor Integration Protocol
(MVIP). Such an interface allows the distribution and
interconnection of services like voice mail, integrated
voice response, voice recognition, LAN gateways,
key systems, fax servers, video cards, etc.
The information being exchanged between cards
through the MVIP interface on every computer as
well as between computers through T1 or CEPT links
is, in general, of mixed type where 64Kb/s and
N*64Kb/s channels are grouped together. When
such a mixed type of data is transferred between
cards within one chassis or from one computer to
another, the sequence integrity of the concatenated
channels has to be maintained. The MT8985 device
suits this application and can be used to form a
complete non-blocking switch matrix of 512 channels
(see Figure 9). This allows 8 pairs of ST-BUS
streams to be dedicated to the MVIP side whereas
the remaining 8 pairs are used for local ancilliary
functions in typical dual T1/E1 interface applications
(Figure 10).
Another application of the MT8985 in an MVIP
environment is to build an ISDN S-interface card
(Figure 11). In this card, 7 pairs of ST-BUS streams
are connected to the MVIP interface while the
remaining p air is res erved for th e interconne ction of
MITEL MT8930 (SNIC), MT8992 (H-PHONE) and
the MVIP in te rfa c e.
Page 10
MT8985
2-54
Figure 8b - Implementation of an Isochronous Network Using Mitel Components
Server 1
MH89760B
MH89790B
ST-BUS
MT8985s
(x4)
MT8930B
MT8930B
•
•
•
•
•
•
•
•
•
•
•
•
MVIP
BUS
ISDN
S-Interface
Local T1/E1 Link
MVIP
BUS
Server 3
(256 PORT
SWITCH MODULE) Server 3
MH89760B/79 0B
MH89760B/79 0B
MH89760B/79 0B
ST-BUS
MT8985s
(x4)
HDLC
MT8985
MT89 85
MT89 85
MT8985
ST-BUS
MH89760B
MH89790B
Dual T1/E1 Card
MH89760B
MH89790B
MT8972B
or
ANALOG
MT8985s
(x4)
Server 2
MVIP
BUS
ST-BUS
To Video, Data,
Fax Services
Local Environment Network Access
•
•
•
•
•
•
Local T1/E1 Link
T1
E1
To Video, Data, Fax and other services
Public
Page 11
MT8985
2-55
Figure 9 - 512-Channel Switch Array
Figure 10 - Dual T1/E1 Card Functional Block Diagram
8 Input Streams
From MVIP
8 Input On-Board
ST-BUS Streams
8 Output Streams
to MVIP
8 Output On-Board
ST-BUS Streams
MVIP Direction
MVIP Enable
MT8985 #1
CSTo
MT8985 #2
CSTo
MT8985
#3
MT8985
#4
FDL HDLC
MT8952B
T1/E1
MH89760B
or
MH89790B
HDLC
MT8952B
ANALOG
D-PHONE
MT8992/93
SWITCH
MT8985
SWITCH
MT8985
SWITCH
MT8985
SWITCH
MT8985
DPLL
MT8941
PC INTERFACE
MVIP HEADER
MVIP STo0-7 MVIP STi0-7
FDL HDLC
MT8952B
T1/E1
MH89760B
or
MH89790B
HDLC
MT8952B
512 Channel
Switch Matrix
Page 12
MT8985
2-56
Figure 11 - S-Access Card Functional Block Diagram
MVIP HEADER
SWITCH
MATRIX
S
INTERFACE
HDLC
DIGITAL
PHONE
DPLL
DTMF
RECEIVER
PC INTERFACE
HDLC
STi7-1 STo7-1
STi0 STo0
MT8930B
MT8941
MT8992/93
MT8870
MVIP STi1-7MVIP STo1-7
MT898 5
Page 13
MT8985
2-57
* Exceeding these values may cause perm anen t damage . Function al ope rati on under the se conditi ons is not impl ied.
‡ Typical figures are at 25°C and are for design aid only: not guarante ed and not subject to producti on testing.
‡ Typical figures are at 25°C and are for design aid only: not guarante ed and not subject to producti on testing.
Figure 12 - Output Test Load
Absolute Maximum Ratings*
Parameter Symbol Min Max Units
1V
DD
- V
SS
-0.3 7 V
2 Voltage on Digital Inputs V
I
VSS-0.3 VDD+0.3 V
3 Voltage on Digital Outputs V
O
VSS-0.3 VDD+0.3 V
4 Current at Digital Outputs I
O
40 mA
5 Storage Temperature T
S
-65 +150 °C
6 Package Power Dissipation P
D
2W
Recommended Operating Conditions - V oltages are with respect to ground (V
SS
) unless otherwise stated.
Characteristics Sym Min Typ
‡
Max Units Test Conditio ns
1 O perat ing Temperature T
OP
-40 25 +85 °C
2 P osit ive Su pply V
DD
4.75 5.0 5.25 V
3 Input Voltage V
I
0V
DD
V
DC Electrical Characteristics - V oltages are with respect to ground (V
SS
) unless otherwise stated.
Characteristics Sym Min Typ‡Max Units Test Conditio ns
1
I
N
P
U
T
S
Supply Current I
DD
10 15 mA Outputs unloaded
2 Input High Voltage V
IH
2.0 V
3 Input Low Voltage V
IL
0.8 V
4 Input Leakage (input pins)
Input Leakage (I/O pins)
I
IL
34
5
100
µAV
I
between VSS and V
DD
5 Input Pin Capacitance C
I
8pF
6
O
U
T
P
U
T
S
Output High Voltage V
OH
2.4 V IOH = 10 mA
7 Output High Current I
OH
10 15 m A Sourcing. VOH=2.4V
8 Output Low Voltage V
OL
0.4 V IOL = 5 mA
9 Output Low Current I
OL
5 10 mA Sinking . VOL = 0.4V
10 High Impedance Leakage I
OZ
5 µAVO between VSS and V
DD
11 Output Pin Capacitance C
O
8pF
Output
Pin
Test Point
C
L
V
SS
S1
R
L
V
DD
S2
V
SS
S1 is open circuit except
when testing output levels
or high impedance states.
S2 is switched to V
DD
or
V
SS
when tes ting output
levels or high impedance
states.
Page 14
MT8985
2-58
† Timing is over recommended temperature & power supply voltages (V
DD
=5V±5%, VSS=0V, TA=–40 to 85°C).
‡ Typical figures are at 25°C and are for design aid only: not guaran teed and not subje ct to production testing.
Figure 13 - ST-BUS Timing
AC Electrical Characteristics† - ST-BUS Timing
Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics Sym Min Typ
‡
Max Units Test Condition s
1 Frame P ulse widt h t
F0iW
244 ns
2 Frame P ulse setup time t
F0iS
10 190 ns
3 Frame P ulse hold time t
F0iH
20 190 ns
4 STo delay Active to Active t
DAA
45 100 ns CL=150 pF
5 STi setup time t
STiS
20 ns
6 STi hold time t
STiH
20 ns
7 Clock period
t
C4i
200 244 300 ns
8 CK Input Low t
CL
85 122 150 ns
9 CK Input High
t
CH
85 122 150 ns
10 Clock Rise/Fall Time t
r,tf
10 ns
2.0V
0.8V
STi
2.0V
0.8V
2.0V
0.8V
STo
2.0V
0.8V
F0i
t
F0iW
t
C4i
t
CH
t
CL
t
F0iS
t
DAA
t
STiS
t
STiH
t
F0iH
Ch. 31
Bit 0
Ch. 0
Bit 7
Ch. 0
Bit 6
Ch. 31
Bit 0
Ch. 0
Bit 7
Ch. 0
Bit 6
Ch. 0
Bit 5
Ch. 0
Bit 5
C4i
t
f
t
r
Page 15
MT8985
2-59
† Timing is over recommended temperature & power supply voltages (V
DD
=5V±5%, VSS=0V, TA=–40 to 85°C).
‡ Typical figures are at 25°C and are for design aid only: not guarante ed and not subject to producti on testing.
Figure 14 - GCI Timing
AC Electrical Characteristics† - GCI Timing
Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics Sym Min Typ
‡
Max Units Test Conditions
1 Clock Period t
C4i
150 2 44 300 ns
2 Pulse Width t
CL
, t
CH
73 122 150 ns
3 Frame Width High t
WFH
244 ns
4 Frame Setup t
F0iS
10 190 ns
5 Frame Hold t
F0iH
20 190 ns
6 Data Dela y/Clock Act ive to
Active
t
DAA
45 100 ns CL=150 pF
7 Serial Input Setup t
STiS
20 ns
8 Serial Input Hold t
STiH
20 ns
9 Clock Rise/ Fall Time t
r,tf
10 ns
2.0V
0.8V
ST o
2.0V
0.8V
C4i
2.0V
0.8V
F0i
C4i
F0i
STi/
STo
bit 0 bit 1 bit 2 bit 3
See Detail a
Detail a
Note: bit 0 identifies the first bit of the GCI frame
t
CL
t
CH
t
C4i
t
DAA
t
WFH
t
F0iS
t
F0iH
t
STiS
t
STiH
2.0V
0.8V
STi
t
f
t
r
Page 16
MT8985
2-60
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to producti on testing.
* High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge CL.
AC Electrical Characteristics† - Serial Streams for ST-BUS and GCI Backplanes
Characteristics Sym Min Typ‡Max Units Test Conditio ns
1
O
U
T
P
U
T
S
STo0/7 Delay - Active to High Z t
SAZ
100 ns RL=1 KΩ*, CL=150 pF
2 STo0/7 Delay - High Z to Active t
SZA
100 ns CL=150 pF
3 Output Driver Enable Delay t
OED
65 ns RL=1 KΩ*, CL=150 pF
4 CSTo Output Delay t
XCD
060nsC
L
=150 pF
Figure 15 - Serial Outputs and External Control
C4i
2.0V
0.8V
STo0
to
STo7
2.4V
0.4V
STo0
to
STo7
2.4V
0.4V
CSTo
2.4V
0.4V
Bit Cell Boundary
(GCI)
(ST-BUS)
*
t
SAZ
t
SZA
t
XCD
*
Figure 16 - Output Driver Enable
ODE
STo0
to
STo7
2.0V
0.8V
2.4V
0.4V
t
OED
*
*
t
OED
Page 17
MT8985
2-61
† Timing is over recommended temperature & power supply voltages .
‡ Typical figures are at 25°C and are for design aid only: not guarante ed and not subject to producti on testing.
* High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge CL.
Figure 17 - Motorola Non-Multiplexed Bus Timing
AC Electrical Characteristics†- Microprocessor Bus
Voltages are with respect to ground (VSS) unless otherwise stated .
Characteristics Sym Min Typ
‡
Max Units Test Conditions
1CS
Setup from DS rising t
CSS
0ns
2R/W
Setup from DS rising t
RWS
30 ns
3 Add setup from DS rising t
ADS
5ns
4CS
hold after DS falling t
CSH
0ns
5R/W
hold after DS falling t
RWH
5ns
6 Add hold after DS fal ling t
ADH
5ns
7 Data setup from DTA
Low on Read t
DDR
10 ns CL=150 pF
8 Data hold on read
t
DHR
10 50 90 ns RL=1 KΩ*,
C
L
=150 pF
9 Data setup on write (fast write) t
DSW
20 ns
10 Valid Data Delay on write
(slow write)
t
SWD
122 ns
11 Da ta hold on write t
DHW
8ns
12 Acknowledgement Delay:
Reading Data Memo ry
Reading/Writing Conn. Memo ry
Writing to Control Register
Reading Control Register
t
AKD
560
300/370
47
70
1220
730/800
95
155
ns
ns
ns
ns
C
L
=150 pF
13 Acknowledgement Hold Time t
AKH
10 60 110 ns RL=1 KΩ*,
C
L
=150 pF
CS
R/W
A0-A6
D0-D7
READ
D0-D7
WRITE
DTA
t
CSS
t
RWS
t
ADS
t
CSH
t
RWH
t
ADH
t
SWD
t
DSW
t
DHR
VALID DATA
t
DDR
t
DHW
t
AKH
t
AKD
VALID DATA
2.0V
0.8V
2.0V
0.8V
2.0V
0.8V
2.0V
0.8V
2.0V
0.8V
2.0V
0.8V
2.0V
0.8V
DS
Page 18
MT8985
2-62
Notes:
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