Datasheet MT8816AC, MT8816AE, MT8816AP Datasheet (MITEL)

ISO-CMOS



8 x 16 Analog Switch Array

MT8816

Features

• Internal cont rol lat ches and add ress d eco der

• Short set-up and hold times

• Wide ope rating v oltag e: 4. 5V to 13.2V

• 12Vpp anal og s ignal capabi lity

•R

• ∆R

65Ω max. @ VDD=12V, 25°C

ON

≤10Ω @ VDD=12V, 25°C

ON

• Full CMOS switch for low distortion

• Minimum f eedthr oug h and c ros stal k

• Separate ana lo g and di gital re ferenc e supp lies

• Low power consumption ISO-CMOS technology

Applications

• Key systems

• PBX systems

• Mobile rad io

• Test e quipme nt/ instr umen tatio n

• Analo g/ di gita l m ult ip le xers

• Audio/Video switching

ISSUE 2 November 1988

Ordering Information

MT8816AC 40 Pin Ce r am i c D IP
MT8816AE 40 Pin Pla stic D IP
MT8816AP 44 Pin PL C C

-40° to 85°C

Description

The Mitel MT8816 is fabricated in MITEL’s ISO­CMOS technology providing low power dissipation
and high reliability. The device contains a 8 x 16
array of crosspoint switches along with a 7 to 128
line decoder and latch circuits. Any one of the 128
switches can be addressed by selecting the
appropriate seven address bits. The selected switch
can be turned on or off by applying a logical one or
zero to the DATA in p ut . V
of the digital inputs. The range of the analog signal
is from V

to VEE. Chip Select (CS) allows the

DD

crosspoint array to be cascaded for matrix
expansion.

is the ground refer-ence

SS

AX0

AX1
AX2
AX3

AY0

AY1

AY2

CS STROBE DATA RESET VDD VEE VSS

11

8 x 16

7 to 128

Decoder

Latches

Switch

Array

128128

• • • • • • • • • • • • • • • • • • •

Yi I/O (i=0-7)

Figure 1 - Functional Block Diagram

• • • • • • • • • • • • • • • •

Xi I/O
(i=0-15)

3-45

MT8816 ISO-CMOS

1

Y3

AY2

RESET

AX3
AX0

VSS

STROBE

VEE

2
3
4

5
6

X14

7

X15

8

X6

9

X7

10

X8

11

X9

12

X10

13

X11

14

NC

15

Y7

16
17

Y6

18
19

Y5

20

40 PIN CERDIP/PLASTIC DIP 44 PIN PLCC

40
39

38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

VDD
Y2
DATA
Y1
CS
Y0
NC
X0
X1
X2
X3
X4
X5
X12
X13
AY1
AY0
AX2
AX1
Y4

X14
X15

X6
X7

X8

X9
X10
X11

NC
NC

Y7

DATA

Y2

VDD

Y3

AY2

RESET

AX3

AX0

NC

65432 44434241
7
8
9
10
11
12
13
14
15
16

17

Y6

VSS

1

231819202122 242526 2728

Y5

VEE

STROBE

Y4

AX1

AX2

AY0

Y1

40

39
38
37
36
35
34
33
32
31
30
29

AY1

CS

NC

Figure 2 - Pin Connections

Pin Description

Pin #* Name Description

1Y3Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array.

Y0
NC
X0
X1
X2
X3
X4
X5
X12
X13
NC

2AY2Y2 Add ress Lin e (Inp ut).
3 RESET Master RESET (Input): this is used to turn off all switches regardless of the condition of

CS. Active High.
4,5 AX3,AX0 X3 and X0 Address Lines (Inputs).
6,7 X14, X15 X14 and X15 Analog (Inputs/Outputs): these are connected to the X14 and X15 rows of

the switch array.

8-13 X6-X11 X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch

array.

14 NC No Connection
15 Y7 Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array.
16 V

Digital Ground Reference.

SS

17 Y6 Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array.
18 STROB E STROBE (Input): enables function selected by address and data. Address must be stable

before STRO BE goes high and DATA must be stable on the falling edge of the STROBE .

Active High.

19 Y5 Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array.
20 V

Negative Power Supply.

EE

21 Y4 Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array.
22, 23 AX1,AX2 X1 and X2 Address Lines (Inputs).
24, 25 AY0,AY1 Y0 and Y1 Address Lines (Inputs).

* Plastic DIP and CERDIP only

3-46

ISO-CMOS MT8816

Pin Description (continued)

Pin #* Name Description

26, 27 X13, X12 X13 and X12 Analog (Inputs/Outputs): these are connected to the X13 and X12 rows of

the switch array.

28 - 33 X5-X0 X5-X 0 Analog (Inp uts/Ou tp uts): these are connected to the X5-X0 rows of the switch

array.
34 NC No Connection.
35 Y0 Y0 Analog (Input/Output): this is connected to the Y0 column of the switch array.
36 CS Chip Select (Input): this is used to select the device. Active High.
37 Y1 Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array.
38 DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off

the selected switch. Active High.
39 Y2 Y2 Analog (Input/Output): this is connected to the Y2 column of the switch array.
40 V

* Plastic DIP and CERDIP only

Positive Pow er Supp ly.

DD

Functional Description

The MT8816 is an analog switch matrix with an array
size of 8 x 16. The switch array is arranged such that
there are 8 columns by 16 rows. The columns are
referred to as the Y inputs/outputs and the rows are
the X inputs/outputs. The crosspoint analog switch
array will i n te r co n ne c t a n y X I/O with a n y Y I/O whe n
turned on and provide a high degree of isolation
when turned off. The control memory consists of a
128 bit write only RAM in which the bits are selected
by the address inputs (AY0-AY2, AX0-AX3). Data is
presente d to th e me m o ry o n th e DATA input. Da ta is
asynchronously written into memory whenever both
the CS (Chip Select) and STROBE inputs are high
and are latched on the falling edge of STROBE. A
logical “1” written into a memory cell turns the
corresponding crosspoint switch on and a logical “0”
turns the crosspoint off. Only the crosspoint switches
corresponding to the addressed memory location are
altered when data is written into memory. The
remaining switches retain their previous s tates. Any
combination of X and Y inputs/outputs can be
interconnected by establishing appropriate patterns
in the control memory. A logical “1” on the RESET
input will asynchronously return all memory locations
to logical “0” turning off all crosspoint
switches regardless of whether CS is high or low.
Two voltage reference pins (V
provided for the MT8816 to enable switching of
negative analog signals. The range for digital
signals is from V
signals is from V
tied together if a single voltage reference is needed.

to VSS while the range for analog

DD

to VEE. VSS and VEE pins can be

DD

and VEE) are

SS

Address Decode

The seven address inputs along with the STROBE
and CS (Chip Select) are logically ANDed to form an
enable signal for the resettable transparent latches.
The DATA input is buffered and is used as the input
to all latches. To write to a location, RESET must be
low and CS must go high while the address and data
are set up. Then the STROBE input is set high and
then low causing the data to be latched. The data
can be changed while STROBE is high, however, the
corresponding switch will turn on and off in
accordance with the DATA input. DATA must be
stable on the falling edge of STROBE in order for
correct data to be written to the latch.

3-47

MT8816 ISO-CMOS

Absolute Maximum Ratings*- Voltages are with respect to V

unless otherwise stated.

EE

Paramete r Symbol Min Max Units

1 Supply Voltage V

2 Analog Input Voltage V
3 Digital Input Voltage V

DD

V

SS

INA

IN

-0.3

-0.3

V

16.0

DD

+0.3

-0.3 VDD+0.3 V

VSS-0.3 VDD+0.3 V
4 Current on any I/O Pin I ±15 mA
5 Storage Tem perature T
6 Package Power Dissipation PLASTIC DIP

CERDIP

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Recommended Operating Conditions - Voltages are with respect to V

S

P

D

P

D

EE

-65 +150 °C

0.6

1.0

unless otherwise stated.

Characteris tics Sym Min Typ Max Units Test Conditions

1 Operating Temperature T
2 Supply Voltage V

3 Analog In put Voltage V
4 Digital In put Voltage V

DC Electrical Characteristics

†

Characteristics Sym Min Typ

DD

V

SS

INA

- Voltages are with resp e ct to V

-40 25 85 °C

O

4.5

V

EE

V

EE

V

IN

SS

V

EE=VSS

‡

13.2

DD

V

DD

V

DD

-4.5

=0V, V

V
V

V
V

=12V unless otherwise stated.

DD

Max Units Test Conditio ns

V
V

W
W

1 Quiescent Supply Current I

DD

1100µA All digital inputs at VIN=VSS or

V

DD

0.4 1.5 mA All digital inputs at VIN=2.4V +
V

; VSS=7.0V

SS

5 15 mA All digi tal in p uts at V

2 Off-state Leakage Current

I

OFF

(See G.9 in Appendix)
3 Input Logic “0” level V
4 Input Logic “1” level V
5 Input Logic “1” level V
6 Input Leakage (digital pins) I

† DC Electrical Characteristics are over recommended temperature range.
‡ Typical figures are at 25°C and are for design aid only; not guaran teed and no t subject to producti on testing .

IL
IH
IH

LEAK

2.0+V

3.3 V

DC Electrical Characteristics- Switch Resistance - V

±1 ± 500 nA IVXi - VYjI = VDD - V

See Appendix, Fig. A.1

SS

0.8+V

SS

VVSS=7.5V; VEE=0V
VVSS=6.5V; VEE=0V

0.1 10 µA All digi tal in p uts at VIN = VSS
or V

DD

is the external DC offset applied at the analog I/O pins.

DC

Characteristics Sym 25°C 70°C 85°C Units Test Conditions

Typ Max Typ Max Typ Max

1 On-state V

Resistance V

=12V

DD

=10V

DD

V

= 5V

DD

R

ON

45
55

120

65
75

185

75
85

215

80
90

225

Ω

VSS=VEE=0V , VDC=VDD/2,

Ω

IV
See Appendix, Fig. A.2

Ω

(See G.1, G.2, G.3 in
Appendix)

2 Difference in on-state

resistance between two
switches
(See G.4 in Appendix)

∆R

510 10 10 ΩVDD=12V, VSS=VEE=0,

ON

V
IV
See Appendix, Fig. A.2

I = 0.4V

Xi-VYj

DC=VDD

I = 0.4V

Xi-VYj

/2,

IN

EE

=3.4V

3-48

ISO-CMOS MT8816

AC Electrical Characteristics† - Crosspoint Performance-Voltages are with respect to V

=-7V , unless otherwise stated.

V

EE

DD

Characteristics Sym Min Typ‡Max Units Test Co nditions

1 Switch I/O Capacitance C
2 Feedthrough Capacitance C
3 Frequency Response

F
Channel “ON”
20LOG(V

OUT/VXi

4 Total Harmonic Distortion

)=-3dB

THD 0.01 % Switch is “ON”; V
(See G.5, G.6 in Appendix)

5 Feedthrough

FDT -95 dB All Switches “OFF”; V
Channel “OFF”
Feed.=20LOG (V

OUT/VXi

)

(See G.8 in Appendix)

6 Crosstalk between any two

X
channels for switches Xi-Yi and
Xj-Yj .

Xtalk=20LOG (V

Yj/VXi

).

(See G.7 in Appendix).

S
F

3dB

talk

20 pF f=1 MHz

0.2 pF f=1 MHz
45 MHz Switch is “ON”; V

sinewave; R

= 1kΩ

L

See Appendix, Fig. A.3

sinewave f= 1k Hz; R

2Vpp sinewave f= 1kHz;
R

= 1kΩ.

L

See Appendix, Fig. A.4

-45 dB V

-90 dB V

-85 dB V

-80 dB V

=2Vpp sinewave

INA

f= 10MHz; R

=2Vpp sinewave

INA

f= 10kHz; R

=2Vpp sinewave

INA

f= 10kHz; R

=2Vpp sinewave

INA

f= 1kHz; R

L

= 75Ω.

L

= 600Ω.

L

= 1kΩ.

L

= 10kΩ.
Refer to Appendix, Fig. A.5
for test circuit.

7 Propagation delay thro ugh

t

PS

30 ns RL=1kΩ; CL=50pF

switc h

† Timing is over recommended temp era tu re range . See Fig. 3 for control and I/O timing details.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to producti on testin g.
Crosstal k m ea su r em e nts a re fo r Pl as tic D I PS o nl y, cross tal k va lu es f or PLCC pa ckag es are ap proximately 5d B better.

AC Electrical Characteristics† - Control and I/O Timings- Voltages are with respect to V

V

=-7V , unless otherwise stated.

EE

DD

Characteristics Sym Min Typ‡Max Units Test Conditions

=5V, VSS=0V,

= 2Vpp

INA

= 2Vpp

INA

=1kΩ

L

=

INA

=5V, VSS=0V,

1 Control Input crosstalk to switch

CX

talk

(for CS, DATA, STROBE,

Address)
2 Digit al Input Capa citan ce C
3 Switching Frequency F
4 Se tup Time DATA to STRO BE t
5 Hold Time DATA to STROBE t
6 Setup Time Address to STROBE t
7 Hold Time Address to STROBE t
8 Se tup Time CS to S TRO BE t
9 Hold Time CS to STROBE t

10 STROBE Pulse Width t
11 RESET Pulse Widt h t
12 STROBE to Switch Status Delay t
13 DATA to Switch Status Delay t
14 RESET to Swit ch Status Delay t

† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Inp ut ris e tim e (t r) an d fall tim e ( tf) = 5 ns .

‡ Typical figures are at 25°C and are for design aid only; not guaran teed and no t subject to producti on testing .

DI

O
DS
DH
AS
AH

CSS

CSH
SPW
RPW

S
D
R

10 ns RL= 1kΩ, CL=50pF
10 ns RL= 1kΩ, CL=50pF
10 ns RL= 1kΩ, CL=50pF
10 ns RL= 1kΩ, CL=50pF
10 ns RL= 1kΩ, CL=50pF
10 ns RL= 1kΩ, CL=50pF
20 ns RL= 1kΩ, CL=50pF
40 ns RL= 1kΩ, CL=50pF

30 mVpp VIN=3V squarewave;

R

IN

See Appendix, Fig. A.6

10 pF f=1M Hz

20 MHz

40 100 ns RL= 1kΩ, CL=50pF
50 100 ns RL= 1kΩ, CL=50pF
35 100 ns RL= 1kΩ, CL=50pF

➀ Refe r to Ap pe nd ix , Fig. A .7 for te st ci r cuit.

=1kΩ, RL=10kΩ.

➀
➀
➀
➀
➀
➀
➀
➀
➀
➀
➀

3-49

MT8816 ISO-CMOS

t

CSS

50%

CS

RESET

STROBE

ADDRESS

DATA

SWITCH*

ON

t

AS

50% 50%

t

SPW

50% 50% 50%

50%

t

DS

OFF

Figure 3 - Control Memory Timing Diagram

* Se e Append ix, Fig. A.7 for switching wavef orm

t

CSH

50%

t

RPW

50% 50%

t

AH

50%

t

DH

t

D

t

S

t

R

t

R

AX0 AX1 AX 2 AX3 AY0 AY1 AY2 Connection*

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1

↓

1
0

↓

0
1

↓

1
0

↓

0
1

↓

1
0

↓

0
1

↓

1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0

↓

0
1

↓

1
1

↓

1
0

↓

0
0

↓

0
1

↓

1
1

↓

1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0

↓

0
0

↓

0
0

↓

0
1

↓

1
1

↓

1
1

↓

1
1

↓

1

Table 1. Address Decode Truth Table

* Swi tch conn ecti ons are not in ascending order

X0-Y0
X1-Y0
X2-Y0
X3-Y0
X4-Y0

X5-Y0
X12-Y0
X13-Y0

X6-Y0

X7-Y0

X8-Y0

X9-Y0
X10-Y0
X11-Y0
X14-Y0
X15-Y0

X0-Y1

↓ ↓

X15-Y1

X0-Y2

↓ ↓

X15-Y2

X0-Y3

↓ ↓

X15-Y3

X0-Y4

↓ ↓

X15-Y4

X0-Y5

↓ ↓

X15-Y5

X0-Y6

↓ ↓

X15-Y6

X0-Y7

↓ ↓

X15-Y7

3-50