Datasheet MT8815AC, MT8815AP, MT8815AE Datasheet (MITEL)

ISO-CMOS



MT8815

8 x 12 Analog Switch Array

Features

• Internal cont rol lat ches and add ress d eco der

• Short set-up and hold times

• Wide ope rating v oltag e: 4. 5V to 13.2V

• 12Vpp anal og s ignal capabi lity

•R

• ∆R

65Ω max. @ VDD=12V, 25°C

ON

≤ 10Ω @ VDD=12V, 25°C

ON

• Full CMOS switch for low distortion

• Minimum f eedthr oug h and c ros stal k

• Separate ana lo g and di gital re ferenc e supp lies

• Low power consumption ISO-CMOS technology

Applications

• Key systems

• PBX systems

• Mobile rad io

• Test equipment /instru men tatio n

• Analo g/ di gita l m ult ip le xers

• Audio/Video switching

ISSUE 1 November 1988

Ordering Information

MT8815AC 40 Pin Ce r am i c D IP
MT8815AE 40 Pin Pla stic D IP
MT8815AP 44 Pin PL C C

-40° to 85°C

Description

The Mitel MT8815 is fabricated in MITEL’s ISO­CMOS technology providing low power dissipation
and high reliability. The device contains a 8 x 12
array of crosspoint switches along with a 7 to 96 line
decoder and latch circuits. Any one of the 96
switches can be addressed by selecting the
appropriate seven address bits. The selected switch
can be turned on or off by applying a logical one or
zero to the DATA input. V
of the digital inputs. The range of the analog signal
is from V

to VEE.

DD

is the ground reference

SS

AX0

AX1
AX2
AX3

AY0

AY1

AY2

STROBE DATA RESET VDD VEE VSS

11

8 x 12

7 to 96

Decoder

Latches

Switch

Array

9696

• • • • • • • • • • • • • • • • • • •

Yi I/O (i=0-7)

Figure 1 - Functional Block Diagram

• • • • • • • • • • • • • • • •

Xi I/O
(i=0-11)

3-39

3-39

MT8815 ISO-CMOS

1

Y3

AY2

RESET

AX3
AX0

VSS

STROBE

VEE

2
3
4

5
6

NC

7

NC

8

X6

9

X7

10

X8

11

X9

12

X10

13

X11

14

NC

15

Y7

16
17

Y6

18
19

Y5

20

40 PIN CERDIP/PLASTIC DIP 44 PIN PLCC

40
39

38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

NC
Y2
DATA
Y1
VDD
Y0
NC
X0
X1
X2
X3
X4
X5
NC
NC
AY1
AY0
AX2
AX1
Y4

NC
NC

X6
X7

X8

X9
X10
X11

NC
NC

Y7

DATA

Y2

NC

Y3

AY2

RESET

AX3

AX0

NC

65432 44434241
7
8
9
10
11
12
13
14
15
16

17

Y6

VSS

1

231819202122 242526 2728

Y5

VEE

STROBE

Y4

AX1

AX2

AY0

Y1

40

39
38
37
36
35
34
33
32
31
30
29

AY1

VDD

Y0
NC
X0
X1
X2
X3
X4
X5
NC
NC
NC

NC

Figure 2 - Pin Connections

Pin Description

Pin #* Name Description

1Y3Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array.
2AY2Y2 Add ress Lin e (Inp ut).

3 RESET Master RESET (Input): this is used to turn off all switches. Active High.
4,5 AX3,AX0 X3 and X0 Address Lines (Inputs): these are used to select X3 and X0 rows of switches.
6,7 NC No Connection.

8-13 X6-X11 X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch

array.
14 NC No Connection
15 Y7 Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array.
16 V
17 Y6 Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array.
18 STROB E STROBE (Input): enables function selected by address and data. Address must be stable

19 Y5 Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array.
20 V
21 Y4 Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array.

22, 23 AX1,AX2 X1 and X2 Address Lines (Inputs).
24, 25 AY0,AY1 Y0 and Y1 Address Lines (Inputs).
26, 27 NC No Connection.

28 - 33 X5-X0 X5-X 0 Analog (Inp uts/Ou tp uts): these are connected to the X5-X0 rows of the switch

34 NC No Connection.
35 Y0 Y0 Anal og (Input/Ou tpu t): this is connected to the Y0 column of the switch array.
36 V
37 Y1 Y1 Anal og (Input/Ou tpu t): this is connected to the Y1 column of the switch array.
38 DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off

39 Y2 Y2 Anal og (Input/Ou tpu t): this is connected to the Y2 column of the switch array.
40 NC No Connection.

* Plastic DIP and CERDIP only.

Digital Ground Reference (Input).

SS

before STRO BE goes high and DATA must be stable on the falling edge of the STROBE .

Active High.

Negative Power Supply.

EE

array.

Positive Po wer Supply.

DD

the selected switch. Active High.

3-40

ISO-CMOS MT8815

Functional Description

The MT8815 is an analog switch matrix with an array
size of 8×12. The switch array is arranged such that
there are 8 columns by 12 rows. The columns are
referred to as the Y inputs/outputs and the rows are
the X inputs/outputs. The crosspoint analog switch
array will i n te r co n ne c t a n y X I/O with an y Y I/O when
turned on and provide a high degree of isolation
when turned off. The control memory consists of a 96
bit write only RAM in which the bits are selected by
the address inputs (AY0-AY2, AX0-AX3). Data is
presente d to th e me m o ry o n th e DATA input. Da ta is
asynchronously written into memory whenever the
STROBE input is high and is latched on the falling
edge of STROBE. A logical “1” written into a
memory cell turns the corresponding crosspoint
switch on and a logical “0” turns the crosspoint off.
Only the crosspoint switches corresponding to the
addressed memory location are altered when data is
written into memory. The remaining switches retain
their previous states. Any combination of X and Y
inputs/outputs can be interconnected by establishing
appropriate patterns in the control memory. A logical
“1” on the RESET input will asynchronously return all
memory locations to logical “0” turning off all
crosspoint switches. Two voltage reference pins
(V

and VEE) are provided for the MT8815 to

SS

enable switching of negative analog signals. The
range for digital signals is from V
range for analog signals is from V
and V

pins can be tied together if a single voltage

EE

reference is needed.

to VSS while the

DD

to VEE. V

DD

SS

Address Decode

The seven address inputs along with the STROBE
are logically ANDed to form an enable signal for the
resettable transparent latches. The DATA input is
buffered and is used as the input to all latches. To
write to a location, RESET must be low while the
address and data are set up. Then the STROBE
input is set high and then low causing the data to be
latched. The data can be changed while STROBE is
high, however, the corresponding switch will turn on
and off in accordance with the DATA input. DATA
must be stable on the falling edge of STROBE in
order for corr e ct da ta to be writte n t o th e l atc h .

3-41

MT8815 ISO-CMOS

Absolute Maximum Ratings *- Voltages are with respect to V

unless otherwise stated.

EE

Paramete r Symbol Min Max Units

1 Supply Voltage V

2 Analog Input Voltage V
3 Digital Input Voltage V

DD

V

SS

INA

IN

-0.3

-0.3

V

15.0

DD

+0.3

-0.3 VDD+0.3 V

VSS-0.3 VDD+0.3 V
4 Current on any I/O Pin I ±15 mA
5 Storage Tem peratu re T
6 Package Power Dissipation PLASTIC DIP

CERDIP

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Recommended Operating Conditions - Voltages are with respect to V

S

P

D

P

D

EE

-65 +150 °C

0.6

1.0

unless otherwise stated.

Characteris tics Sym Min Typ Max Units Test Conditions

1 Operating Temperature T
2 Supply Voltage V

3 Analog In put Voltage V
4 Digital In put Voltage V

DC Electrical Characteristics

†

Characteristics Sym Min Typ

DD

V

SS

INA

- Vo lt ag es are with respect to V

-40 25 85 °C

O

4.5

V

EE

V

EE

V

IN

SS

V

EE=VSS

‡

13.2

DD

V

DD

V

DD

-4.5

=0V, V

V
V

V
V

=12V unless otherwi se stated .

DD

Max Units Test Conditio ns

V
V

W
W

1 Quiescent Supply Current I

DD

1100µA All digital inputs at VIN=VSS or

V

DD

0.4 1.5 mA All digital inputs at VIN=2.4V +
V

; VSS=7.0V

SS

5 15 mA All digi tal in p uts at V

2 Off-state Leakage Current

I

OFF

(See G.9 in Appendix)
3 Input Logic “0” level V
4 Input Logic “1” level V
5 Input Logic “1” level V
6 Input Leakage (digital pins) I

† DC Electrical Characteristics are over recommended temperature range.
‡ Typical figures are at 25°C and are for design aid only; not guaran teed and no t subject to producti on testing .

IL
IH
IH

LEAK

2.0+V

3.3 V

DC Electrical Characteristics- Switch Resistance - V

±1 ± 500 nA IVXi - VYjI = VDD - V

See Appendix, Fig. A.1

SS

0.8+V

SS

VVSS=7.5V; VEE=0V
VVSS=6.5V; VEE=0V

0.1 10 µA All digital in p uts at VIN = VSS
or V

DD

is the external DC offset applied at the analog I/O pins.

DC

Characteristics Sym 25°C 70°C 85°C Units Test Conditions

Typ Max Typ Max Typ Max

1 On-state V

Resistance V

=12V

DD

=10V

DD

V

= 5V

DD

R

ON

45
55

120

65
75

185

75
85

215

80
90

225

Ω

VSS=VEE=0V , VDC=VDD/2,

Ω

IV
See Appendix, Fig. A.2

Ω

(See G.1, G.2, G.3 in
Appendix)

2 Difference in on-state

resistance between two
switches
(See G.4 in Appendix)

∆R

510 10 10 ΩVDD=12V, VSS=VEE=0,

ON

V
IV
See Appendix, Fig. A.2

I = 0.4V

Xi-VYj

DC=VDD

I = 0.4V

Xi-VYj

/2,

IN

EE

=3.4V

3-42

ISO-CMOS MT8815

AC Electrical Characteristics† - Crosspoint Performance-Voltages are with respect to V

=-7V, unless otherwise stated.

V

EE

DD

Characteristics Sym Min Typ‡Max Units Test Conditions

1 Switch I/O Capacitance C
2 Feedthrough Capacitance C
3 Frequency Response

F
Channel “ON”
20LOG(V

OUT/VXi

4 Total Harmonic Distortion

)=-3dB

THD 0.01 % Switch is “ON”; V
(See G.5, G.6 in Appendix)

5 Feedthrough

FDT -95 dB All Switches “OFF”; V
Channel “OFF”
Feed.=20LOG (V

OUT/VXi

)

(See G.8 in Appendix)

6 Crosstalk between any two

X
channels for switches Xi-Yi and
Xj-Yj .

Xtalk=20LOG (V

Yj/VXi

).

(See G.7 in Appendix).

S
F

3dB

talk

20 pF f=1 MHz

0.2 pF f=1 MHz
45 MHz Switch is “ON”; V

sinewave; R

= 1kΩ

L

See Appendix, Fig. A.3

sinewave f= 1k Hz; R

2Vpp sinewave f= 1kHz;

= 1kΩ.

R

L

See Appendix, Fig. A.4

-45 dB V

-90 dB V

-85 dB V

-80 dB V

=2Vpp sinewave

INA

f= 10MHz; R

=2Vpp sinewave

INA

f= 10kHz; R

=2Vpp sinewave

INA

f= 10kHz; R

=2Vpp sinewave

INA

f= 1kHz; R

L

= 75Ω.

L

= 600Ω.

L

= 1kΩ.

L

= 10kΩ.
Refer to Appendix, Fig. A.5
for test circuit.

7 Propagation delay thro ugh

t

PS

30 ns RL=1kΩ; CL=50pF

switc h

† Timing is over recommended temp era tu re range . See Fig. 3 for control and I/O timing details.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to producti on testin g.
Crosstal k m ea su r em e nts a re fo r Pl as tic D I PS o nl y, cross tal k va lu es f or PLCC pa ckag e s a re approxim ately 5dB b etter.

AC Electrical Characteristics† - Control and I/O Timings- Voltages are with respect to V

V

=-7V , unless otherwise stated.

EE

DD

Characteristics Sym Min Typ‡Max Units Test Conditions

=5V, VSS=0V,

= 2Vpp

INA

= 2Vpp

INA

=1kΩ

L

=

INA

=5V, VSS=0V,

1 Control Input crosstalk to switch

(for DATA, STROBE, Address)

CX

talk

30 mVpp VIN=3V squarewave;

R

IN

See Appendix, Fig. A.6
2 Digit al Input Capa citan ce C
3 Switching Frequency F
4 Se tup Time DATA to STRO BE t
5 Hold Time DATA to STROBE t
6 Setup Time Address to STROBE t
7 Hold Time Address to STROBE t
8 STROBE Pulse Width t
9 RES E T Pulse Widt h t

10 STROBE to Switch Status Delay t
11 DATA to Switch Status Delay t
12 RESET to Switch Status Delay t

† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Inp ut ris e tim e (t r) an d fall time (tf) = 5 ns .
‡ Typical figures are at 25°C and are for design aid only; not guaran teed and no t subject to producti on testing .

➀

Refer to Ap pe nd ix , Fig. A.7 for tes t ci rcu it .

DI

O
DS
DH
AS
AH

SPW
RPW

S
D
R

10 ns RL= 1kΩ, CL=50pF
10 ns RL= 1kΩ, CL=50pF
10 ns RL= 1kΩ, CL=50pF
10 ns RL= 1kΩ, CL=50pF
20 ns RL= 1kΩ, CL=50pF
40 ns RL= 1kΩ, CL=50pF

10 pF f=1MHz

20 MHz

40 100 ns RL= 1kΩ, CL=50pF
50 100 ns RL= 1kΩ, CL=50pF
35 100 ns RL= 1kΩ, CL=50pF

=1kΩ, RL=10kΩ.

➀
➀
➀
➀
➀
➀
➀
➀
➀

3-43

MT8815 ISO-CMOS

t

RPW

50%

t

S

50%

t

R

RESET

STROBE

ADDRESS

DATA

SWITCH*

ON

OFF

t

AS

50%

50%

t

SPW

50%

t

DS

50%

50%

t

AH

50%

t

DH

t

D

Figure 3 - Control Memory Timing Diagram

* See Appe ndix, Fig. A.7 for switching wavef orm

AX0 AX1 AX2 AX3 AY0 A Y1 A Y2 Connection

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1

➀

This address has no effect on device status.

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0

↓

0
0

↓

0
0

↓

0
0

↓

0
0

↓

0
0

↓

0
0

↓

0

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1

↓

1
0

↓

0
1

↓

1
0

↓

0
1

↓

1
0

↓

0
1

↓

1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0

↓

0
1

↓

1
1

↓

1
0

↓

0
0

↓

0
1

↓

1
1

↓

1

Table 1. Address Decode Truth Table

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0

↓

0
0

↓

0
0

↓

0
1

↓

1
1

↓

1
1

↓

1
1

↓

1

No Connection
No Connection

No Connection
No Connection

X0-Y0
X1-Y0
X2-Y0
X3-Y0
X4-Y0
X5-Y0

X6-Y0
X7-Y0
X8-Y0

X9-Y0
X10-Y0
X11-Y0

X0-Y1

↓ ↓

X11-Y1

X0-Y2

↓ ↓

X11-Y2

X0-Y3

↓ ↓

X11-Y3

X0-Y4

↓ ↓

X11-Y4

X0-Y5

↓ ↓

X11-Y5

X0-Y6

↓ ↓

X11-Y6

X0-Y7

↓ ↓

X11-Y7

50%

t

R

➀
➀

➀
➀

3-44