Datasheet MT8812AP, MT8812AC, MT8812AE Datasheet (MITEL)



ISO-CMOS

MT8812

8 x 12 Analog Switch Array

Features

• Internal cont rol lat ches and add ress d eco der

• Short set-up and hold times

• Wide ope rating v oltag e: 4. 5V to 14.5V

• 14Vpp anal og s ignal capabi lity

•R

• ∆R

65Ω max. @ VDD=14V, 25°C

ON

≤10Ω @ VDD=14V, 25°C

ON

• Full CMOS switch for low distortion

• Minimum f eedthr oug h and c ros stal k

• Low power consumption ISO-CMOS technology

Applications

• PBX systems

• Mobile rad io

• Test e quipme nt / instru men tatio n

• Analo g/ di gita l m ult ip le xers

• Audio/Video switching

ISSUE 5 November 1988

Ordering Information

MT8812AC 40 Pin Ce r am i c D IP
MT8812AE 40 Pin Pla stic D IP
MT8812AP 44 Pin PL C C

0° to 70°C

Description

The Mitel MT8812 is fabricated in MITEL’s ISO­CMOS technology providing low power dissipation
and high reliability. The device contains a 8 x12 array
of crosspoint switches along with a 7 to 96 line
decoder and latch circuits. Any one of the 96
switches can be addressed by selecting the
appropriate seven input bits. The selected switch
can be turned on or off by applying a logical one or
zero to the DATA inpu t.

AX0
AX1
AX2

AX3

AY0
AY1
AY2

STROBE DATA RESET VDD VSS

11

8 x 12

7 to 96

Decoder

Latches

Switch

Array

9696

• • • • • • • • • • • • • • • • • • •

Yi I/O (i=0-7)

Figure 1 - Functional Block Diagram

• • • • • • • • • • • • • • • •

Xi I/O
(i=0-11)

3-27

MT8812 ISO-CMOS

1

Y3

AY2

RESET

AX3
AX0

STROBE

VSS

2
3
4

5
6

NC

7

NC

8

X6

9

X7

10

X8

11

X9

12

X10

13

X11

14

NC

15

Y7

16

NC

17

Y6

18
19

Y5

20

40 PIN CERDIP/PLASTIC DIP 44 PIN PLCC

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

VDD
Y2
DATA
Y1
NC
Y0
NC
X0
X1
X2
X3
X4
X5
NC
NC
AY1
AY0
AX2
AX1
Y4

NC
NC

X6
X7

X8

X9
X10
X11

NC
NC
NC

DATA

Y2

VDD

Y3

AY2

RESET

AX3

AX0

NC

65432 44434241
7
8
9
10
11
12
13
14
15
16

17

Y7

Y6

1

231819202122 2425 262728

Y5

VSS

STROBE

Y4

AX1

AX2

AY0

Y1

40

39
38
37
36
35
34
33
32
31
30
29

AY1

Y0

NC
NC
X0
X1
X2
X3
X4
X5
NC
NC
NC

NC

Figure 2 - Pin Connections

Pin Description

Pin #* Name Description

1Y3Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array.
2AY2Y2 Address Line (Input).

3RESETMaster RESET (Input): this is used to turn off all switches. Active High.
4,5 AX3,AX0 X3 and X0 Address Lines (Inputs).
6,7 NC No Connection.

8-13 X6-X11 X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch

array.
14 NC No Connection.
15 Y7 Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array.
16 NC No Connection.
17 Y6 Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array.
18 STROBE STROBE (In put): enables function selected by address and data. Address must be stable

before STROB E goes high and DATA mu st be stable on the falling edge of the STRO BE.

Active High.
19 Y5 Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array.
20 V
21 Y4 Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array.

22, 23 AX1,AX2 X1 and X2 Address Lines (Inputs).
24, 25 AY0,AY1 Y0 and Y1 Address Lines (Inputs).
26, 27 NC No Connection.

28 - 33 X5-X0 X5-X0 Analo g (Inputs/ Ou tpu t s): these are connected to the X5-X0 rows of the switch array.

34 NC No Connection.
35 Y0 Y0 Analog (Input/Output): this is connected to the Y0 column of the switch array.
36 NC No Connection.
37 Y1 Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array.
38 DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the

39 Y2 Y2 Analog (Input/Output): this is connected to the Y2 column of the switch array.
40 V

* Plastic DIP and CERDIP only.

Ground Reference.

SS

selected switch. Active High.

Positive Power Sup pl y.

DD

3-28

ISO-CMOS MT8812

Functional Description

The MT8812 is an analog switch matrix with an array
size of 8 x 12. The switch array is arranged such that
there are 8 columns by 12 rows. The columns are
referred to as the Y input/output lines and the rows
are the X input/output lines. The crosspoint analog
switch array will interconnect any X line wit h any Y
line when turned on and provide a high degree of
isolation when turned off. The control memory
consists of a 96 bit write only RAM in which the bits
are selected by the address input lines (AY0-AY2,
AX0-AX3) . Data is presented to the memory on the
DATA input line. Data is asynchro-nously written into
memory whenever the STROBE input is high and is
latched on the falling edge of STROBE. A logical “1”
written into a memory cell turns the corresponding
crosspoint switch on and a logical “0” turns the
crosspoint off. Only the crosspoint switches
corresponding to the addressed memory location are
altered when data is written into memory. The
remaining switches retain their previous s tates. Any
combination of X and Y lines can be interconnected
by establishing appropriate patterns in the control
memory. A logical “1” on the RESET input line will
asynchronously return all memory locations to logical
“0” turnin g off al l cr o ssp oi n t s witches.

Address Decode

The seven address lines along with the STROBE
input are logically ANDed to form an enable signal
for the resettable transparent latches. The DATA
input is buffered and is used as the input to all
latches. To write to a location, RESET mu st be low
while the address and data lines are set up. Then the
STROBE input is set high and then low causing the
data to be latched. The data can be changed while
STROBE is high, however, the corresponding switch
will turn on and off in accordance with the data. Data
must be stable on the falling edge of STROBE in
order for corr e ct da ta to be written to th e latc h .

3-29

MT8812 ISO-CMOS

Absolute Maximum Ratings*- Voltages are with respect to V

unless otherwise stated.

SS

Parameter Symbol Min Max Units

1 Supply Voltage V

2 Analog Input Voltage V
3 Digital Input Voltage V

DD

V

SS

INA

IN

-0.3

-0.3

V

16.0

DD

+0.3

-0.3 VDD+0.3 V

VSS-0.3 VDD+0.3 V
4 Current on any I/O Pin I ±15 mA
5 Storage Tem perature T
6 Package Power Dissipation PLASTIC DIP

CERDIP

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Recommended Operating Conditions - Voltages are with respect to V

S

P

D

P

D

SS

-65 +150 °C

0.6

1.0

unless otherwise stated.

Characteris tics Sym Min Typ Max Units Test Conditio ns

1 Operating Temperature T
2 Supply Voltage V
3 Analog In put Voltage V

4 Digital In put Voltage V

DC Electrical Characteristics

†

Characteristics Sym Min Typ

O

DD

INA

IN

- Voltages are with respect to V

025 70 °C

4.5 14.5 V

V

SS

V

SS

‡

SS

V

DD

V

DD

=0V, V

DD

V
V

=14V unless otherwi se stated .

Max Units Test Conditio ns

V
V

W
W

1 Quiescent Supply Current I

DD

1100µA All digital inputs at VIN=VSS or

V

DD

7 15 mA A ll digi tal inp uts at VIN=2.4V

2 Off-state Leakage Current

(See G.9 in Appendix)
3 Input Logic “0” level V
4 Input Logic “1” level V
5 Input Leakage (digital pins) I

† DC Electrical Characteristics are over recommended temperature range.
‡ Typical figures are at 25°C and are for design aid only; not guaran teed and no t subject to producti on testing .

DC Electrical Characteristics- Switch Resistance - V

I

OFF

IL
IH

LEAK

±1 ± 500 nA IVXi - VYjI = VDD - V

0.8 V

2.4 V

0.1 10 µA All digital inp uts at VIN = VSS

is the external DC offset applied at the analog I/O pins.

DC

See Appendix, Fig. A.1

or V

DD

Characteristics Sym 25°C 6 0°C 70°C Units Test Conditio ns

Typ Max Typ Max Typ Max

1 On-state V

Resistance V

=14V

DD

=12V

DD

V

=10V

DD

V

= 5V

DD

R

ON

45
60
65

145

65
85
95

220

75

95
110
260

Ω

VSS=0V,VDC=VDD/2,

Ω

IV
See Appendix, Fig. A.2

Ω
Ω

(See G.1, G.2, G.3 in
Appendix)

2 Difference in on-state

resistance between two
switches
(See G.4 in Appendix)

∆R

510 10 10 ΩVDD=14V, VSS=0,

ON

V
IV
See Appendix, Fig. A.2

I = 0.4V

Xi-VYj

DC=VDD

I = 0.4V

Xi-VYj

SS

/2,

3-30

ISO-CMOS MT8812

AC Electrical Characteristics† - Crosspoint Performance-V

I/O pins. Voltages are with respect to V

=7V, VDC=0V, VSS=-7V, unless otherwise stated.

DD

is the external DC offset applied at the analog

DC

Characteristics Sym Min Typ‡Max Units Test Co nditions

1 Switch I/O Capacitance C
2 Feedthrough Capacitance C
3 Frequency Response

F
Channel “ON”
20LOG(V

OUT/VXi

4 Total Harmonic Distortion

)=-3dB

THD 0.01 % Switch is “ON”; V
(See G.5, G.6 in Appendix)

5 Feedthrough

FDT -95 dB All Switches “OFF”; V
Channel “OFF”
Feed.=20LOG (V

OUT/VXi

)

(See G.8 in Appendix)

6 Crosstalk between any two

X
channels for switches Xi-Yi and
Xj-Yj .

Xtalk=20LOG (V

Yj/VXi

).

(See G.7 in Appendix).

S
F

3dB

talk

20 pF f=1 MHz

0.2 pF f=1 MHz
45 MHz Switch is “ON”; V

sinewave; R

= 1kΩ

L

See Appendix, Fig. A.3

sinewave f= 1k Hz; R

2Vpp sinewave f= 1kHz;
R

= 1kΩ.

L

See Appendix, Fig. A.4

-45 dB V

-90 dB V

-85 dB V

-80 dB V

=2Vpp sinewave

INA

f= 10MHz; R

=2Vpp sinewave

INA

f= 10kHz; R

=2Vpp sinewave

INA

f= 10kHz; R

=2Vpp sinewave

INA

f= 1kHz; R

L

= 75Ω.

L

= 600Ω.

L

= 1kΩ.

L

= 10kΩ.
Refer to Appendix, Fig. A.5
for test circuit.

7 Propagation delay thro ugh

t

PS

30 ns RL=1kΩ; CL=50pF

switc h

† Timing is over recommended temp era tu re range . See Fig. 3 for control and I/O timing details.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to producti on testin g.
Crosstal k m ea su r em e nts a re fo r Pl as tic D I PS o nl y, cross tal k va lu es f or PLCC pa ckag es are ap proximately 5d B better.

AC Electrical Characteristics† - Control and I/O Timings- V

I/O pins. Voltages are with respect to V

=7V, VDC=0V, VSS=-7V, unless otherwise stated.

DD

is the external DC offset applied at the analog

DC

Characteristics Sym Min Typ‡Max Units Test Conditions

= 2Vpp

INA

= 2Vpp

INA

L

=1kΩ

=

INA

1 Control Input crosstalk to switch

(for CS, DATA, STROBE,

Address)
2 Digit al Input Capa citan ce C
3 Switching Frequency F
4 Se tup Time DATA to STRO BE t
5 Hold Time DATA to STROBE t
6 Setup Time Address to STROBE t
7 Hold Time Address to STROBE t
8 STROBE Pulse Width t
9 RES E T Pulse Widt h t

10 STROBE to Switch Status Delay t
11 DATA to Switch Status Delay t
12 RESET to Switch Status Delay t

† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Inp ut ris e tim e (t r) an d fall tim e ( tf) = 5 ns .

‡ Typical figures are at 25°C and are for design aid only; not guaran teed and no t subject to producti on testing .



Refer t o A pp en di x, Fi g. A.7 fo r te st c ircuit.

CX

SPW
RPW

DS
DH
AS
AH

S
D
R

talk

DI
O

30 mVpp VIN=3V+VDC squarewave;

R

IN

See Appendix, Fig. A.6

10 pF f=1M Hz

20 MHz
10 ns RL= 1kΩ, CL=50pF
10 ns RL= 1kΩ, CL=50pF
10 ns RL= 1kΩ, CL=50pF
10 ns RL= 1kΩ, CL=50pF
20 ns RL= 1kΩ, CL=50pF
40 ns RL= 1kΩ, CL=50pF

40 100 ns RL= 1kΩ, CL=50pF
50 100 ns RL= 1kΩ, CL=50pF
35 100 ns RL= 1kΩ, CL=50pF

=1kΩ, RL=10kΩ.











3-31

MT8812 ISO-CMOS

t

RPW

RESET

STROBE

ADDRESS

DATA

SWITCH*

t

SPW

t

AS

50% 50%

50% 50%

t

DS

ON

t

AH

t

DH

50% 50%

50%50%50%

OFF

t

D

t

S

t

R

Figure 3 - Control Memory Timing Diagram

* Se e Append ix, Fig. A.7 for switching wavef orm

AX0 AX1 AX2 AX3 AY0 AY1 AY2 Connection

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1

➀

This add r es s ha s no e ffec t o n d ev ic e s tat us .

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0

↓

0
0

↓

0
0

↓

0
0

↓

0
0

↓

0
0

↓

0
0

↓

0

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1
0

↓

1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1

↓

1
0

↓

0
1

↓

1
0

↓

0
1

↓

1
0

↓

0
1

↓

1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0

↓

0
1

↓

1
1

↓

1
0

↓

0
0

↓

0
1

↓

1
1

↓

1

Table 1. Address Decode Truth Table

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0

↓

0
0

↓

0
0

↓

0
1

↓

1
1

↓

1
1

↓

1
1

↓

1

No Connection

No Connection

No Connection
No Connection

X0-Y0
X1-Y0
X2-Y0
X3-Y0
X4-Y0
X5-Y0

X6-Y0
X7-Y0
X8-Y0

X9-Y0
X10-Y0
X11-Y0

X0-Y1

↓ ↓

X11-Y1

X0-Y2

↓ ↓

X11-Y2

X0-Y3

↓ ↓

X11-Y3

X0-Y4

↓ ↓

X11-Y4

X0-Y5

↓ ↓

X11-Y5

X0-Y6

↓ ↓

X11-Y6

X0-Y7

↓ ↓

X11-Y7

t

R

➀

➀

➀
➀

3-32