Datasheet MT8806AC, MT8806AE, MT8806AP Datasheet (MITEL)

ISO-CMOS



MT8806

8 x 4 Analog Switch Array

Features

• Internal cont rol lat ches and add ress d eco der

• Short set-up and hold times

• Wide ope rating v oltag e: 4. 5V to 13.2V

• 12Vpp anal og s ignal capabi lity

•R

• ∆R

65Ω max. @ VDD=12V, 25°C

ON

≤ 10Ω @ VDD=12V, 25°C

ON

• Full CMOS switch for low distortion

• Minimum f eedthr oug h and c ros stal k

• Separate ana lo g and di gital re ferenc e supp lies

• Low power consumption ISO-CMOS technology

Applications

• Key systems

• PBX systems

• Mobile rad io

• Test equipment /instr umen tatio n

• Analo g/ di gita l m ult ip le xers

• Audio/Video switching

ISSUE 2 November 1988

Ordering Information

MT8806AC 24 Pin Ce r am i c D IP
MT8806AE 24 Pin Pla stic D IP
MT8806AP 28 Pin PL C C

-40° to 85°C

Description

The Mitel MT8806 is fabricated in MITEL’s ISO­CMOS technology providing low power dissipation
and high reliability. The device contains a 8 x 4 array
of crosspoint switches along with a 5 to 32 line
decoder and latch circuits. Any one of the 32
switches can be addressed by selecting the
appropriate five address bits. The selected switch
can be turned on or off by applying a logical one or
zero to the DATA input. V
of the digital inputs. The range of the analog
signal is from V

to VEE. Chip Select (CS) allows

DD

the crosspoint array to be cascaded for matrix
expansion.

is the ground reference

SS

AX0

AX1

AY0

AY1

AY2

CS STROBE DATA RESET VDD VEE VSS

11

8 x 4

5 to 32

Decoder

Latches

Switch

Array

3232

• • • • • • • • • • • • • • • • • • •

Yi I/O (i=0-7)

Figure 1 - Functional Block Diagram

• • • • • • • • • • • • • • • •

Xi I/O
(i=0-3)

3-9

MT8806 ISO-CMOS

D

1

0

D

2

4

3

Y

Y

3

2

•

3

4

1

1

3

S

X

S
V

Y

V

Y

Y

1

7

6

8

2

2

2

Y5

25

Y6

24

Y7

23
22

RESET

21

STROBE

20

AY2

19

5

7

6

1

1

1

1

0

E

Y

Y

E

A

A

V

NC

8

1

C
N

1

Y2

2

Y1

3

Y0

DATA

AX0
AX1

VSS

4
5

X0

6

X1

7
8

X2

9

CS

10

X3

11
12

24 PIN CERDIP/PLASTIC DIP

24
23
22
21
20
19
18
17
16
15
14
13

VDD
Y3
Y4
Y5
Y6
Y7
RESET
STROBE
AY2
AY1
AY0
VEE

NC

D0

J0

D1

J1

D2

J2

C
N

4

5
6
7
8
9
10
11

2

1

S
C

28 PIN PLCC

Figure 2 - Pin Connections

Pin Description

Pin #* Name Description

1-3 Y2-Y0 Y2-Y0 Anal og (Inputs/ Ou tputs): these are connected to the Y2-Y0 columns of the

switch array.

4DATADATA (Input): a logic high input will turn on the selected switch and a logic low will turn off

the selected switch. Active High.
5X0X0 Analog (Input/Output): this is connected to the X0 row of the switch array.
6AX0X0 Address Li n e (Input).
7X1X1 Analog (Input/Output): this is connected to the X1 row of the switch array.
8AX1X1 Address Li n e (Input).
9X2X2 Analog (Input/Output): this is connected to the X2 row of the switch array.

10 CS Chip Select (Input): this is used to select the device. Active High.
11 X3 X3 Analog (Input/Output): this is connected to the X3 row of the switch array.
12 V
13 V

Digital Ground Reference.

SS

Negative Power Supply.

EE

14-16 AY0-AY2 Y0 -Y2 Address Lines (Inputs).

17 STROBE STROBE (Input): enables function selected by address and data. Address must be stable

before STRO BE goes high and DATA must be stable on the falling edge of the STROBE .

Active High.

18 RESET Master RESET (Input): this is used to turn off all switches regardless of the condition of

CS. Active High.

19-23 Y7-Y3 Y7-Y3 Anal og (Inputs/ Ou tputs): these are connected to the Y7-Y3 columns of the

switch array.

24 VDD Positive Pow er Supp ly.

* Plastic DIP and CERDIP only

3-10

ISO-CMOS MT8806

Functional Description

The MT8806 is an analog switch matrix with an array
size of 8 x 4. The switch array is arranged such that
there are 8 columns by 4 rows. The columns are
referred to as the Y inputs/outputs and the rows are
the X inputs/outputs. The crosspoint analog switch
array will i n te r co n ne c t a n y X I/O with an y Y I/O when
turned on and provide a high degree of isolation
when turned off. The control memory consists of a 32
bit write only RAM in which the bits are selected by
the address inputs (AY0-AY2, AX0 & AX1). Data is
presente d to th e me m o ry o n th e DATA input. Da ta is
asynchronously written into memory whenever both
the CS (Chip Select) and the STROBE inputs are
high and is latched on the f alling edge of STROBE. A
logical “1” written into a memory cell turns the
corresponding crosspoint switch on and a logical
“0” turns the crosspoint off. Only the crosspoint
switches corresponding to the addressed memory
location are altered when data is written into
memory. The remaining switches retain their
previous states. Any combination of X and Y inputs/
outputs can be interconnected by establishing
appropriate patterns in the control memory. A logical
“1” on the RESET input will asynchronously return all
memory locations to logical “0” turning off all
crosspoint switches regardless of whether CS is high
or low. Two voltage reference pins (V
are provided for the MT8806 to enable switching of
negative analog signals. The range for digital
signals is from V

DD

to V

analog signals is from V

DD

while the range for

SS

to VEE. VSS and VEE pins
can be tied together if a single voltage reference is
needed.

and VEE)

SS

Address Decode

The five address inputs along with the STROBE and
CS (Chip Select) inputs are logically ANDed to form
an enable signal for the resettable transparent
latches. The DATA input is buffered and is used as
the input t o a ll l at che s. To write to a lo cation, RESET
must be low and CS must go high while the address
and data are set up. Then the STROBE input is set
high and then low causing the data to be latched.
The data can be changed while STROBE is high,
however, the corresponding switch will turn on and
off in accordance with the DATA input. DATA must be
stable on the falling edge of STROBE in order for
correct data to be written to the latch.

3-11

MT8806 ISO-CMOS

Absolute Maximum Ratings *- Voltages are with respect to V

unless otherwise stated.

EE

Parameter Symbol Min Max Units

1 Supply Voltage V

2 Analog Input Voltage V
3 Digital Input Voltage V

DD

V

SS

INA

IN

-0.3

-0.3

V

15.0

DD

+0.3

-0.3 VDD+0.3 V

VSS-0.3 VDD+0.3 V
4 Current on any I/O Pin I ± 15 mA
5 Storage Tem peratu re T
6 Package Power Dissipation PLASTIC DIP

CERDIP

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Recommended Operating Conditions - Voltages are with respect to V

S

P

D

P

D

EE

-65 +150 °C

0.6

1.0

unless otherwise stated.

Characteris tics Sym Min Typ Max Units Test Conditions

1 Operating Temperature T
2 Supply Voltage V

3 Analog In put Voltage V
4 Digital In put Voltage V

DC Electrical Characteristics

†

Characteristics Sym Min Typ

DD

V

SS

INA

- Voltages are with resp e ct to V

-40 25 85 °C

O

4.5

V

EE

V

EE

V

IN

SS

V

EE=VSS

‡

Max Units Test Conditio ns

13.2

DD

V

DD

V

DD

-4.5

=0V, V

V
V

V
V

=12V unless otherwise stated.

DD

V
V

W
W

1 Quiescent Supply Current I

DD

1100µA All digital inputs at VIN=VSS or

V

DD

0.4 1.5 mA All digi tal i np uts at VIN=2.4 +
V

; VSS =7.0V

SS

5 15 mA All digi tal i np uts at V

2 Off-state Leakage Current

(See G.9 in Appendix)

3 Input Logic “0” level V
4 Input Logic “1” level V

5 Input Logic “1” level V
6 Input Leakage (digital pins) I

† DC Electrical Characteristics are over recommended temperature range.
‡ Typical figures are at 25°C and are for desi gn aid only; not guarantee d and not subje ct to producti on testing.

DC Electrical Characteristics- Switch Resistance - V

I

OFF

IL

IH
IH

LEAK

±1 ± 500 nA IVXi - VYjI = VDD - V

0.8+V

S

S

2.0+V

SS

3.3 V

0.1 10 µ A All digital i np uts at VIN = VSS

is the external DC offset applied at the analog I/O pins.

DC

See Appendix, Fig. A.1

VVSS =7.5V; VEE=0V
VVSS =6.5V; VEE=0V

or V

DD

Characteristics Sym 25°C 70°C 85°C Units Test Conditions

Typ Max Typ Max Typ Max

1 On-state V

Resistance V

=12V

DD

=10V

DD

V

= 5V

DD

R

ON

45
55

120

65
75

185

75
85

215

80
90

225

Ω

VSS=VEE=0V , VDC=VDD/2,

Ω

IV

Ω

See Appendix, Fig. A.2
(See G.1, G.2, G.3 in
Appendix)

2 Difference in on-state

resistance between two
switches
(See G.4 in Appendix)

∆R

510 10 10 ΩVDD=12V, VSS=VEE=0,

ON

V

IV

See Appendix, Fig. A.2

I = 0.4V

Xi-VYj

DC=VDD

I = 0.4V

Xi-VYj

/2,

IN

EE

=3.4V

3-12

ISO-CMOS MT8806

AC Electrical Characteristics† - Crosspoint Performance - Voltages are with respect to V

=-7V, unless otherwise stated.

V

EE

DD

Characteristics Sym Min Typ‡Max Units Test Conditions

1 Switch I/O Capacitance C
2 Feedthrough Capacitance C
3 Frequency Response

F
Channel “ON”
20LOG(V

OUT/VXi

4 Total Harmonic Distortion

)=-3dB

THD 0.01 % Switch is “ON”; V
(See G.5, G.6 in Appendix)

5 Feedthrough

FDT -95 dB All Switches “OFF”; V
Channel “OFF”
Feed.=20LOG (V

OUT/VXi

)

(See G.8 in Appendix)

6 Crosstalk between any two

X
channels for switches Xi-Yi and
Xj-Yj .

Xtalk=20LOG (V

Yj/VXi

).

(See G.7 in Appendix).

S
F

3dB

talk

20 pF f=1 MHz

0.2 pF f=1 MHz
45 MHz Switch is “ON”; V

sinewave; R

= 1kΩ

L

See Appendix, Fig. A.3

sinewave f= 1kHz; R

2Vpp sinewave; f= 1kHz;
R

= 1kΩ.

L

See Appendix, Fig. A.4

-45 dB V

-90 dB V

-85 dB V

-80 dB V

=2Vpp sinewave

INA

f= 10MHz; R

=2Vpp sinewave

INA

f= 10kHz; R

=2Vpp sinewave

INA

f= 10kHz; R

=2Vpp sinewave

INA

f= 1kHz; R

L

= 75Ω.

L

= 600Ω.

L

= 1kΩ.

L

= 10kΩ.
Refer to Appendix, Fig. A.5
for test circuit.

7 Propagation delay thro ugh

t

PS

30 ns RL=1kΩ; CL=50pF

switc h

† Timing is over recommended tempera tu re range . See Fig. 3 for control and I/O timing details.
‡ Typical figures are at 25°C and are for design aid only; not guaran te ed and not subj ect to producti on testin g.
Crosstal k m ea su r em e nts a re fo r Pl as tic D I PS o nl y, cross tal k va lu es f or PLCC pa ckag e s a re approxim ately 5dB b etter.

AC Electrical Charact eristics† - Control and I/O T i mings - Voltages are with respect to V

V

=-7V , unless otherwise stated.

EE

=5V, VSS=0V,

DD

Characteristics Sym Min Typ‡Max Units Test Conditions

=5V, VSS=0V,

= 2Vpp

INA

= 2Vpp

INA

=1kΩ

L

=

INA

1 Control Input crosstal k to switch

CX

talk

30 mVpp VIN=3V squarewave;

(for CS, DATA, STROBE, Address)

2 Digital Input Capacitance C
3 Switching Frequency F
4 Setup Time DATA to STROBE t
5 Hold Time DATA to STROBE t
6 Setup Time Address to STROBE t
7 Hold Time Address to STROBE t
8 Setup Time CS to STROBE t
9 Hold Time CS to STROBE t

10 S TRO BE Pulse Widt h t

11 RESET Pulse Width t
12 STROBE to Switch Status Delay t
13 DATA to Switch Status Delay t
14 RE S E T to Switch Status Delay t

† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Inp ut ris e tim e (t r) an d fall time (tf) = 5 ns .
‡ Typical figures are at 25°C and are for desi gn aid only; not gua rantee d and not subje ct to producti on testing.



Refer to Ap pe nd ix , Fig. A.7 for te st ci rc uit .

DI

O
DS
DH
AS
AH

CSS

CSH
SPW
RPW

S
D
R

10 ns RL= 1kΩ, CL=50pF
10 ns RL= 1kΩ, CL=50pF
10 ns RL= 1kΩ, CL=50pF
10 ns RL= 1kΩ, CL=50pF
10 ns RL= 1kΩ, CL=50pF
10 ns RL= 1kΩ, CL=50pF
20 ns RL= 1kΩ, CL=50pF
40 ns RL= 1kΩ, CL=50pF

10 pF f=1MHz

20 MH z

40 100 ns RL= 1kΩ, CL=50pF
50 100 ns RL= 1kΩ, CL=50pF
35 100 ns RL= 1kΩ, CL=50pF

R

=1kΩ, RL=10kΩ.

IN

See Appendix, Fig. A.6

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3-13

MT8806 ISO-CMOS

t

CSS

CS

RESET

50% 50%

t

SPW

STROBE

t

AS

ADDRESS

DATA

SWITCH*

50% 50%

50% 50%

t

DS

ON
OFF

Figure 3 - Control Memory Timing Diagram

* See Appendix, Fig. A.7 for switching waveform

t

CSH

t

RPW

50% 50%

50%50%50%

t

AH

t

DH

t

D

t

S

t

R

t

R

AX0 AX1 AY0 AY1 AY2 Connection

0 0 0 0 0 X0-Y0
0 0 1 0 0 X0-Y1
0 0 0 1 0 X0-Y2
0 0 1 1 0 X0-Y3
0 0 0 0 1 X0-Y4
0 0 1 0 1 X0-Y5
0 0 0 1 1 X0-Y6
0 0 1 1 1 X0-Y7
1

↓

1
0

↓

0
1

↓

1

0

↓

0
1

↓

1
1

↓

1

0

↓

1
0

↓

1
0

↓

1

0

↓

1
0

↓

1
0

↓

1

0

↓

1
0

↓

1
0

↓

1

X1-Y0

↓ ↓

X1-Y7
X2-Y0

↓ ↓

X2-Y7
X3-Y0

↓ ↓

X3-Y7

Table 1. Address Decode Truth Table

3-14