Datasheet MT70014 Datasheet (Aeroflex Circuit Technology)

MT70014

TWO CHANNEL ARINC TRANSMITTER

• 8 bit parallel interface

• TTL/CMOS compatible I/P

• Single 5V supply with low power

consumption < 50mW

• Full MIL operating range

• Automatic parity generation

• HIGH/LOW speed programmable

independently in each channel

VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS

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MT70014

MAXIMUM RATINGS (Above which the useful life may be impaired)

Storage Temperature - 65ºC to +150ºC
Temperature (Ambient) under Bias - 55ºC to +125ºC
Supply Voltage VDD -0.3V to + 7V
DC Input Voltage -0.3 to VDD +0.3V
Output Current (Single O/P) 10mA
Output Current (Total O/P) 20mA

ELECTRICAL CHARACTERISTICS over operating range

PARAMETER DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS
IOH Output High Current VOH=2.8V VDD= 4.5V 1.0
IOL Output Low Current VOL=0.4V 3.2
VIH Input High Voltage 2.4 VCC
VIL Input Low Voltage -0.3 0.8
IIL Input Load Current VSS 0.45
IOZ Output Leakage Current
CI Input Capacitance
CI/O I/O Capacitance 7 9
ICC Supply Current

0.4V<VO<VCC Output Disabled

Test Frequency = 1.0 MHZ

VCC = MAX. All inputs
HIGH, All outputs open.

-40 40
2 2.6

1.5

mA
mA
Volts
Volts
mA
uA
pF
pF
mA

VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS

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3. SWITCHING CHARACTERISTICS (For CL = 50pF & RL = 3K ohms)

PARAMETER Min Max Units

MT70014

f

t

t

t

t

t

t

t

t

t

CLK

P

RES

RTC

RD

WL

GL

SU

H

LTC

Clock Frequency - 5 MHz

( Serial data bit period for HNL input high 50/f uS
(
( Serial data bit period for HNL input low 380/f uS
(
( (f = f

CLK

/MHz)

NRSET pulse width 200nS -

Propagation delay, NRESET falling edge to TXC high - 200nS

Propagation delay, NRESET falling edge to data outputs low - 200nS

NLD pulse width 200nS -

Gap between NLD pulses 400nS -

Data set up time 100nS -

Data hold time 100nS -

Propagation delay, NLD rising edge following last - 400nS
byte load to TXZ low

t

t

t

t

t

t

R

F

WTE

TED

DTC

M

Output rise time - 50nS

Output fall time - 50nS

NOT Transmit enable pulse width 100nS -

Propagation delay NOT transmit enable falling )
edge or ) tp 2tp
NOT Transmission complete falling edge to )
data output )

Last data bit of message to TXC high - 200nS

Time of data pulse output (mark time) tp + 1%

2

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MT70014

FUNCTIONAL DESCRIPTION

The device consists of two independent channels each of which functions as a parallel to serial data converter.
The parallel data is loaded via an 8-bit input highway and the serial output is generated in the ARINC
format, i.e. 31 bits of data plus one parity bit.

The input highway (DIO to D17) is common to both channels as are the reset (NRESET) CLOCK 9clock),
positive supply (VDD), and ground (VSS) pins. Each channel has 3 control inputs. Channel 0 has a ‘load’
input (NLDO), a ‘transmit enable’ input (NTXEO), and a ‘high/low speed’ (HNLO) control input. There are
3 outputs per channel. Channel 0 has a ‘data out zeros’ (ZDO) output, a ‘data out ones’ (ODO) output and a
‘transmission complete’ (TXCO) output.

Operations for Channel 0 and Channel 1 are identical in all respects.

The data to be transmitted by a particular channel is loaded as four 8-bit bytes via the input highway. The
four bytes are stored on chip in the order in which they were loaded. Loading is performed by pulsing the
(NLDO) input low. The data must then be changed to the value of the next byte and (NLDO) pulsed low
again etc.

The four bytes are transmitted in the order in which they were loaded. The only exception is the most
significant bit of the 4th byte. This bit is ignored and a parity bit is transmitted in its place. The parity bit
corresponds to an odd parity check on the first 31 bits, i.e. if the number of ones in the first 31 bits is odd, the
parity bit is equal to zero.

Data is only accepted if the TXCO output is high. Once byte 4 has been loaded, TXCO is driven low. Data
must be valid on the input highway for tsu before and to tH after the (NLDO) rising edge.

The clock (CLOCK) input of 5mhz + 1%* is divided down on chip by 50 to give a serial data transmission
rate for (HNLO) high or by 380 for (HNLO) low. These rates correspond to the ARINC fast and slow rates
respectively. The timing of the two output data lines (ODO) and (ZDO) is shown in Fig.2. A data value of
one is signified by a positive pulse output on (ODO) and a zero by a positive pulse on (ZDO). The bit period
tp will be 50/f

for (HNLO) high and 380/f

CLK

for (HNLO) low.

CLK

* ARINC recommends that the transmission rate should not be precisely 100KHZ to avoid interference but
any rate within + 1% of these can be used.

The overall timing diagram for a complete data transfer is shown in Fig.3. When the last byte has been
loaded (TXCO) goes low. This signal is combined with the output of an on chip latch which is set by the
(NTXEO) signal to initiate the start of transmission. The latch is reset upon start of transmission. If the
(NTXEO) signal is left permanently low the on chip latch is always set and transmission will be initiated by
TXCO going low, i.e. as soon as the 4 bytes have been loaded. Hence there is an option between auto-start
and controlled-start of transmission. At the end of the transmission TXCO goes high and the device is able
to accept new data.

The devices can be completely reset by pulsing the (NRESET) line low. This causes both channels to be put
into the data load phase of operation. The TXC lines are forced high and all data outputs are forced low. the
timing is shown in Fig. 4.

INTERFACE DEFINITIONS

The device is implemented as a monolithic circuit using CMOS compatible with standard TLL circuitry.

A circuit with V

(min) = 2.7V and VOL (max) = 0.4V will drive all inputs to the device and a standard TTL

OH

circuit with IIL (max) = -1.6mA at VI = 0.4V and IIH (max) = 40 uA at VI = 2.4V can be driven by all the
outputs of the device.

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MT70014

An on-chip resistor of nominal value 25K ohms is connected between the input pin and VDD. This is intended
to pull up the input to a sufficiently high voltage to ensure switching when a standard TTL driver is driving
the input.

VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS

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MT70014

VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS

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MT70014

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