Datasheet MT5C6401C-70L-IT, MT5C6401C-55L-XT, MT5C6401C-55L-883C, MT5C6401C-20L-IT, MT5C6401C-15L-XT Datasheet (AUSTIN)

Austin Semiconductor, Inc.

SRAM

MT5C6401

64K x 1 SRAM

SRAM MEMORY ARRAY

AVAILABLE AS MILITARY
SPECIFICATIONS

• SMD 5962-86015

• MIL-STD-883

FEATURES

• Speeds: 12, 15, 20, 25, 35, 45, 55, and 70ns

• Battery Backup: 2V data retention

• High-performance, low-power CMOS double-metal
process

• Single +5V (+10%) Power Supply

• Easy memory expansion with CE\

• All inputs and outputs are TTL compatible

OPTIONS MARKING

• Timing

12ns access -12
15ns access -15
20ns access -20
25ns access -2 5
35ns access -3 5
45ns access -45*
55ns access -55*
70ns access -70*

• Package(s)

Ceramic DIP (300 mil) C No. 105

• Operating T emperature Ranges

Industrial (-40oC to +85oC) IT
Military (-55oC to +125oC) XT

PIN ASSIGNMENT

(Top View)

22-Pin DIP (C)

(300 MIL)

1

22
2
3
4
5
6
7
8
9
10
11

Vcc

21

A15

20

A14

19

A13

18

A12

17

A11

16

A10

15

A9

14

A8

13

D

12

CE\

WE\

Vss

A0
A1
A2
A3
A4
A5
A6
A7

Q

GENERAL DESCRIPTION

The Austin Semiconductor SRAM family employs

high-speed, low-power CMOS designs using a four-transistor
memory cell. Austin Semiconductor SRAMs are fabricated
using double-layer metal, double-layer polysilicon
technology.
For flexibility in high-speed memory applications, Austin
Semiconductor offers chip enable (CE\) on all organizations.
This enhancement can place the outputs in High-Z for
additional flexibility in system design. The X1 configuration
features separate data input and output.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is
accomplished when WE\ remains HIGH and CE\ goes LOW.
The device offers a reduced power standby mode when
disabled. This allows system designs to achieve low standby
power requirements.
All devices operate from a single +5V power supply and
all inputs and outputs are fully TTL compatible.

• 2V data retention/low power L

*Electrical characteristics identical to those provided for the 35ns

access devices.

MT5C6401

Rev. 1.0 8/01

For more products and information

please visit our web site at

www.austinsemiconductor .com

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

1

Austin Semiconductor, Inc.

FUNCTIONAL BLOCK DIA GRAM

V

CC

GND

SRAM

MT5C6401

A

D

A
A
A
A
A

ROW DECODER

65,536-BIT

MEMORY ARRAY

I/O CONTROL

Q

CE\

A

(LSB)

WE\

POWER

COLUMN DECODER

(LSB)

DOWN

A A A A A A A A A

MT5C6401

Rev. 1.0 8/01

TRUTH TABLE

MODE CE\ WE\ DQ POWER

STANDBY H X HIGH-Z STANDBY
READ L H Q ACTIVE
WRITE L L HIGH-Z ACTIVE

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

2

Austin Semiconductor, Inc.

SRAM

MT5C6401

ABSOLUTE MAXIMUM RATINGS*

Voltage on any Input Relative to Vss................-2.0V to +7.0V

Voltage on Vcc Supply Relative to Vss............-1.0V to +7.0V

Voltage Applied to Q.........................................-1.0V to +7.0V

Storage Temperature…...................................-65oC to +150oC

Power Dissipation.................................................................1W

Max Junction T emperature............................................+175°C

*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods

may affect reliability .

Lead Temperature (soldering 10 seconds)...................+260oC

Short Circuit Output Current...........................................50mA

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS

(-55oC < TC < 125oC; VCC = 5V +10%)

DESCRIPTION CONDITIONS SYM MIN MAX UNITS NOTES

Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current

Output Leakage Current
Output High Voltage

Output Low Voltage

0V <

VIN < V

CC

Outputs Disabled

0V < V

I

OH

I

OL

< V

OUT

CC

= -4.0mA V

= 8.0mA V

V

V

IL

IL

OH

OL

2.2 Vcc+1.0V V 1

IH

-0.5 0.8 V 1, 2

IL

-10 10 µA

I

-10 10 µA

O

2.4 --- V 1

--- 0.4 V 1

PARAMETER

Power Supply
Current: Operating

Power Supply
Current: Standby

CONDITIONS

CE\ <

VIL; VCC = MAX

Output Open

CE\ >

VIH; VCC = MAX

f = 1/t

VIH; All Other Inputs

CE\ >

VIL or > VIH, VCC = MAX

<

CE\ >

(V

All Other Inputs <

(VCC - 0.2V), f = 0 Hz

or >

(MIN) Hz

RC

f = 0 Hz

-0.2); VCC = MAX

CC

0.2V

SYM -12 -15 -20 -25 -35 UNITS NOTES

I

I

SBT1

I

SBT2

I

SBC2

140 125 110 100 90 mA 3

cc

45 41 36 33 30 mA

25 25 25 25 25 mA

55555mA

CAPACITANCE

DESCRIPTION CONDITIONS SYM MAX UNITS NOTES

Input Capacitance C
Output Capacitance C

= 25oC, f = 1MHz

T

A

Vcc = 5V

I

O

6pF 4
7pF 4

MAX

MT5C6401

Rev. 1.0 8/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

3

SRAM

MT5C6401

Austin Semiconductor, Inc.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Note 5) (-55oC < TC < 125oC; VCC = 5V +10%)

DESCRIPTION

READ CYCLE

READ cycle time
Address access time
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Chip Enable to power-up time
Chip disable to power-down time

WRITE CYCLE

WRITE cycle time
Chip Enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
Data setup time
Data hold time
Write disable to output in Low-Z
Write Enable to output in High-Z

-12

SYMBOL UNITS

t

t

LZCE

t

HZCE

t
t
t

t

t

LZWE

t

HZWE

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

t

RC

t

AA

ACE

t

OH

12 15 20 25 35 ns

12 15 20 25 35 ns

10 13 15 20 25 ns
22222 ns
22222 ns7

7 8 10 12 15 ns 6, 7
t
t

t
t

t
t

PU
PD

WC
CW
AW

AS
AH

WP

DS
DH

00000 ns

12 15 20 25 35 ns

12 15 20 25 35 ns
10 12 15 20 25 ns
10 12 15 20 25 ns

00000 ns
00000 ns

10 12 15 20 25 ns

7 8 10 12 15 ns
00000 ns
22222 ns7
060708010015ns 6, 7

-35-25-20-15
NOTES

MT5C6401

Rev. 1.0 8/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

4

Austin Semiconductor, Inc.

3

3

1234

1234

1234

1234

3

3

4

4

3

3

4

4

SRAM

MT5C6401

AC TEST CONDITIONS

Input pulse levels ...................................... Vss to 3.0V

Input rise and fall times ......................................... 5ns

Input timing reference levels ................................ 1.5V

Output reference levels ....................................... 1.5V

Output load ................................. See Figures 1 and 2

NOTES

1 . All voltages referenced to VSS (GND).
2 . -3V for pulse width < 20ns

3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f = 1 Hz.

tRC (MIN)

4. This parameter is sampled.

5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.

6. t

Fig. 2. Transition is measured ±500mV typical from steady
state voltage, allowing for actual tester RC time constant.

HZCE

and t

are specified with CL = 5pF as in

HZWE

+5V

480

5 pF

Q

255

Fig. 1 Output Load

Equivalent

+5V

480

30pF

Q

255

Fig. 2 Output Load

Equivalent

7. At any given temperature and voltage condition,
t

is less than t

HZCE

LZCE

, and t

is less than t

HZWE

LZWE

.

8. WE\ is HIGH for READ cycle.

9. Device is continuously selected. Chip enable is held in

its active state.
10 . Address valid prior to, or coincident with, latest

occurring chip enable.

11.tRC = READ Cycle Time.

12 . Chip enable (CE\) and write enable (WE\) can initiate
and terminate a WRITE cycle.

DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)

DESCRIPTION SYM MIN MAX UNITS NOTES

V

for Retention Data V

CC

CE\ >

Data Retention Current

V

Chip Deselect to Data
Retention Time

Operation Recovery Time

CONDITIONS

(VCC - 0.2V)

> (VCC - 0.2V)

IN

or <

0.2V

V

CC

V

CC

= 2V I

= 3V I

DR

CCDR

CCDR

t

CDR

t

R

2 --- V

--- 300 µA

--- 500 µA

0 --- ns 4

t

RC

--- ns 4, 11

LOW Vcc DA T A RETENTION WA VEFORM

DA TA RETENTION MODE

4.5V

VDR > 2V

V

DR

5

4.5V
t

R

2

23

2

23

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

MT5C6401

Rev. 1.0 8/01

V

CE\

CC

t

CDR

2

23

V

IH

2

23

V

IL

2

2

DON’T CARE
UNDEFINED

Austin Semiconductor, Inc.

123

123

123

5

5

5

SRAM

MT5C6401

READ CYCLE NO. 1

READ CYCLE NO. 2

8, 9

7, 8, 10

Q

DON’T CARE

234

234

UNDEFINED

234

MT5C6401

Rev. 1.0 8/01

6

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

3

3

4

4

SRAM

MT5C6401

WRITE CYCLE NO. 1

12

(Chip Enabled Controlled)

WRITE CYCLE NO. 2

7, 12, 13

(Write Enabled Controlled)

2

2

DON’T CARE

23

23

UNDEFINED

MT5C6401

Rev. 1.0 8/01

7

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

MECHANICAL DEFINITIONS*

ASI Case #105 (Package Designator C)

SMD 5962-86015, Case Outline X

S

SRAM

MT5C6401

Pin 1

D

E

SYMBOL

A --- 0.200

b 0.014 0.023

b1 0.030 0.065

c 0.008 0.015
D --- 1.260
E 0.220 0.310

E1 0.290 0.320

e

L 0.125 0.200

L1 0.150 ---

Q 0.015 0.060
S --- 0.080

S1 0.005 --­S2 0.005 ---

NOTE: These dimensions ar e per the SMD. ASI's package dimensional limits may
differ, but they will be within the SMD limits.

MIN MAX

S2

L1

b1

S1

E1

c

SMD SPECIFICATIONS

0.100 BSC

e

b

A

Q

L

* All measurements are in inches.

MT5C6401

Rev. 1.0 8/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

8

Austin Semiconductor, Inc.

ORDERING INFORMA TION

EXAMPLE: MT5C6401C-45L/883C

SRAM

MT5C6401

Device Number

MT5C6401 C -12 L /*
MT5C6401 C -15 L /*
MT5C6401 C -20 L /*
MT5C6401 C -25 L /*
MT5C6401 C -35 L /*
MT5C6401 C -45 L /*
MT5C6401 C -55 L /*
MT5C6401 C -70 L /*

Package

Type

Speed

ns

Options** Process

*AVAILABLE PROCESSES

IT = Industrial T emperature Range -40oC to +85oC
XT = Extended T emperature Range -55oC to +125oC
883C = Full Military Processing -55oC to +125oC

** OPTIONS

L = 2V Data Retention/Low Power

MT5C6401

Rev. 1.0 8/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

9

Austin Semiconductor, Inc.

ASI TO DSCC PART NUMBER

CROSS REFERENCE*

ASI Pac kage Designator C

SMD 5962-86015

ASI Part # SMD Part #

MT5C6801C-35/883C 5962-8601501XA
MT5C6801C-35L/883C 5962-8601502XA
MT5C6801C-45/883C 5962-8601503XA
MT5C6801C-45L/883C 5962-8601504XA
MT5C6801C-55/883C 5962-8601505XA
MT5C6801C-55L/883C 5962-8601506XA

SRAM

MT5C6401

* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.

MT5C6401

Rev. 1.0 8/01

10

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.