Datasheet MT5C2561EC-70L-IT, MT5C2561EC-55L-XT, MT5C2561EC-55L-883C, MT5C2561C-35L-IT, MT5C2561C-35L-XT Datasheet (AUSTIN)

Austin Semiconductor, Inc.

256K x 1 SRAM

SRAM MEMORY ARRAY

AVAILABLE AS MILITARY
SPECIFICATIONS

• SMD 5962-88725

• SMD 5962-88544

• MIL-STD-883

FEATURES

• High Speed: 35, 45, 55, and 70

• Battery Backup: 2V data retention

• Low power standby

• High-performance, low-power, CMOS double-metal
process

• Single +5V (+10%) Power Supply

• Easy memory expansion with CE\

• All inputs and outputs are TTL compatible

OPTIONS MARKING

• Timing

35ns access -35
45ns access -45
55ns access -55*
70ns access -70*

• Package(s)

Ceramic DIP (300 mil) C No. 106
Ceramic LCC EC No. 204

MT5C2561

PIN ASSIGNMENT

(Top View)

24-Pin DIP (C)

(300 MIL)

1

A6
A7
A8

A9
A10
A11
A14
A15

A0

Q

WE\

Vss

28-Pin LCC (EC)

4

NC

5

A9

6

A10

7

A11

8

A14

9

A15

10

A0

11

Q

12

NC

24

2

23

3

22

4

21

5

20

6

19

7

18

8

17

9

16

10

15

11

14

12

13

A8A7A6

WE\

Vss

CE\

Vcc

D

3 2 1 28 27

13 14 15 16 17

A12

A17

Vcc
A5
A4
A3
A2
A1
A17
A16
A13
A12
D
CE\

26

NC

25

A4

24

A3

23

A2

22

A1

21

A17

20

A16

19

A13

18

NC

SRAM

• Operating T emperature Ranges

Industrial (-40oC to +85oC) IT
Military (-55oC to +125oC) XT

• 2V data retention/low power L

*Electrical characteristics identical to those provided for the 45ns
access devices.

For more products and information

please visit our web site at

www.austinsemiconductor .com

MT5C2561

Rev. 2.5 1/01

GENERAL DESCRIPTION

The Austin Semiconductor SRAM family employs
high-speed, low-power CMOS and are fabricated using double­layer metal, double-layer polysilicon technology.

For flexibility in high-speed memory applications,
Austin Semiconductor offers chip enable (CE\) on all organiza­tions. This enhancement can place the outputs in High-Z for
additional flexibility in system design. The x1 configuration
features separate data input and output.

Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW . Reading is accom­plished when WE\ remains HIGH and CE\ goes LOW. The
device offers a reduced power standby mode when disabled.
This allows system designs to achieve low standby power re­quirements.

These devices operate from a single +5V power sup­ply and all inputs and outputs are fully TTL compatible.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

1

Austin Semiconductor, Inc.

Q

FUNCTIONAL BLOCK DIAGRAM

V

CC

GND

SRAM

MT5C2561

A13
A14
A15
A16
A17

A0
A1
A2
A3
A4

262,144-BIT

MEMORY ARRAY

ROW DECODER

COLUMN DECODER

A5 A6 A7 A8 A9 A10 A11 A12

D

CE\

I/O CONTROL

WE\

POWER

DOWN

TRUTH TABLE

MODE CE\ WE\ DQ POWER

STANDBY H X HIGH-Z STANDBY
READ L H Q ACTIVE
WRITE L L HIGH-Z ACTIVE

MT5C2561

Rev. 2.5 1/01

2

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

SRAM

MT5C2561

ABSOLUTE MAXIMUM RA TINGS*

V oltage on Any Pin Relative to Vss..................................-0.5V to +7V

V oltage on Vcc Supply Relative to Vss.............................-0.5V to +7V

V oltage Applied to Q.........................................................-0.5V to +6V

Storage Temperature......................................................-65oC to +150oC

Power Dissipation..............................................................................1W

Short Circuit Output Current.........................................................50mA

Lead T emperature (soldering 10 seconds)....................................+260oC

Junction Temperature..................................................................+175oC

*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability .

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS

(-55oC < TC < 125oC; VCC = 5V +10%)

DESCRIPTION CONDITIONS

Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage

Input Leakage Current

Output Leakage Current

Output High Voltage
Output Low Voltage

PARAMETER

VIN<V

0V<

CC

Output(s) disabled

V

0V<

OUT<VCC

= -4.0mA V

I

OH

I

= 8.0mA V

OL

CONDITIONS

SYM

V

IH

V

IL

IL

IL

O

OH

OL

I

MIN MAX UNITS NOTES

2.2

V

+0.5

CC

V1

-0.5 0.8 V 1, 2

-10 10 µA

-10 10 µA

2.4 V 1

0.4 V 1

MAX

SYM -35 -45 UNITS NOTES

Power Supply
Current: Operating

CE\ <

VIL; VCC = MAX

f = MAX = 1/t

(MIN)

RC

Output Open

CE\ >

Power Supply
Current: Standby

VIH; All Other Inputs

<

VIL or > VIH, VCC = MAX

f = 0 Hz

CE\ >

V

-0.2V; VCC = MAX

CC

V

< VSS +0.2V

IL

V

> VCC -0.2V; f = 0 Hz

IH

"L" Version Only

CAPACITANCE

PARAMETER CONDITIONS SYM MAX UNITS NOTES

Input Capacitance C
Output Capacitance C

MT5C2561

Rev. 2.5 1/01

T

= 25oC, f = 1MHz

A

Vcc = 5V

3

I

CCSP

I

CCLP

I

SBT1

I

SBCSP

I

SBCLP

I

O

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

120 120 mA 3

100 100 mA 3

25 25 mA

20 20 mA

33mA

10 pF 4
12 pF 4

SRAM

MT5C2561

Austin Semiconductor, Inc.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Note 5) (-55oC < TC < 125oC; VCC = 5V +10%)

DESCRIPTION

READ CYCLE

READ cycle time
Address access time
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Chip Enable to power-up time
Chip disable to power-down time

WRITE CYCLE

WRITE cycle time
Chip Enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
Data setup time
Data hold time
Write disable to output in Low-Z
Write Enable to output in High-Z

SYMBOL

t

RC

t

AA

t

ACE

t

OH

t

LZCE

t

HZCE

t

PU

t

PD

t

WC

t

CW

t

AW

t

AS

t

AH

t

WP

t

DS

t

DH

t

LZWE

t

HZWE

-35 -45

MIN MAX MIN MAX UNITS NOTES

35 45 ns

35 45 ns

35 45 ns
33ns
3 3 ns 7

20 20 ns 6, 7
0 0 ns 4

35 45 ns 4

35 45 ns
30 40 ns
30 40 ns

00ns
55ns

30 40 ns
20 20 ns

00ns
0 0 ns 7
0 15 0 20 ns 6, 7

MT5C2561

Rev. 2.5 1/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

4

Austin Semiconductor, Inc.

3

3

1234

1234

1234

1234

3

3

4

4

3

3

4

4

AC TEST CONDITIONS

Input pulse levels ...................................... Vss to 3.0V

Input rise and fall times ......................................... 5ns

Input timing reference levels ................................ 1.5V

Output reference levels ....................................... 1.5V

Output load ................................. See Figures 1 and 2

SRAM

MT5C2561

167Ω

Q

VTH = 1.73V

Q

30pF

167Ω

VTH = 1.73V

5pF

Fig. 1 Output Load

Fig. 2 Output Load

Equivalent

NOTES

1 . All voltages referenced to VSS (GND).
2 . -3V for pulse width < 20ns

3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f = 1 Hz.

tRC (MIN)

4. This parameter is guaranteed but not tested.

5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.

6. t

, t

, t

, t

, t

LZCE

LZWE

LZOE

HZCE

HZOE

and t

HZWE

are
specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,

allowing for actual tester RC time constant.

7. At any given temperature and voltage condition, t
less than t
less than t

LZCE

LZOE

, and t

.

is less than t

HZWE

8. WE\ is HIGH for READ cycle.

9 . Device is continuously selected. Chip enable is held in

its active state.

10. Address valid prior to, or coincident with, latest
occurring chip enable.

11. tRC = Read Cycle Time.

12 . Chip enable (CE\) and write enable (WE\) can initiate and

terminate a WRITE cycle.

DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)

DESCRIPTION CONDITIONS SYM MIN MAX UNITS NOTES

VCC for Retention Data

Data Retention Current

Chip Deselect to Data
Retention Time

Operation Recovery Time

CE\ >

(VCC - 0.2V)

> (VCC - 0.2V)

V

IN

0.2V

or <

V

CC

= 2V I

V

DR

CCDR

t

CDR

t

R

2 --- V

900

µA

0 --- ns 4

t

RC

ns 4, 11

Equivalent

and t

LZWE

HZCE

HZOE

is

is

LOW Vcc DA T A RETENTION WA VEFORM

V

CC

t

CDR

2

23

V

IH

2

CE\

MT5C2561

Rev. 2.5 1/01

23

V

IL

DA TA RETENTION MODE

4.5V

VDR > 2V

V

DR

5

4.5V
t

R

2

23

2

23

2

2

DON’T CARE
UNDEFINED

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

SRAM

MT5C2561

ADDRESS

DQ

PREVIOUS DATA VALID

READ CYCLE NO. 1

t

tRCtRC

RC

VALID

t

tAA

AA

t

OH

tOH

READ CYCLE NO. 2

8, 9

DATA VALID

7, 8, 10

CE\

DQ

Icc

MT5C2561

Rev. 2.5 1/01

t

LZCE

tLZCE

t

tPU

PU

t

ACE

t

tRCtRC

RC

t

HZCE

tHZCEtACE

DATA VALID

t

PD

tPD

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

6

Austin Semiconductor, Inc.

1

1

1

6

6

6

6

7

3

1234

1234

1234

1234

SRAM

MT5C2561

ADDRESS

CE\

WE\

WRITE CYCLE NO. 1

12

(Chip Enabled Controlled)

t

WC

tWCtWC

t

tAW

AW

t

AS

D

t

CW

tCW

tCWtAS

t

tWP1tWP1

WP

t

DS

DATA VAILD

Q

HIGH Z

t

tDHtDS

t

AH

tAH

DH

WRITE CYCLE NO. 2

(Write Enabled Controlled)

ADDRESS

234567890123456

CE\

t

tAS

AS

WE\

D

23456789012345

23456789012345

Q

NOTE: Output enable (OE\) is inactive (HIGH).

t

HZWE

t

AW

tAW

t

tWCtWC

WC

t

CW

tCW

tCW

t

tWP1tWP1

WP

HIGH-Z

7, 12

t

DS

DATA VALID

t

AH

tAH

234567890123456789012

t

DH

tDH

t

LZWE

23

DON’T CARE

2345

2345

UNDEFINED

MT5C2561

Rev. 2.5 1/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

7

Austin Semiconductor, Inc.

MECHANICAL DEFINITIONS*

ASI Case #106 (Package Designator C)

SMD #5962-88544 & #5962-88725, Case Outline L

D

SRAM

MT5C2561

Pin 1

A

b

b2

NOTE

0o to 15

S1

E

o

eA

c

e

SMD SPECIFICATIONS

SYMBOL

MIN MAX

A --- 0.200

b 0.014 0.026

b2 0.045 0.065

c 0.008 0.018
D --- 1.280
E 0.220 0.310

eA

e

0.300 BSC

0.100 BSC

L 0.125 0.200

Q 0.015 0.060

S1 0.005 ---

NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.

Q

L

*All measurements are in inches.

MT5C2561

Rev. 2.5 1/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

8

Austin Semiconductor, Inc.

MECHANICAL DEFINITIONS*

ASI Case #204 (Package Designator EC)

SMD# 5962-88544, Case Outline X

SRAM

MT5C2561

D1

B2

D2

L2

E3

D

hx45

E

o

D3

A1

h x 45

E1

E2

o

B1

A

e

L

SMD SPECIFICATIONS

SYMBOL

MIN MAX

A 0.060 0.120
A1 0.050 0.088
B1 0.022 0.028
B2

0.072 REF

D 0.342 0.358
D1
D2

0.200 BSC

0.100 BSC

D3 --- 0.358

E 0.540 0.560
E1
E2

0.400 BSC

0.200 BSC

E3 --- 0.558

e

h

0.050 BSC

0.040 REF

L 0.045 0.055
L2 0.075 0.095

NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.

*All measurements are in inches.

MT5C2561

Rev. 2.5 1/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

9

Austin Semiconductor, Inc.

MT5C2561EC-70/XT

ORDERING INFORMATION

SRAM

MT5C2561

EXAMPLE: MT5C2561C-45L/IT

Device

Number

MT5C2561 C -35 L /* MT5C2561 EC -35 L /*
MT5C2561 C -45 L /* MT5C2561 EC -45 L /*
MT5C2561 C -55 L /* MT5C2561 EC -55 L /*
MT5C2561 C -70 L /* MT5C2561 EC -70 L /*

Package

Type

Speed

ns

Options** Process

EXAMPLE:

Device

Number

Package

Type

Speed

ns

Options** Process

*AVAILABLE PROCESSES

IT = Industrial T emperature Range -40oC to +85oC
XT = Extended T emperature Range -55oC to +125oC
883C = Full Military Processing -55oC to +125oC

MT5C2561

Rev. 2.5 1/01

** OPTIONS

L = 2V Data Retention/Low Power

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

10

Austin Semiconductor, Inc.

ASI TO DSCC PART NUMBER

CROSS REFERENCE*

SRAM

MT5C2561

ASI Package Designator C

ASI Part # SMD Part #

MT5C2561C-35/883C 5962-8872501LX
MT5C2561C-45/883C 5962-8872502LX
MT5C2561C-55/883C 5962-8872503LX
MT5C2561C-70/883C 5962-8872504LX

MT5C2561C-35L883C 5962-8854401LX
MT5C2561C-45L883C 5962-8854402LX
MT5C2561C-55L883C 5962-8854403LX
MT5C2561C-70L883C 5962-8854404LX

ASI Package Designator EC

ASI Part # SMD Part #

MT5C2561EC-35/883C 5962-8872501XX
MT5C2561EC-45/883C 5962-8872502XX
MT5C2561EC-55/883C 5962-8872503XX
MT5C2561EC-70/883C 5962-8872504XX

MT5C2561EC-35L883C 5962-8854401XX
MT5C2561EC-45L883C 5962-8854402XX
MT5C2561EC-55L883C 5962-8854403XX
MT5C2561EC-70L883C 5962-8854404XX

* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.

MT5C2561

Rev. 2.5 1/01

11

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.