Datasheet MT5C1005F-20L-883C, MT5C1005ECW-70L-XT, MT5C1005ECW-40L-IT, MT5C1005ECW-40L-XT, MT5C1005ECW-55L-883C Datasheet (AUSTIN)

Austin Semiconductor, Inc.

SRAM

MT5C1005

256K x 4 SRAM

SRAM MEMORY ARRAY

AVAILABLE AS MILITARY
SPECIFICATIONS

•MIL-STD-883

FEATURES

• High Speed: 20, 25, 35, and 45

• Battery Backup: 2V data retention

• Low power standby

• High-performance, low-power CMOS double-metal
process

• Single +5V (+10%) Power Supply

• Easy memory expansion with CE\ and OE\ options.

• All inputs and outputs are TTL compatible

OPTIONS MARKING

• Timing

20ns access -20
25ns access -2 5
35ns access -3 5
45ns access -4 5
55ns access -55*
70ns access -70*

28-Pin DIP (C)

(400 MIL)

A7
A8

A9
A10
A11
A12
A13
A14
A15
A16
A17

CE\

OE\

Vss

32-Pin Flat Pack (F)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

A12
A10
A11
A13

NC
A14
A15
A16
A17

NC

CE\
OE\
Vss

A7
A8
A9

PIN ASSIGNMENT

(Top View)

1

28
2
3
4
5
6
7
8
9
10
11
12
13
14

Vcc

27

A6

26

A5

25

A4

24

A3

23

A2

22

A1

21

A0

20

NC

19

DQ4

18

DQ3

17

DQ2

16

DQ1

15

WE\

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

32-Pin LCC (EC)

32-Pin SOJ (DCJ)

A7
A8

A9
A12
A10
A11
A13

NC
A14
A15
A16
A17

NC

CE\

OE\

Vss

32-Pin LCC (ECW)

Vcc
A6
A5
A2
A4
A3
A1
NC
NC
A0
NC
DQ4
DQ3
DQ2
DQ1
WE\

A10
A11
A12
A13
A14
A15
A16
A17

CE\

5
6
7
8

9
10
11
12
13

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

4 3 2 1 31 32 30

14 15 16 17 18 19 20

NC

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

A9A8A7NCVccA6A5

DQ2

DQ1

WE\

Vss

OE\

DQ3

Vcc
A6
A5
A2
A4
A3
A1
NC
NC
A0
NC
DQ4
DQ3
DQ2
DQ1
WE\

29

A2

28

A4

27

A3

26

A1

25

A0

24

NC

23

NC

22

NC

21

DQ4

• Package(s)

Ceramic DIP (400 mil) C No. 109
Ceramic Quad LCC (contact factory)ECW No. 206
Ceramic LCC E C No. 207
Ceramic Flatpack F No. 303
Ceramic SOJ DC J No. 501

• Operating T emperature Ranges

Industrial (-40oC to +85oC) IT
Military (-55oC to +125oC) XT

• 2V data retention/low power L

*Electrical characteristics identical to those provided for the

45ns access devices.

For more products and information

please visit our web site at

www.austinsemiconductor .com

MT5C1005

Rev. 3.1 1/01

GENERAL DESCRIPTION

The Austin Semiconductor SRAM family employs
high-speed, low power CMOS designs fabricated using double­layer metal, double-layer polysilicon technology.

For flexibility in high-speed memory applications, ASI
offers chip enable (CE\) and output enable (OE\) capability.
These enhancements can place the outputs in High-Z for addi­tional flexibility in system design. Writing to these devices is
accomplished when write enable (WE\) and CE\ inputs are both
LOW . Reading is accomplished when WE\ remains HIGH while
CE\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.

All devices operation from a single +5V power supply
and all inputs and outputs are fully TTL compatible.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

1

SRAM

ROW DECODER

MT5C1005

Austin Semiconductor, Inc.

FUNCTIONAL BLOCK DIA GRAM

V

A
A
A

CC

GND

A
A
A
A
A
A
A

A A A A A A A A

262,144 x 4-BIT

MEMORY ARRAY

I/O CONTROL

COLUMN DECODER

POWER

DOWN

DQ4

DQ1

CE\

OE\
WE\

MT5C1005

Rev. 3.1 1/01

TRUTH TABLE

MODE OE\ CE\ WE\ DQ POWER

STANDBY X H X HIGH-Z STANDBY
READ L L H Q ACTIVE
READ H L H HIGH-Z ACTIVE
WRITE X L L D ACTIVE

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

2

Austin Semiconductor, Inc.

SRAM

MT5C1005

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage Range (Vcc)................................-.5V to +7.0V

Storage Temperature......................................-65°C to +150°C

Voltage on any Pin Relative to Vss................-.5V to Vcc+.5V

Max Junction T emperature............................................+175°C

Lead Temperature (soldering 10 seconds)..................+260oC

Power Dissipation ...............................................................1 W

*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability .

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS

(-55oC < TC < 125oC; VCC = 5V +10%)

DESCRIPTION CONDITIONS SYM MIN MAX UNITS NOTES

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage

Input Leakage Current

Output Leakage Current

Output High Voltage

Output Low Voltage

PARAMETER

0V<

VIN<V

CC

Output(s) disabled

0V<

V

OUT<VCC

I

= -4.0mA V

OH

I

= 8.0mA V

OL

CONDITIONS

V
V

IL

2.2

IH

-0.5 0.8 V 1

IL

-10 10 µA

IL

I

-10 10 µA

O

2.4 V 1

OH
OL

+0.5

V

CC

0.4 V 1

SYM -20 -25 -35 -45 UNITS NOTES

V1

MAX

Power Supply
Current: Operating

Power Supply
Current: Standby

* “L” version only.

WE\, CE\ <

Output Open

CE\ >

VIH; All Other Inputs

<

VIL or > VIH, VCC = MAX

V

CE\ >

CC

V

IL

V

> VCC -0.2V; f = 0 Hz*

IH

CAPACITANCE

PARAMETER CONDITIONS SYM MAX UNITS NOTES

Input Capacitance

Output Capacitance (DQ1-DQ4)

VIL; VCC = MAX

-0.2V; VCC = MAX

< VSS +0.2V

= 0V,

V

IN

T

= 25°C, f = 1MHz

A

= 5V

V

CC

I

cc

I

SBT2

I

SBC

180 180 180 180 mA 3

25 25 25 25 mA

16 16 16 16 mA

C

I

C

O

12 pF 4

14 pF 4

MT5C1005

Rev. 3.1 1/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

3

SRAM

MT5C1005

Austin Semiconductor, Inc.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Note 5) (-55oC < TC < 125oC; VCC = 5V +10%)

DESCRIPTION

READ CYCLE

READ cycle time
Address access time
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Chip Enable to power-up time
Chip disable to power-down time
Output Enable access time
Output Enable to output in Low-Z
Output disable to output in High-Z

WRITE CYCLE

WRITE cycle time
Chip Enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
Data setup time
Data hold time
Write disable to output in Low-Z
Write Enable to output in High-Z

SYMBOL

t

RC

t

AA

t

ACE

t

OH

t

LZCE

t

HZCE

t

PU

t

PD

t

AOE

t

LZOE

t

HZOE

t

WC

t

CW

t

AW

t

AS

t

AH

t

WP

t

DS

t

DH

t

LZWE

t

HZWE

-20

-25

-35 -45

MIN MAX MIN MAX M IN MAX M IN MAX UNITS NOTES

20 25 35 45 ns

20 25 35 45 ns

20 25 35 45 ns
3333 ns
3333 ns4, 6, 7

10 12 20 25 ns 4, 6, 7
0000 ns4

20 25 35 45 ns 4

8 102025ns

0000 ns4, 6, 7

8 10 20 25 ns 4, 6, 7

20 25 35 45 ns
15 20 30 35 ns
15 20 30 35 ns

0000 ns
0000 ns

15 20 30 35 ns
12 15 20 25 ns

0000 ns
3333 ns4, 6, 7
0 8 0 10 0 15 0 20 ns 4, 6, 7

MT5C1005

Rev. 3.1 1/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

4

Austin Semiconductor, Inc.

3

3

1234

1234

1234

1234

3

3

4

4

3

3

4

4

AC TEST CONDITIONS

Input pulse levels ................................... Vss to 3.0V

Input rise and fall times ....................................... 5ns

Input timing reference levels ............................. 1.5V

Output reference levels ..................................... 1.5V

Output load .............................. See Figures 1 and 2

SRAM

MT5C1005

167Ω

Q

VTH = 1.73V

Q

30pF

167Ω

VTH = 1.73V

5pF

Fig. 1 Output Load

Equivalent

NOTES

1 . All voltages referenced to VSS (GND).
2 . -3V for pulse width < 20ns

3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f = 1 Hz.

tRC (MIN)

4. This parameter is guaranteed but not tested.

5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.

6. Minimum of 5pF for t

and t

WHQX

.

EHQZ

, t

OHQZ

, t

ELQX

, t

OLQX

,

7. At any given temperature and voltage condition,

t

HZCE is less than tLZCE, and tHZWE is less than

t

LZWE and tHZOE is less than tLZOE.

8. WE\ is HIGH for READ cycle.

9. Device is continuously selected. Chip enables and
output enables are held in their active state.

10. Address valid prior to, or coincident with, latest
occurring chip enable.

11.tRC = Read Cycle Time.

12 . Chip enable (CE\) and write enable (WE\) can initiate and

terminate a WRITE cycle.

DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)

DESCRIPTION SYM MIN MAX UNITS NOTES

V

for Retention Data V

CC

CE\ >

Data Retention Current

V

Chip Deselect to Data
Retention Time

Operation Recovery Time

CONDITIONS

(VCC-0.2V)

and

> (VCC-0.2V)

IN

or <

0.2V

V

CC

= 2V I

DR

CCDR

t

CDR

t

R

2V

5mA

0--ns4

t

RC

ns 4, 11

Fig. 2 Output Load

Equivalent

LOW Vcc DA T A RETENTION WA VEFORM

V

CC

t

CDR

2

23

V

IH

2

CE\

MT5C1005

Rev. 3.1 1/01

23

V

IL

DA TA RETENTION MODE

4.5V

VDR > 2V

V

DR

5

4.5V

t

R

2

23

2

23

2

2

DON’T CARE
UNDEFINED

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

4

4

4

SRAM

MT5C1005

ADDRESS

DQ

PREVIOUS DATA VALID

READ CYCLE NO. 1

t

tRCtRC

RC

VALID

t

tAA

AA

t

OH

tOH

READ CYCLE NO. 2

8, 9

DATA VALID

7, 8, 10

CE\

OE\

DQ

Icc

MT5C1005

Rev. 3.1 1/01

t

LZCE

tLZCE

t

tPU

PU

t

LZOE

tLZOE

t

ACE

t

AOE

tAOE

t

tRCtRC

RC

t

HZOE

tHZOE

t

HZCE

tHZCEtACE

DATA VALID

t

tPD

PD

23

DON’T CARE

23

23

UNDEFINED

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

6

Austin Semiconductor, Inc.

4

4

5

5

1

7

1

1

3

SRAM

MT5C1005

ADDRESS

CE\

WE\

WRITE CYCLE NO. 1

12

(Chip Enabled Controlled)

t

WC

tWCtWC

t

tAW

AW

t

AS

D

t

CW

tCW

tCWtAS

t

tWP1tWP1

WP

t

DS

DATA VAILD

Q

HIGH Z

t

tAH

t

DH

tDHtDS

AH

WRITE CYCLE NO. 2

(Write Enabled Controlled)

ADDRESS

234567890123456

CE\

tAS

t

AS

WE\

D

Q

NOTE: Output enable (OE\) is inactive (HIGH).

t

AW

tAW

t

tWCtWC

WC

t

CW

tCW

tCW

t

tWP1tWP1

WP

HIGH-Z

7, 12

t

DS

DATA VALID

t

AH

tAH

234567890123456789012

t

DH

tDH

23

23

DON’T CARE

234

234

UNDEFINED

MT5C1005

Rev. 3.1 1/01

7

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Pin 1

SRAM

MT5C1005

Austin Semiconductor, Inc.

MECHANICAL DEFINITIONS*

ASI Case #109 (Package Designator C)

D

A

Q

L

e

E

E1

c

ASI PACKAGE SPECIFICATIONS

SYMBOL

MIN MAX

A 0.090 0.110
b 0.016 0.020

b1 0.040 0.060

c 0.008 0.012

D 1.386 1.414

E 0.385 0.405

E1 0.390 0.410

e 0.090 0.110
L 0.125 0.175

Q 0.040 0.060

b

b1

*All measurements are in inches.

MT5C1005

Rev. 3.1 1/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

8

Austin Semiconductor, Inc.

MECHANICAL DEFINITIONS*

ASI Case #206 (Package Designator ECW)

E1

SRAM

MT5C1005

D

E

D1

L

b1

b

ASI PACKAGE SPECIFICATIONS

SYMBOL

MIN MAX

A 0.077 0.093

b 0.022 0.028
b1 0.004 0.014
b2 0.054 0.066

D 0.742 0.758

D1 0.395 0.405

E 0.442 0.458

E1 0.295 0.305

e 0.045 0.055

L 0.045 0.055
L1 0.077 0.093

L1

e

A

b2

*All measurements are in inches.

MT5C1005

Rev. 3.1 1/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

9

Austin Semiconductor, Inc.

MECHANICAL DEFINITIONS*

ASI Case #207 (Package Designator EC)

L1

D

L

SRAM

MT5C1005

A

e

E

b

b1

b2

ASI PACKAGE SPECIFICATIONS

SYMBOL

MIN MAX

A 0.080 0.100

b 0.022 0.028
b1 0.004 0.014
b2 0.054 0.066

D 0.815 0.835
E 0.392 0.408

e 0.045 0.055

L 0.070 0.080
L1 0.090 0.110

*All measurements are in inches.

MT5C1005

Rev. 3.1 1/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

10

Austin Semiconductor, Inc.

MECHANICAL DEFINITIONS*

ASI Case #303 (Package Designator F)

SRAM

MT5C1005

L

E

Pin 1

e

b

D

D1

32

17 16

Index

1

Bottom View

T op View

c

E2

A

Q

*All measurements are in inches.

MT5C1005

Rev. 3.1 1/01

ASI PACKAGE SPECIFICATIONS

SYMBOL

MIN MAX

A --- 0.125

b 0.015 0.019
c 0.004 0.006

D 0.812 0.828
D1 0.745 0.755

E 0.405 0.415

E2 0.324 0.336

e 0.045 0.055
L 0.290 0.310

Q 0.027 0.033

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

11

SRAM

MT5C1005

Austin Semiconductor, Inc.

MECHANICAL DEFINITIONS*

ASI Case #501 (Package Designator DCJ)

A

e

b

A2

D1

E

D

R

E2

E1

ASI PACKAGE SPECIFICATIONS

SYMBOL

MIN MAX

A 0.135 0.153

A2 0.026 0.036

b 0.015 0.019

D 0.812 0.828

D1 0.740 0.755

E 0.405 0.415

e 0.045 0.055
E1 0.435 0.445
E2 0.360 0.380

R 0.030 0.040

*All measurements are in inches.

MT5C1005

Rev. 3.1 1/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

12

Austin Semiconductor, Inc.

MT5C1005EC-45/XT

MT5C1005DCJ-70/XT

yp

ORDERING INFORMA TION

SRAM

MT5C1005

EXAMPLE: MT5C1005C-20L/IT

Device

Number

MT5C1005 C -20 L /* MT5C1005

MT5C1005 C -25 L /* MT5C1005

MT5C1005 C -35 L /* MT5C1005

MT5C1005 C -40 L /* MT5C1005

MT5C1005 C -55 L /* MT5C1005

MT5C1005 C -70 L /* MT5C1005

Package

Type

Speed

ns

Options** Process

EXAMPLE: MT5C1005F-25L/883C

Device

Number

MT5C1005 F -20 L /* MT5C1005 DCJ -20 L /*
MT5C1005 F -25 L /* MT5C1005 DCJ -25 L /*
MT5C1005 F -35 L /* MT5C1005 DCJ -35 L /*
MT5C1005 F -40 L /* MT5C1005 DCJ -40 L /*
MT5C1005 F -55 L /* MT5C1005 DCJ -55 L /*
MT5C1005 F -70 L /* MT5C1005 DCJ -70 L /*

Package

T

e

Speed

ns

Options** Process

EXAMPLE:

Device

Number

Package

EXAMPLE:

Device

Number

Package

Type

EC

ECW

EC

ECW

EC

ECW

EC

ECW

EC

ECW

EC

ECW

Type

Speed

Speed

Options** Process

ns

-20 L /*

-25 L /*

-35 L /*

-40 L /*

-55 L /*

-70 L /*

Options** Process

ns

MT5C1005

Rev. 3.1 1/01

*AVAILABLE PROCESSES

IT = Industrial T emperature Range -40oC to +85oC
XT = Extended T emperature Range -55oC to +125oC
883C = Full Military Processing -55oC to +125oC

** OPTIONS

L = 2V Data Retention/Low Power

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

13