Datasheet MT5C1001F-70L-XT, MT5C1001F-70L-883C, MT5C1001F-55L-IT, MT5C1001F-55L-XT, MT5C1001F-35L-883C Datasheet (AUSTIN)
...Page 1
SRAM
MT5C1001
Austin Semiconductor, Inc.
1M x 1 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-92316
• MIL-STD-883
FEATURES
• High Speed: 20, 25, 35, and 45
• Battery Backup: 2V data retention
• Low power standby
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\ and OE\ options.
• All inputs and outputs are TTL compatible
• Three-state output
OPTIONS MARKING
• Timing
20ns access -20
25ns access -2 5
35ns access -3 5
45ns access -4 5
55ns access -55*
70ns access -70*
• Package(s)
Ceramic DIP (400 mil) C No. 109
Ceramic LCC EC No. 207
Ceramic Flatpack F No. 303
Ceramic SOJ DCJ No. 501
• Operating T emperature Ranges
Industrial (-40oC to +85oC) IT
Military (-55oC to +125oC) XT
• 2V data retention/low power L
*Electrical characteristics identical to those provided for the
45ns access devices.
For more products and information
please visit our web site at
www.austinsemiconductor .com
Limited Availability
PIN ASSIGNMENT
(Top View)
28-Pin DIP (C)
(400 MIL)
1
A10
A11
A12
A13
A14
A15
NC
A16
A17
A18
A19
WE\
Vss
Q
28
2
3
4
5
6
7
8
9
10
11
12
13
14
Vcc
27
A9
26
A8
25
A7
24
A6
23
A5
22
A4
21
NC
20
A3
19
A2
18
A1
17
A0
16
D
15
CE\
32-Pin Flat Pack (F)
A10
A11
A12
NC
A13
A14
A15
NC
A16
A17
A18
A19
NC
WE\
Vss
Q
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GENERAL DESCRIPTION
The MT5C1001 employs low power, high-performance
silicon-gate CMOS technology. Static design eliminates the
need for external clocks or timing strobes while CMOS circuitry
reduces power consumption and provides for greater
reliability.
For flexibility in high-speed memory applications, ASI
offers chip enable (CE\) and output enable (OE\) capability.
These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is
accomplished when write enable (WE|) and CE\ inputs are both
LOW . Reading is accomplished when WE\ remains HIGH while
CE\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
The “L” version provides an approximate 50 percent
reduction in CMOS standby current (I
version.
All devices operation from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
A10
1
2
A11
3
A12
NC
4
5
A13
6
A14
A15
7
8
NC
9
A16
A17
10
11
A18
12
A19
NC
13
14
Q
15
WE\
Vss
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
NC
A9
A8
A7
A6
A5
A4
A3
NC
A2
NC
A1
A0
D
CE\
) over the standard
SBC2
32
Vcc
31
NC
30
A9
29
A8
28
A7
27
A6
26
A5
25
A4
24
A3
23
NC
22
A2
21
NC
20
A1
19
A0
18
D
17
CE\
MT5C1001
Rev. 2.0 2/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
Page 2
SRAM
ROW DECODER
Q
PIN
ASSIGNMENT
MT5C1001
Austin Semiconductor, Inc.
Limited Availability
FUNCTIONAL BLOCK DIA GRAM
V
CC
A
6
A
5
A
4
A
3
A
15
A
14
A
13
A
8
A
7
1,048,576-BIT
MEMORY ARRAY
512 rows x 2048
columns
Vss
D
CE\
I/O CONTROL
WE\
POWER
DOWN
COLUMN DECODER
A2 A1 A
A17 A18 A
16 A0
19 A10 A9 A12 A11
TRUTH TABLE
MODE CE\ WE\ OUTPUT POWER
STANDBY H X HIGH-Z STANDBY
READ L H Q ACTIVE
WRITE L L HIGH-Z ACTIVE
PIN ASSIGNMENTS
A0-A
19
WE\ Write Enable
CE\ Chip Enable
D Data Input
Q Data Output
NC No Connection
V
CC
V
SS
Address Inputs
+5V Power Supply
Ground
MT5C1001
Rev. 2.0 2/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
Page 3
SRAM
MT5C1001
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RA TINGS*
V oltage on Any Input Relative to Vss................................-.5V to +7V
V oltage on Vcc Supply Relative to Vss...............................-.5V to +7V
V oltage Applied to Q............................................................-.5V to +6V
Storage Temperature......................................................-65oC to +150oC
Power Dissipation..............................................................................1W
Short Circuit Output Current.........................................................20mA
Lead T emperature (soldering 10 seconds)....................................+260oC
Junction Temperature..................................................................+175oC
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability .
Limited Availability
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TC < 125oC; VCC = 5V +10%)
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
0V ≤ V
≤ VCC IL
IN
Output(s) disabled
V
0V <
I
< VCC
OUT
= -4.0mA V
OH
= 8.0mA V
I
OL
V
IL
V
IH
IL
I
O
OH
OL
2.2 VCC+0.5 V 1
-0.5 0.8 V 1, 2
-5 5
-5 5
µA
µA
2.4 V 1
0.4 V 1
MAX
PARAMETER
Power Supply
Current: Operating
Power Supply
Current: Standby
CONDITIONS
CE\ <
VIL; VCC = MAX
f = MAX = 1/t
(MIN)
RC
Output Open
CE\ >
VIH; VCC = MAX
f = MAX = 1/t
(MIN)
RC
Output Open
VIH; All Other Inputs
CE\ >
VIH or > VIH, VCC = MAX
<
SYM -20 -25 -35 -45 UNITS NOTES
I
cc
I
SBT1
I
SBT2
125 120 115 110 mA 3
50 45 40 35 mA
25 25 25 25 mA
f = 0 Hz
CE\ >
V
-0.2V; VCC = MAX
CC
V
< VSS +0.2V
IL
> VCC -0.2V; f = 0 Hz
V
IH
"L" Version Only
I
SBC2
I
SBC2
10 10 10 10 mA
5555mA
CAPACITANCE
PARAMETER CONDITIONS SYMBOL MAXIMUM UNITS NOTES
Input Capacitance (A3-A5, A15 -A17)
= 25oC, f = 1MHz
T
Output Capactiance (Q) Co 8 pF 4
Input Capacitance: (All Other Input
s) C
A
V
= 5V
CC
C
I
I
10 pF 4
8pF
4
MT5C1001
Rev. 2.0 2/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
Page 4
SRAM
MT5C1001
Austin Semiconductor, Inc.
Limited Availability
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55oC < TC < 125oC; VCC = 5V +10%)
DESCRIPTION
READ CYCLE
READ cycle time
Address access time
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Chip Enable to power-up time
Chip disable to power-down time
WRITE CYCLE
WRITE cycle time
Chip Enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
Data setup time
Data hold time
Write disable to output in Low-Z
Write Enable to output in High-Z
SYMBOL
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP
t
DS
t
DH
t
LZWE
t
HZWE
-20
-25
MIN MAX MIN MAX M IN MAX M IN MAX UNITS NOTES
20 25 35 45 ns
20 25 35 45 ns
20 25 35 45 ns
3333 ns
3333 ns4, 6, 7
8 10 15 15 ns 4, 6, 7
0000 ns4
20 25 35 45 ns 4
20 25 35 45 ns
15 16 20 25 ns
15 16 20 25 ns
0000 ns
1111 ns
15 16 20 25 ns
8 101315 ns
0000 ns
3333 ns7
0 9 010013013 ns4, 6, 7
-35 -45
MT5C1001
Rev. 2.0 2/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
Page 5
SRAM
3
3
1234
1234
1234
1234
3
3
4
4
3
3
4
4
MT5C1001
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
NOTES
1 . All voltages referenced to VSS (GND).
2 . -3V for pulse width < 20ns
3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f = 1 Hz.
tRC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. t
, t
, t
LZCE
LZWE
LZOE
, t
HZCE
, t
HZOE
and t
HZWE
are
specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
Limited Availability
167Ω
Q
VTH = 1.73V
Q
30pF
Fig. 1 Output Load
Equivalent
allowing for actual tester RC time constant.
7. At any given temperature and voltage condition,
t
is less than t
HZCE
t
is less than t
HZOE
LZCE
LZOE
, and t
.
HZWE
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
12 . Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
167Ω
VTH = 1.73V
5pF
Fig. 2 Output Load
Equivalent
is less than t
LZWE
and
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION SYMBOL MIN MAX UNITS NOTES
for Retention Data V
V
CC
CE\ >
Data Retention Current
and
V
Chip Deselect to Data
Retention Time
Operation Recovery Time
CONDITIONS
(VCC - 0.2V)
> (VCC - 0.2V)
IN
or <
0.2V
DR
V
= 2V I
CC
V
= 3V 1.5 mA
CC
CCDR
t
CDR
2--V
1.0 mA
0
--
t
R
t
RC
ns 4
ns
LOW Vcc DA T A RETENTION WA VEFORM
DA TA RETENTION MODE
4.5V
VDR > 2V
V
DR
5
4.5V
t
R
2
23
2
23
2
2
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C1001
Rev. 2.0 2/00
V
CE\
CC
t
CDR
2
23
V
IH
2
23
V
IL
4, 11
DON’T CARE
UNDEFINED
Page 6
SRAM
MT5C1001
ADDRESS
DQ
Austin Semiconductor, Inc.
READ CYCLE NO. 1
t
tRCtRC
RC
VALID
t
tAA
AA
t
OH
tOH
PREVIOUS DATA VALID
Limited Availability
8, 9
DATA VALID
CE\
DQ
Icc
MT5C1001
Rev. 2.0 2/00
t
LZCE
tLZCE
t
tPU
PU
READ CYCLE NO. 2
t
tRCtRC
RC
t
ACE
6
7, 8, 10
t
HZCE
tHZCEtACE
DATA VALID
t
PD
tPD
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Page 7
SRAM
1
1
1
6
6
6
6
7
3
1234
1234
1234
1234
MT5C1001
ADDRESS
CE\
WE\
Austin Semiconductor, Inc.
WRITE CYCLE NO. 1
Limited Availability
12
(Chip Enabled Controlled)
t
WC
tWCtWC
t
tAW
AW
t
AS
D
t
CW
tCW
tCWtAS
t
tWP1tWP1
WP
t
DS
DATA VAILD
Q
HIGH Z
t
tAH
t
DH
tDHtDS
AH
WRITE CYCLE NO. 2
(Write Enabled Controlled)
ADDRESS
234567890123456
CE\
t
tAS
AS
WE\
D
23456789012345
23456789012345
Q
NOTE: Output enable (OE\) is inactive (HIGH).
t
HZWE
t
AW
tAW
t
tWCtWC
WC
t
CW
tCW
tCW
t
tWP1tWP1
WP
HIGH-Z
7, 12
t
DS
DATA VALID
t
AH
tAH
234567890123456789012
t
DH
tDH
t
LZWE
23
DON’T CARE
2345
2345
UNDEFINED
MT5C1001
Rev. 2.0 2/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
Page 8
SRAM
MT5C1001
Pin 1
Austin Semiconductor, Inc.
Limited Availability
MECHANICAL DEFINITIONS*
ASI Case #109 (Package Designator C)
SMD #5962-92316, Case Outline T
D
A
e
E
Q
L
b
b1
NOTE
0o to 15
o
E1
c
SMD SPECIFICATIONS
SYMBOL
MIN MAX
A 0.075 0.095
b 0.016 0.020
b1 0.040 0.060
c 0.008 0.012
D 1.386 1.414
E 0.385 0.405
E1 0.390 0.410
e
0.100 BSC
L 0.125 0.175
Q 0.040 0.060
NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.
*All measurements are in inches.
MT5C1001
Rev. 2.0 2/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
Page 9
SRAM
MT5C1001
Austin Semiconductor, Inc.
Limited Availability
MECHANICAL DEFINITIONS*
ASI Case #207 (Package Designator EC)
SMD# 5962-92316, Case Outline Y
D1
D
L1
A
L
e
E
b
b1
SMD SPECIFICATIONS
SYMBOL
MIN MAX
A 0.080 0.100
b 0.022 0.028
b1 0.004 0.014
b2 0.054 0.066
D 0.815 0.835
D1 0.740 0.760
E 0.392 0.408
e
0.050 BSC
L 0.070 0.080
L1 0.090 0.110
NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.
b2
*All measurements are in inches.
MT5C1001
Rev. 2.0 2/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
Page 10
SRAM
MT5C1001
Austin Semiconductor, Inc.
Limited Availability
MECHANICAL DEFINITIONS*
ASI Case #303 (Packag e Designator F)
SMD #5962-92316, Case Outline Z
L
E1
Pin 1
e
b
D
D1
32
17 16
Index
1
Bottom View
T op View
c
E
SMD SPECIFICATIONS
SYMBOL
MIN MAX
A 0.097 0.117
b 0.015 0.019
c 0.004 0.006
D 0.812 0.828
D1 0.745 0.755
E 0.324 0.336
E1 0.405 0.415
e
0.050 BSC
L 0.290 0.310
Q 0.032 0.038
NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.
A
Q
*All measurements are in inches.
MT5C1001
Rev. 2.0 2/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
Page 11
SRAM
MT5C1001
Austin Semiconductor, Inc.
Limited Availability
MECHANICAL DEFINITIONS*
ASI Case #501 (Package Designator DCJ)
SMD #5962-92316, Case Outline U
A
e
b
D1
D
B1
E2
E1
A2
E
SMD SPECIFICATIONS
SYMBOL
MIN MAX
A 0.135 0.153
A2 0.026 0.036
B1 0.030 0.040
b 0.015 0.019
D 0.812 0.828
D1 0.745 0.760
E 0.405 0.415
E1 0.435 0.445
E2 0.360 0.380
e
0.050 BSC
NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.
*All measurements are in inches.
MT5C1001
Rev. 2.0 2/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11
Page 12
SRAM
MT5C1001EC-45/XT
MT5C1001DCJ-70/XT
Package
Type
Device
Number
yp
Speed
ns
MT5C1001
Austin Semiconductor, Inc.
Limited Availability
ORDERING INFORMA TION
EXAMPLE: MT5C1001C-20L/IT
Device
Number
MT5C1001 C -20 L /* MT5C1001 EC -20 L /*
MT5C1001 C -25 L /* MT5C1001 EC -25 L /*
MT5C1001 C -35 L /* MT5C1001 EC -35 L /*
MT5C1001 C -40 L /* MT5C1001 EC -40 L /*
MT5C1001 C -55 L /* MT5C1001 EC -55 L /*
MT5C1001 C -70 L /* MT5C1001 EC -70 L /*
Package
Type
Speed
ns
Options** Process
EXAMPLE: MT5C1001F-25L/883C
Device
Number
MT5C1001 F -20 L /* MT5C1001 DCJ -20 L /*
MT5C1001 F -25 L /* MT5C1001 DCJ -25 L /*
MT5C1001 F -35 L /* MT5C1001 DCJ -35 L /*
MT5C1001 F -40 L /* MT5C1001 DCJ -40 L /*
MT5C1001 F -55 L /* MT5C1001 DCJ -55 L /*
MT5C1001 F -70 L /* MT5C1001 DCJ -70 L /*
Speed
Options** Process
ns
EXAMPLE:
Device
Number
Package
Type
EXAMPLE:
Package
e
T
Speed
ns
Options** Process
Options** Process
MT5C1001
Rev. 2.0 2/00
*AVAILABLE PROCESSES
IT = Industrial T emperature Range -40oC to +85oC
XT = Extended T emperature Range -55oC to +125oC
883C = Full Military Processing -55oC to +125oC
** OPTIONS
L = 2V Data Retention/Low Power
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
Page 13
SRAM
MT5C1001
Austin Semiconductor, Inc.
ASI T O DSCC P AR T NUMBER
CROSS REFERENCE*
ASI Package Designator C
ASI Part # SMD Part #
MT5C1001C-20L/883C 5962-9231608MT A
MT5C1001C-20/883C 5962-9231604MT A
MT5C1001C-25L/883C 5962-9231607MT A
MT5C1001C-25/883C 5962-9231603MT A
MT5C1001C-35L/883C 5962-9231606MT A
MT5C1001C-35/883C 5962-9231602MT A
MT5C1001C-45L/883C 5962-9231605MT A
MT5C1001C-45/883C 5962-9231601MT A
Limited Availability
ASI Package Designator EC
ASI Part # SMD Part #
MT5C1001EC-20L/883C 5962-9231608MY A
MT5C1001EC-20/883C 5962-9231604MY A
MT5C1001EC-25L/883C 5962-9231607MY A
MT5C1001EC-25/883C 5962-9231603MY A
MT5C1001EC-35L/883C 5962-9231606MY A
MT5C1001EC-35/883C 5962-9231602MY A
MT5C1001EC-45L/883C 5962-9231605MY A
MT5C1001EC-45/883C 5962-9231601MY A
ASI Package Designator F
ASI Part # SMD Part #
MT5C1001F-20L/883C 5962-9231608MZA
MT5C1001F-20/883C 5962-9231604MZA
MT5C1001F-25L/883C 5962-9231607MZA
MT5C1001F-25/883C 5962-9231603MZA
MT5C1001F-35L/883C 5962-9231606MZA
MT5C1001F-35/883C 5962-9231602MZA
MT5C1001F-45L/883C 5962-9231605MZA
MT5C1001F-45/883C 5962-9231601MZA
ASI Package Designator DCJ
ASI Part # SMD Part #
MT5C1001DCJ-20L/883C 5962-9231608MUA
MT5C1001DCJ-20/883C 5962-9231604MUA
MT5C1001DCJ-25L/883C 5962-9231607MUA
MT5C1001DCJ-25/883C 5962-9231603MUA
MT5C1001DCJ-35L/883C 5962-9231606MUA
MT5C1001DCJ-35/883C 5962-9231602MUA
MT5C1001DCJ-45L/883C 5962-9231605MUA
MT5C1001DCJ-45/883C 5962-9231601MUA
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
MT5C1001
Rev. 2.0 2/00
13
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Loading...