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MT55L512L12PT-6
Datasheet (MICRON)
25 pgs400.62 Kb0

Datasheet MT55L512L12PT-10, MT55L256V36PT-6IT, MT55L256V36PT-7.5, MT55L256V36PT-7.5IT, MT55L512L12PF-10 Datasheet (MICRON)

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Page 1
1
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. MT55L512L18P_C.p65 – Rev. 2/02 ©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
8Mb ZBT® SRAM
FEATURES
• High frequency and 100 percent bus utilization
• Fast cycle times: 6ns, 7.5ns and 10ns
• Single +3.3V ±5% power supply (V
DD)
• Separate +3.3V or +2.5V isolated output buffer supply (VDDQ)
• Advanced control logic for minimum control signal interface
• Individual BYTE WRITE controls may be tied LOW
• Single R/W# (read/write) control pin
• CKE# pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• Clock-controlled and registered addresses, data I/Os and control signals
• Internally self-timed, fully coherent WRITE
• Internally self-timed, registered outputs to eliminate the need to control OE#
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Linear or Interleaved Burst Modes
• Burst feature (optional)
• Pin/function compatibility with 2Mb, 4Mb, and 18Mb ZBT SRAM
• Automatic power-down
• 100-pin TQFP package
• 165-pin FBGA package
OPTIONS MARKING
• Timing (Access/Cycle/MHz)
3.5ns/6ns/166 MHz -6
4.2ns/7.5ns/133 MHz -7.5 5ns/10ns/100 MHz -10
• Configurations
3.3V I/O
512K x 18 MT55L512L18P 256K x 32 MT55L256L32P 256K x 36 MT55L256L36P
2.5V I/O
512K x 18 MT55L512V18P 256K x 32 MT55L256V32P 256K x 36 MT55L256V36P
• Package 100-pin TQFP T 165-pin, 13mm x 15mm FBGA F*
• Operating Temperature Range Commercial (0ºC to +70ºC) None Industrial (-40°C to +85°C)** IT
Part Number Example:
MT55L256L32PT-7.5
MT55L512L18P, MT55L512V18P, MT55L256L32P, MT55L256V32P, MT55L256L36P, MT55L256V36P
3.3V VDD, 3.3V or 2.5V I/O
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/support/index.html.
** Industrial temperature range offered in specific speed grades and
configurations. Contact factory for more information.
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).
100-Pin TQFP
1
165-Pin FBGA
GENERAL DESCRIPTION
The Micron® Zero Bus Turnaround™ (ZBT®) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.
Micron’s 8Mb ZBT SRAMs integrate a 512K x 18, 256K x 32, or 256K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization, eliminating any turnaround cycles for READ to WRITE, or WRITE to READ, transitions. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, chip enable (CE#), two additional chip enables for easy depth expansion (CE2, CE2#), cycle start input
Page 2
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8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. MT55L512L18P_C.p65 – Rev. 2/02 ©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
36 36 36 36 36
K
MODE
18
BWa# BWb# BWc# BWd#
R/W#
CE# CE2
CE2#
OE#
READ LOGIC
DQs DQPa DQPb DQPc DQPd
D A T A
S T E E R
I N G
O U T P U T
B U F F E R S
256K x 8 x 4
(x32)
256K x 9 x 4
(x36)
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
18
18
16 18
BURST LOGIC
SA0'
SA1'
D1D0Q1
Q0
SA0
SA1
K
18
ADV/LD#
ADV/LD#
E
INPUT
REGISTER 1
S E N S E
A
M
P S
O U T P U T
R E G
I S T E R S
E
CLK
CKE#
WRITE
DRIVERS
SA0, SA1, SA
36
36
36
NOTE: Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions, and timing diagrams
for detailed information.
FUNCTIONAL BLOCK DIAGRAM
256K x 32/36
FUNCTIONAL BLOCK DIAGRAM
512K x 18
18 18 18 18
SA0, SA1, SA
K
MODE
19
BWa#
BWb#
R/W#
CE# CE2
CE2#
OE#
READ LOGIC
DQs
D A T A
S T E E R
I N G
O U T P U T
B U F F E R S
512K x 9 x 2
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
19
19
17 19
BURST LOGIC
SA0'
SA1'
D1D0Q1
Q0
SA0
SA1
K
19
ADV/LD#
ADV/LD#
E
INPUT
REGISTER 1
S E
N
S E
A M
P S
O U T P U T
R E G
I S T E R S
E
CLK
CKE#
WRITE
DRIVERS
1818
18
18
18
Page 3
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8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. MT55L512L18P_C.p65 – Rev. 2/02 ©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
GENERAL DESCRIPTION (continued)
(ADV/LD#), synchronous clock enable (CKE#), byte write enables (BWa#, BWb#, BWc#, and BWd#), and read/write (R/W#).
Asynchronous inputs include the output enable (OE#, which may be tied LOW for control signal mini­mization), clock (CLK), and snooze enable (ZZ, which may be tied LOW if unused). There is also a burst mode pin (MODE) that selects between interleaved and linear burst modes. MODE may be tied HIGH, LOW, or left unconnected if burst is unused. The data-out (Q), enabled by OE#, is registered by the rising edge of CLK. WRITE cycles can be from one to four bytes wide as controlled by the write control inputs.
All READ, WRITE, and DESELECT cycles are initi­ated by the ADV/LD# input. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV/LD#). Use of burst mode is optional. It is allowable to give an address for each individual READ and WRITE cycle. BURST cycles wrap around after the fourth access from a base address.
To allow for continuous, 100 percent use of the data bus, the pipelined ZBT SRAM uses a LATE LATE WRITE cycle. For example, if a WRITE cycle begins in clock cycle one, the address is present on rising edge one. BYTE WRITEs need to be asserted on the same cycle as the address. The data associated with the address is required two cycles later, or on the rising edge of clock cycle three.
Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During a BYTE WRITE cycle, BWa# controls DQa pins; BWb# controls DQb pins; BWc# controls DQc pins; and BWd# controls DQd pins. Cycle types can only be defined when an address is loaded, i.e., when ADV/LD# is LOW. Parity/ECC bits are only available on the x36 version.
Micron’s 8Mb ZBT SRAMs operate from a +3.3V VDD power supply, and all inputs and outputs are LVTTL­compatible. Users can choose either a 2.5V or 3.3V I/O version. The device is ideally suited for systems requir­ing high bandwidth and zero bus turnaround delays.
Please refer to Micron’s Web site (www.micron.com/
sramds) for the latest data sheet.
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8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. MT55L512L18P_C.p65 – Rev. 2/02 ©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
PIN # x18 x32 x36
51 NC NF DQPa 52 NC DQa DQa 53 NC DQa DQa 54 VDDQ 55 VSS 56 NC DQa DQa 57 NC DQa DQa 58 DQa 59 DQa 60 VSS 61 VDDQ 62 DQa 63 DQa 64 ZZ 65 VDD 66 VDD
1
67 VSS 68 DQa DQb DQb 69 DQa DQb DQb 70 VDDQ 71 VSS 72 DQa DQb DQb 73 DQa DQb DQb 74 DQa DQb DQb 75 NC DQb DQb
PIN # x18 x32 x36
76 VSS 77 VDDQ 78 NC DQb DQb 79 NC DQb DQb 80 SA NF DQPb 81 SA 82 SA 83 SA 84 NF
2
85 ADV/LD# 86 OE# (G#) 87 CKE# 88 R/W# 89 CLK 90 VSS 91 VDD 92 CE2# 93 BWa# 94 BWb# 95 NC BWc# BWc# 96 NC BWd# BWd# 97 CE2 98 CE# 99 SA
100 SA
PIN # x18 x32 x36
TQFP PIN ASSIGNMENT TABLE
26 VSS 27 VDDQ 28 NC DQd DQd 29 NC DQd DQd 30 NC NF DQPd 31 MODE (LBO#) 32 SA 33 SA 34 SA 35 SA 36 SA1 37 SA0 38 DNU 39 DNU 40 VSS 41 VDD 42 DNU 43 DNU 44 SA 45 SA 46 SA 47 SA 48 SA 49 SA 50 SA
PIN # x18 x32 x36
1NCNFDQPc 2NCDQc DQc 3NCDQc DQc 4VDDQ 5VSS 6NCDQc DQc 7NCDQc DQc 8 DQb DQc DQc
9 DQb DQc DQc 10 VSS 11 VDDQ 12 DQb DQc DQc 13 DQb DQc DQc 14 VDD 15 VDD 16 VDD
1
17 VSS 18 DQb DQd DQd 19 DQb DQd DQd 20 VDDQ 21 VSS 22 DQb DQd DQd 23 DQb DQd DQd 24 DQb DQd DQd 25 NC DQd DQd
NOTE: 1. Pins 16 and 66 do not have to be connected directly to V
DD if the input voltage is ≥ VIH.
2. Pin 84 is reserved for expansion to 18Mb device.
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8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. MT55L512L18P_C.p65 – Rev. 2/02 ©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
PIN ASSIGNMENT (TOP VIEW)
100-PIN TQFP
SA SA SA
NF
2
ADV/LD# OE# (G#)
CKE# R/W#
CLK
V
SS
V
DD
CE2# BWa# BWb#
NC
NC CE2 CE#
SA SA
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SANCNC
V
DD
Q
V
SS
NC
DQa
DQa
DQa
VSSV
DD
Q
DQa
DQa
V
SSVDD
1
VDDZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQaNCNC
VSSV
DD
Q
NCNCNC
SA SA SA SA SA SA SA
DNU DNU V
DD
V
SS
DNU DNU
SA0 SA1 SA SA SA SA
MODE (LBO#)
NCNCNC
V
DD
Q
V
SS
NC
NC
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
DDVDD
V
DD
1
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
NC
V
SS
V
DD
Q
NCNCNC
x18
SA SA SA
NF
2
ADV/LD# OE# (G#)
CKE# R/W#
CLK
V
SS
V
DD
CE2#
BWa# BWb#
BWc#
BWd#
CE2 CE#
SA SA
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NF/DQPb3DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
DQb
VSSV
DD
Q
DQb
DQb
V
SSVDD
1
VDDZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
DQa
DQa
VSSV
DD
Q
DQa
DQa
NF/DQPa
3
SA SA SA SA SA SA SA
DNU DNU V
DD
V
SS
DNU DNU
SA0 SA1 SA SA SA SA
MODE (LBO#)
NF/DQPc
3
DQc
DQc
V
DD
Q
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DD
Q
DQc
DQc
V
DDVDD
V
DD
1
V
SS
DQd
DQd
V
DD
Q
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DD
Q
DQd
DQd
NF/DQPd
3
x32/x36
NOTE: 1. Pins 16 and 66 do not have to be connected directly to VDD if the input voltage is ≥ VIH.
2. Pin 84 is reserved for expansion to 18Mb device.
3. NF for x32 version, DQPx for x36 version.
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8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. MT55L512L18P_C.p65 – Rev. 2/02 ©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
TQFP PIN DESCRIPTIONS
x18 x32/x36 SYMBOL TYPE DESCRIPTION
37 37 SA0 Input Synchronous Address Inputs: These inputs are registered 36 36 SA1 and must meet the setup and hold times around the rising
32-35, 44-50, 32-35, 44-50, SA edge of CLK. Pin 84 is reserved as an address bit for
80-83, 99, 100 81-83, 99, 100 higher-density 18Mb ZBT SRAMs. SA0 and SA1 are the
two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
93 93 BWa# Input Synchronous Byte Write Enables: These active LOW inputs 94 94 BWb# allow individual bytes to be written when a WRITE cycle is
– 95 BWc# active and must meet the setup and hold times around the – 96 BWd# rising edge of CLK. BYTE WRITEs need to be asserted on
the same cycle as the address. BWs are associated with addresses and apply to subsequent data. BWa# controls DQa pins; BWb# controls DQb pins; BWc# controls DQc pins; BWd# controls DQd pins.
89 89 CLK Input Clock: This signal registers the address, data, chip enables,
byte write enables, and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock’s rising edge.
98 98 CE# Input Synchronous Chip Enable: This active LOW input is used to
enable the device and is sampled only when a new external address is loaded (ADV/LD# is LOW).
92 92 CE2# Input Synchronous Chip Enable: This active LOW input is used to
enable the device and is sampled only when a new external address is loaded (ADV/LD# is LOW). This input can be used for memory depth expansion.
97 97 CE2 Input Synchronous Chip Enable: This active HIGH input is used to
enable the device and is sampled only when a new external address is loaded (ADV/LD# is LOW). This input can be used for memory depth expansion.
86 86 OE# Input Output Enable: This active LOW, asynchronous input
(G#) enables the data I/O output drivers. G# is the JEDEC-
standard term for OE#.
85 85 ADV/LD# Input Synchronous Address Advance/Load: When HIGH, this
input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When ADV/LD# is HIGH, R/W# is ignored. A LOW on ADV/LD# clocks a new address at the CLK rising edge.
87 87 CKE# Input Synchronous Clock Enable: This active LOW input permits
CLK to propagate throughout the device. When CKE# is HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet setup and hold times around the rising edge of CLK.
64 64 ZZ Input Snooze Enable: This active HIGH, asynchronous input
causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored.
(continued on next page)
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8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. MT55L512L18P_C.p65 – Rev. 2/02 ©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
TQFP PIN DESCRIPTIONS (CONTINUED)
x18 x32/x36 SYMBOL TYPE DESCRIPTION
88 88 R/W# Input Read/Write: This input determines the cycle type when
ADV/LD# is LOW and is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Full bus-width WRITEs occur if all byte write enables are LOW.
31 31 MODE Input Mode: This input selects the burst sequence. A LOW on
(LBO#) this pin selects linear burst. NC or HIGH on this pin selects
interleaved burst. Do not alter input state while device is operating. LBO# is the JEDEC-standard term for MODE.
(a) 58, 59, 62, 63, (a) 52, 53, 56-59, DQa Input/ SRAM Data I/Os: Byte “a” is associated with DQa pins;
68, 69, 72-74 62, 63 Output Byte “b” is associated with DQb pins; Byte “c” is
(b) 8, 9, 12, 13, (b) 68, 69, 72-75, DQb associated with DQc pins; Byte “d” is associated with
18, 19, 22-24 78, 79 DQd pins. Input data must meet setup and hold times
(c) 2, 3, 6-9, DQc around the rising edge of CLK.
12, 13
(d) 18, 19, 22-25, DQd
28, 29
n/a 51 NF/DQPa NF/ No Function/Data Bits: On the x32 version, these pins are
80 NF/DQPb I/O No Function (NF) and can be left floating or connected to
1 NF/DQPc GND to minimize thermal impedance. On the x36 version,
30 NF/DQPd these bits are DQPs.
14, 15, 16, 41, 65, 14, 15, 16, 41, 65, V
DD
Supply Power Supply: See DC Electrical Characteristics and
66, 91 66, 91 Operating Conditions for range.
4, 11, 20, 27, 4, 11, 20, 27, VDDQ Supply Isolated Output Buffer Supply: See DC Electrical
54, 61, 70, 77 54, 61, 70, 77 Characteristics and Operating Conditions for range.
5, 10, 17, 21, 5, 10, 17, 21, V
SS
Supply Ground: GND.
26, 40, 55, 60, 26, 40, 55, 60,
67, 71, 76, 90 67, 71, 76, 90
1-3, 6, 7, 25, n/a NC – No Connect: These pins can be left floating or connected
28-30, 51-53, 56, to GND to minimize thermal impedance.
57, 75, 78, 79,
95, 96
38, 39, 42, 43 38, 39, 42, 43 DNU – Do Not Use: These signals may either be unconnected or
wired to GND to minimize thermal impedance.
84 84 NF – No Function: This pin is internally connected to the die and
will have the capacitance of an input pin. It is allowable to leave this pin unconnected or driven by signals. Pin 84 is reserved as an address pin for the 18Mb ZBT SRAM.
Page 8
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8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. MT55L512L18P_C.p65 – Rev. 2/02 ©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
PIN LAYOUT (TOP VIEW)
165-PIN FBGA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
CE#
CE2
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
SA
SA
SA
SA
NC
DQb
DQb
DQb
DQb
V
DD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
DD
DQb
DQb
DQb
DQb
NF/DQPb
NC
MODE
(LBO#)
BWb#
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
SA
SA
NC
BWa#
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
DNU
DNU
CE2#
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
SA1
SA0
CKE#
R/W#
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
DNU
DNU
ADV/L D#
OE# (G#)
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
SA
SA
SA
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
SA
SA
SA
SA
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
SA
SA
SA
NC
NF/DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
NC
SA
TOP VIEW
3456789
10 11
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
CE#
CE2
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
SA
SA
SA
SA
NC
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
NC
NC
NC
NC
NC
NF/DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
NF/DQPd
NC
MODE
(LBO#)
BWc#
BWd#
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
SA
SA
BWb#
BWa#
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
DNU
DNU
CE2#
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
SA1
SA0
CKE#
R/W#
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
DNU
DNU
ADV/LD#
OE# (G#)
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
SA
SA
SA
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
SA
SA
SA
SA
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
SA
SA
NC
NC
NF/DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
NF/DQPa
NC
SA
TOP VIEW
3456789
10 11
1
X18
X32/X36
*No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version. NOTE: Pin 9B reserved for address pin expansion; 18Mb.
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8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
FBGA PIN DESCRIPTIONS
x18 x32/x36 SYMBOL TYPE DESCRIPTION
6R 6R SA0 Input Synchronous Address Inputs: These inputs are registered and 6P 6P SA1 must meet the setup and hold times around the rising edge of
2A, 9A, 10A, 2A, 9A, 10A, SA CLK.
11A, 2B, 10B, 2B, 10B,
3P, 4P, 8P, 3P, 4P, 8P,
9P, 10P, 3R, 9P, 10P, 3R,
4R, 8R, 9R, 4R, 8R, 9R,
10R, 11R 10R, 11R
5B 5B BWa# Input Synchronous Byte Write Enables: These active LOW inputs allow 4A 5A BWb# individual bytes to be written and must meet the setup and hold
– 4A BWc# times around the rising edge of CLK. A byte write enable is LOW – 4B BWd# for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb. For the x32 and x36 versions, BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb; BWc# controls DQc’s and DQPc; BWd# controls DQd’s and DQPd. Parity is only available on the x18 and x36 versions.
7A 7A CKE# Input Synchronous Clock Enable: This active LOW input permits CLK to
propogate throughout the device. When CKE# is HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet the setup and hold times around the rising edge of CLK.
7B 7B R/W# Input Read/Write: This input determines the cycle type when ADV/LD#
is LOW and is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE operations to meet the setup and hold times around the rising edge of CLK. Full bus-width WRITEs occur if all byte write enables are LOW.
6B 6B CLK Input Clock: This signal registers the address, data, chip enable, byte
write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock’s rising edge.
3A 3A CE# Input Synchronous Chip Enable: This active LOW input is used to enable
the device. CE# is sampled only when a new external address is loaded.
6A 6A CE2# Input Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is loaded.
11H 11H ZZ Input Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored.
3B 3B CE2 Input Synchronous Chip Enable: This active HIGH input is used to
enable the device and is sampled only when a new external address is loaded.
(continued on next page)
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8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
x18 x32/x36 SYMBOL TYPE DESCRIPTION
8B 8B OE# Input Output Enable: This active LOW, asynchronous input enables the
(G#) data I/O output drivers.
8A 8A ADV/LD# Input Synchronous Address Advance/Load: When HIGH, this input is used
to advance the internal burst counter, controlling burst access after the external address is loaded. When ADV/LD# is HIGH, R/W# is ignored. A LOW on ADV/LD# clocks a new address at the CLK rising edge.
1R 1R MODE Input Mode: This input selects the burst sequence. A LOW on this input
(LBO#) selects “linear burst.” NC or HIGH on this input selects “interleaved
burst.” Do not alter input state while device is operating.
(a) 10J, 10K, (a) 10J, 10K, DQa Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated with
10L, 10M, 11D 10L, 10M, 11J, Output DQa’s; Byte “b” is associated with DQb’s. For the x32 and x36
11E, 11F, 11G 11K, 11L, 11M versions, Byte “a” is associated with DQa’s; Byte “b” is associated
(b) 2D, 2E, 2F, (b) 10D, 10E, DQb with DQb’s; Byte “c” is associated with DQc’s; Byte “d” is associated
2G, 1J, 1K, 10F, 10G, 11D, with DQd’s. Input data must meet setup and hold times around the
1L, 1M 11E, 11F, 11G rising edge of CLK.
(c) 1D, 1E, 1F, DQc
1G, 2D, 2E,
2F, 2G,
(d) 1J, 1K, 1L, DQd
1M, 2J, 2K,
2L, 2M
11C 11N NF/DQPa NF/ No Function/Parity Data I/Os: On the x32 version, these are No
1N 11C NF/DQPb I/O Function(NF). On the x18 version, Byte “a” parity is DQPa; Byte “b”
– 1C NF/DQPc parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte – 1N NF/DQPd “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
1H, 2H, 4D, 1H, 2H, 4D, V
DD
Supply Power Supply: See DC Electrical Characteristics and Operating 4E, 4F, 4G, 4H, 4E, 4F, 4G, 4H, Conditions for range. 4J, 4K, 4L, 4M, 4J, 4K, 4L, 4M, 7N, 8D, 8E, 8F, 7N, 8D, 8E, 8F,
8G,8H, 8J, 8G,8H, 8J,
8K, 8L, 8M 8K, 8L, 8M
3C, 3D, 3E, 3F, 3C, 3D, 3E, 3F, VDDQ Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
3G, 3J, 3K, 3L, 3G, 3J, 3K, 3L, Operating Conditions for range.
3M, 3N, 9C, 3M, 3N, 9C,
9D, 9E, 9F, 9D, 9E, 9F, 9G, 9J, 9K, 9G, 9J, 9K,
9L, 9M, 9N 9L, 9M, 9N
FBGA PIN DESCRIPTIONS (CONTINUED)
(continued on next page)
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8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
x18 x32/x36 SYMBOL TYPE DESCRIPTION
4C, 4N, 5C, 4C, 4N, 5C, V
SS
Supply Ground: GND. 5D, 5E, 5F, 5G, 5D, 5E, 5F, 5G,
5H, 5J, 5K, 5L, 5H, 5J, 5K, 5L,
5M, 6C, 6D, 5M, 6C, 6D, 6E, 6F, 6G, 6H, 6E, 6F, 6G, 6H, 6J, 6K, 6L, 6M, 6J, 6K, 6L, 6M,
7C, 7D, 7E, 7F, 7C, 7D, 7E, 7F, 7G, 7H, 7J, 7K, 7G, 7H, 7J, 7K, 7L, 7M, 8C, 8N 7L, 7M, 8C, 8N
5P, 7P, 5R, 7R 5P, 7P, 5R, 7R DNU – Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
1A, 1B, 1C, 1D, 1A, 1B, 1P, NC – No Connect: These signals are not internally connected and may be
1E, 1F, 1G, 2C, 2N, 2P, connected to ground to improve package heat dissipation.
1P, 2C, 2J, 2K, 2R, 3H, 5N, Pin 9B is reserved for address pin expansion; 16MB.
2L, 2M, 2N, 6N, 9B, 9H,
2P, 2R, 3H, 4B, 10C, 10H, 10N,
5A, 5N, 6N, 11A, 11B, 11P
9B, 9H, 10C,
10D, 10E, 10F,
10G, 10H, 10N,
11B, 11J, 11K,
11L, 11M,
11N, 11P
NF — No Function: These pins are internally connected to the die and
have the capacitance of an input pin. It is allowable to leave these pins unconnected or driven by signals.
FBGA PIN DESCRIPTIONS (CONTINUED)
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8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
FUNCTION R/W# BWa# BWb# BWc# BWd#
READ H X X X X WRITE Byte “a” LLHHH WRITE Byte “b” LHLHH WRITE Byte “c” LHHLH WRITE Byte “d” LHHHL WRITE All Bytes LLLLL WRITE ABORT/NOP L H H H H
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X...X00 X...X01 X...X10 X...X11 X...X01 X...X00 X...X11 X...X10 X...X10 X...X11 X...X00 X...X01 X...X11 X...X10 X...X01 X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X...X00 X...X01 X...X10 X...X11 X...X01 X...X10 X...X11 X...X00 X...X10 X...X11 X...X00 X...X01 X...X11 X...X00 X...X01 X...X10
PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x32/x36)
NOTE: Using R/W# and byte write(s), any one or more bytes may be written.
FUNCTION R/W# BWa# BWb#
READ H X X WRITE Byte “a” LLH WRITE Byte “b” LHL WRITE All Bytes L L L WRITE ABORT/NOP L H H
PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x18)
NOTE: Using R/W# and byte write(s), any one or more bytes may be
written.
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8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
STATE DIAGRAM FOR ZBT SRAM
DESELECT
BEGIN
READ
BURST
READ
BEGIN
WRITE
DS
DS DS
BURST WRITE
READ
DS
WRITE
WRITE
BURST
READ
WRITE
READ
BURSTBURST
READ
BURST
DS
WRITE
KEY: COMMAND
DS READ WRITE BURST
OPERATION
DESELECT New READ New WRITE BURST READ, BURST WRITE, or CONTINUE DESELECT
BURSTREAD
WRITE
NOTE: 1. A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the
clock (CLK) input and does not change the state of the device.
2. States change on the rising edge of the clock (CLK).
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8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
TRUTH TABLE
(Notes 5-10)
ADDRESS ADV/
OPERATION USED CE# CE2# CE2 ZZ L D# R/W# BWx OE# CKE# CLK D Q NOTES
DESELECT Cycle None H X X L L X X X L L-H High-Z DESELECT Cycle None X H X L L X X X L L-H High-Z DESELECT Cycle None X X L L L X X X L L-H High-Z CONTINUE DESELECT Cycle None X X X L H X X X L L-H High-Z 1 READ Cycle External L L H L L H X L L L-H Q
(Begin Burst) READ Cycle Next X X X L H X X L L L-H Q 1, 11
(Continue Burst) NOP/DUMMY READ External L L H L L H X H L L-H High-Z 2
(Begin Burst) DUMMY READ Next X X X L H X X H L L-H High-Z 1, 2,
(Continue Burst) 11 WRITE Cycle External L L H L L L L X L L-H D 3
(Begin Burst) WRITE Cycle Next X X X L H X L X L L-H D 1, 3,
(Continue Burst) 11 NOP/WRITE ABORT None L L H L L L H X L L-H High-Z 2, 3
(Begin Burst) WRITE ABORT Next X X X L H X H X L L-H High-Z 1, 2,
(Continue Burst) 3, 11 IGNORE CLOCK EDGE Current X X X L X X X X H L-H – 4
(Stall) SNOOZE MODE None X X X H X X X X X X High-Z
NOTE: 1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or
WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT cycle is executed first.
2. DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a WRITE command is given, but no operation is performed.
3. OE# may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the output drivers during a WRITE cycle. OE# may be used when the bus turn-on and turn-off times do not meet an application’s requirements.
4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE CLOCK EDGE cycle.
5. X means “Don’t Care.” H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa#, BWb#, BWc# and BWd#) are HIGH. BWx = L means one or more byte write signals are LOW.
6. BWa# enables WRITEs to Byte “a” (DQa pins); BWb# enables WRITEs to Byte “b” (DQb pins); BWc# enables WRITEs to Byte “c” (DQc pins); BWd# enables WRITEs to Byte “d” (DQd pins).
7. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
8. Wait states are inserted by setting CKE# HIGH.
9. This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth burst cycle.
11. The address counter is incremented for all CONTINUE BURST cycles.
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8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply
Relative to VSS ................................... -0.5V to +4.6V
Voltage on VDDQ Supply
Relative to V
SS ....................................... -0.5V to VDD
VIN -0.5V to VDDQ + 0.5V
Storage Temperature (plastic) .......... -55°C to +150°C
Storage Temperature (FBGA) .......... -55°C to +125°C
Junction Temperature** .................................. +150°C
Short Circuit Output Current .......................... 100mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature, and airflow. See Micron Technical Note TN-05-14 for more information.
3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0°C ≤ TA ≤ +70°C; VDD, VDDQ = +3.3V ±0.165V unless otherwise noted)
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES
Input High (Logic 1) Voltage VIH 2.0 VDD + 0.3 V 1, 2 Input High (Logic 1) Voltage DQ pins VIH 2.0 VDD + 0.3 V 1, 2 Input Low (Logic 0) Voltage VIL -0.3 0.8 V 1, 2 Input Leakage Current 0V ≤ VIN ≤ VDD ILI -1.0 1.0 µA 3 Output Leakage Current Output(s) disabled, ILO -1.0 1.0 µA
0V ≤ VIN ≤ VDD
Output High Voltage IOH = -4.0mA VOH 2.4 – V 1, 4 Output Low Voltage IOL = 8.0mA VOL – 0.4 V 1, 4 Supply Voltage VDD 3.135 3.465 V 1 Isolated Output Buffer Supply VDDQ 3.135 VDD V 1, 5
NOTE: 1. All voltages referenced to VSS (GND).
2. Overshoot: VIH ≤ +4.6V for t ≤ tKHKH/2 for I ≤ 20mA Undershoot: VIL ≥ -0.7V for t ≤ tKHKH/2 for I ≤ 20mA Power-up: VIH ≤ +3.465V and VDD ≤ +3.135V for t ≤ 200ms
3. MODE pin has an internal pull-up, and input leakage = ±10µA.
4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O curves are available upon request.
5. VDDQ should never exceed VDD. VDD and VDDQ can be externally wired together to the same power supply.
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8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0°C ≤ TA ≤ +70°C; VDD = +3.3V ±0.165V; VDDQ = +2.5V +0.4V/-0.125V unless otherwise noted)
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES
Input High (Logic 1) Voltage Data bus (DQx) VIHQ 1.7 VDDQ + 0.3 V 1, 2
Inputs VIH 1.7 VDD + 0.3 V 1, 2
Input Low (Logic 0) Voltage VIL -0.3 0.7 V 1, 2 Input Leakage Current 0V ≤ VIN ≤ VDD ILI -1.0 1.0 µA 3 Output Leakage Current Output(s) disabled, ILO -1.0 1.0 µA
0V ≤ VIN ≤ VDDQ (DQx)
Output High Voltage IOH = -2.0mA VOH 1.7 – V1
IOH = -1.0mA VOH 2.0 – V1
Output Low Voltage IOL = 2.0mA VOL – 0.7 V 1
IOL = 1.0mA VOL – 0.4 V 1 Supply Voltage VDD 3.135 3.465 V 1 Isolated Output Buffer Supply VDDQ 2.375 2.9 V 1
NOTE: 1. All voltages referenced to VSS (GND).
2. Overshoot: VIH ≤ +4.6V for t ≤ tKHKH/2 for I ≤ 20mA Undershoot: VIL ≥ -0.7V for t ≤ tKHKH/2 for I ≤ 20mA Power-up: VIH ≤ +3.465V and VDD ≤ +3.135V for t ≤ 200ms
3. MODE pin has an internal pull-up, and input leakage = ±10µA.
4. This parameter is sampled.
5. Preliminary package data.
TQFP CAPACITANCE
DESCRIPTION CONDITIONS SYMBOL TYP MAX UNITS NOTES
Control Input Capacitance TA = +25°C; f = 1 MHz CI 34pF4 Input/Output Capacitance (DQ) VDD = +3.3V CO 45pF4 Address Capacitance CA 3 3.5 pF 4 Clock Capacitance CCK 3 3.5 pF 4
FBGA CAPACITANCE
DESCRIPTION CONDITIONS SYMBOL TYP MAX UNITS NOTES
Address/Control Input Capacitance CI 2.5 3.5 pF 4, 5 Output Capacitance (Q) TA = 25°C; f = 1 MHz CO 4 5 p F 4, 5 Clock Capacitance CCK 2.5 3.5 pF 4, 5
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8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
NOTE: 1. VDDQ = +3.3V ±0.165V for 3.3V I/O configuration; VDDQ = +2.5V +0.4V/-0.125V for 2.5V I/O
configuration.
2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading.
3. “Device deselected” means device is in a deselected cycle as defined in the truth table. “Device selected” means device is active (not in deselected mode).
4. Typical values are measured at +3.3V, +25°C and 10ns cycle time.
5. This parameter is sampled.
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(Note 1) (0°C ≤ TA ≤ +70°C; VDD = +3.3V ±0.165V unless otherwise noted)
DESCRIPTION CONDITIONS SYMBOL TYP -6 -7.5 -10 UNITS NOTES
Power Supply Device selected; All inputs ≤ V
IL
Current: Operating or ≥ VIH; Cycle time ≥ tKC (MIN); I
DD
200 500 400 300 mA 2, 3, 4
VDD = MAX; Outputs open
Power Supply Device selected; VDD = MAX; Current: Idle CKE# ≥ VIH;I
DD
1 10 25 25 20 mA 2, 3, 4
All inputs ≤ V
SS
+ 0.2 or ≥ VDD - 0.2;
Cycle time ≥ tKC (MIN)
CMOS Standby Device deselected; VDD = MAX;
All inputs ≤ VSS + 0.2 or ≥ VDD - 0.2; I
SB
2 0.5 10 10 10 mA 3, 4
All inputs static; CLK frequency = 0
TTL Standby Device deselected; VDD = MAX;
All inputs ≤ VIL or ≥ VIH;I
SB
3 6 252525mA3, 4
All inputs static; CLK frequency = 0
Clock Running Device deselected; VDD = MAX;
ADV/LD# ≥ VIH; All inputs ≤ VSS + 0.2 I
SB
4 45 120 75 60 m A 3, 4
or ≥ VDD - 0.2; Cycle time ≥ tKC (MIN)
Snooze Mode ZZ ≥ V
IH
I
SB2Z
0.5 10 10 10 mA 4
MAX
TQFP THERMAL RESISTANCE
DESCRIPTION CONDITIONS SYMBOL TYP UNITS NOTES
Thermal Resistance Test conditions follow standard test methods θ
JA
40 °C/W 5
(Junction to Ambient) and procedures for measuring thermal
Thermal Resistance
impedance, per EIA/JESD51.
θ
JC
8 °C/W 5
(Junction to Top of Case)
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8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
NOTE: 1. This parameter is sampled.
2. OE# can be considered a “Don’t Care” during WRITEs; however, controlling OE# can help fine-tune a system for turnaround timing.
3. Test conditions as specified with output loading as shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V ±0.165V) and Figure 3 for 2.5V I/O (VDDQ = +2.5V +0.4V/-0.125V).
4. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times.
5. Measured as HIGH above VIH and LOW below VIL.
6. Refer to Technical Note TN-55-01, “Designing with ZBT SRAMs,” for a more thorough discussion on these parameters.
7. This parameter is sampled.
8. This parameter is measured with output loading as shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.
9. Transition is measured ±200mV from steady state voltage.
10. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when they are being registered into the device. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when ADV/LD# is LOW to remain enabled.
11. Preliminary package data.
AC ELECTRICAL CHARACTERISTICS
(Notes 2, 3, 4) (0°C ≤ TA ≤ +70°C; VDD = +3.3V ±0.165V unless otherwise noted)
-6 -7.5 -10 DESCRIPTION SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES Clock
Clock cycle time
t
KHKH 6.0 7.5 10 ns
Clock frequency
f
KF 166 133 100 MHz
Clock HIGH time
t
KHKL 1.7 2.0 3.2 ns 5
Clock LOW time
t
KLKH 1.7 2.0 3.2 ns 5
Output Times
Clock to output valid
t
KHQV 3.5 4.2 5.0 ns
Clock to output invalid
t
KHQX 1.5 1.5 1.5 ns 6
Clock to output in Low-Z
t
KHQX1 1.5 1.5 1.5 ns 6, 7, 8, 9
Clock to output in High-Z
t
KHQZ 1.5 3.5 1.5 3.5 1.5 3.5 ns 6, 7, 8, 9
OE# to output valid
t
GLQV 3.5 4.2 5.0 ns 2
OE# to output in Low-Z
t
GLQX 0 0 0 ns 6, 7, 8, 9
OE# to output in High-Z
t
GHQZ 3.5 4.2 5.0 ns 6, 7, 8, 9
Setup Times
Address
t
AVKH 1.5 1.7 2.0 ns 10
Clock enable (CKE#)
t
EVKH 1.5 1.7 2.0 ns 10
Control signals
t
CVKH 1.5 1.7 2.0 ns 10
Data-in
t
DVKH 1.5 1.7 2.0 ns 10
Hold Times
Address
t
KHAX 0.5 0.5 0.5 ns 10
Clock enable (CKE#)
t
KHEX 0.5 0.5 0.5 ns 10
Control signals
t
KHCX 0.5 0.5 0.5 ns 10
Data-in
t
KHDX 0.5 0.5 0.5 ns 10
FBGA THERMAL RESISTANCE
DESCRIPTION CONDITIONS SYMBOL TYP UNITS NOTES
Junction to Ambient Test conditions follow standard test methods θ
JA
40 °C/W 1, 11
(Airflow of 1m/s) and procedures for measuring thermal
Junction to Case (Top)
impedance, per EIA/JESD51.
θ
JC
9 °C/W 1, 11
Junction to Pins (Bottom) θ
JB
17 °C/W 1, 11
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8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. MT55L512L18P_C.p65 – Rev. 2/02 ©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
Q
50
V = 1.5V
Z = 50
O
T
Figure 1
Q
351
317
5pF
+3.3V
Figure 2
3.3V I/O AC TEST CONDITIONS
Input pulse levels ...................................VSS to 3.3V
Input rise and fall times ..................................... 1ns
Input timing reference levels .......................... 1.5V
Output reference levels ................................... 1.5V
Output load ............................. See Figures 1 and 2
LOAD DERATING CURVES
The Micron 512K x 18, 256K x 32, and 256K x 36 ZBT SRAM timing is dependent upon the capacitive loading on the outputs.
Consult the factory for copies of I/O current versus voltage curves.
Q
50Ω
V = 1.25V
Z = 50Ω
O
T
Figure 3
Q
225Ω
225Ω
5pF
+2.5V
Figure 4
2.5V I/O AC TEST CONDITIONS
Input pulse levels ...................................VSS to 2.5V
Input rise and fall times ..................................... 1ns
Input timing reference levels ........................ 1.25V
Output reference levels ................................. 1.25V
Output load ............................. See Figures 3 and 4
3.3V I/O Output Load Equivalents 2.5V I/O Output Load Equivalents
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8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. MT55L512L18P_C.p65 – Rev. 2/02 ©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
SNOOZE MODE
SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time the ZZ pin is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become disabled and all outputs go to High-Z.
The ZZ pin is an asynchronous, active HIGH input
that causes the device to enter SNOOZE MODE. When
the ZZ pin becomes a logic HIGH, ISB2Z is guaranteed after the time tZZI is met. Any READ or WRITE opera­tion pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pend­ing operations are completed. Similarly, when exiting SNOOZE MODE during tRZZ, only a DESELECT or READ cycle should be given.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES
Current during SNOOZE MODE ZZ ≥ V
IH
I
SB
2Z 10 m A
ZZ active to input ignored
t
ZZ 0 2(tKHKH) ns 1
ZZ inactive to input sampled
t
RZZ 0 2(tKHKH) ns 1
ZZ active to snooze current
t
ZZI 2(tKHKH) ns 1
ZZ inactive to exit snooze current
t
RZZI 0 ns 1
SNOOZE MODE WAVEFORM
t
ZZ
I
SUPPLY
CLK
ZZ
t
RZZ
ALL INPUTS
(except ZZ)
DON’T CARE
I
ISB2Z
t
ZZI
t
RZZI
Outputs (Q)
High-Z
DESELECT or READ Only
NOTE: 1. This parameter is sampled.
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8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. MT55L512L18P_C.p65 – Rev. 2/02 ©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
READ/WRITE TIMING
WRITE
D(A1)
123456789
CLK
t
KHKH
t
KLKH
t
KHKL
10
CE#
t
KHCX
t
CVKH
R/W#
CKE#
t
KHEX
t
EVKH
BWx#
ADV/LD#
t
KHAX
t
AVKH
ADDRESS
A1 A2
A3
A4
A5 A6 A7
t
KHDX
t
DVKH
DQ
COMMAND
t
KHQX1
D(A1) D(A2) D(A5)Q(A4)Q(A3)
D(A2+1)
t
KHQX
t
KHQZ
t
KHQV
WRITE
D(A2)
BURST WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ Q(A6)
WRITE
D(A7)
DESELECT
OE#
t
GLQV
t
GLQX
t
GHQZ
t
KHQX
DON’T CARE UNDEFINED
Q(A6)
Q(A4+1)
NOTE: 1. For this waveform, ZZ is tied LOW.
2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional.
3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register.
-6 -7.5 -10
SYM MIN MAX MIN MAX MIN MAX UNITS
t
GHQZ 3.5 4.2 5.0 ns
t
AVKH 1.5 1.7 2.0 ns
t
EVKH 1.5 1.7 2.0 ns
t
CVKH 1.5 1.7 2.0 ns
t
DVKH 1.5 1.7 2.0 ns
t
KHAX 0.5 0.5 0.5 ns
t
KHEX 0.5 0.5 0.5 ns
t
KHCX 0.5 0.5 0.5 ns
t
KHDX 0.5 0.5 0.5 ns
READ/WRITE TIMING PARAMETERS
-6 -7.5 -10
SYM MIN MAX MIN MAX MIN MAX UNITS
t
KHKH 6.0 7.5 10 ns
f
KF 166 133 100 MHz
t
KHKL 1.7 2.0 3.2 ns
t
KLKH 1.7 2.0 3.2 ns
t
KHQV 3.5 4.2 5.0 ns
t
KHQX 1.5 1.5 1.5 ns
t
KHQX1 1.5 1.5 1.5 ns
t
KHQZ 1.5 3.5 1.5 3.5 1.5 3.5 ns
t
GLQV 3.5 4.2 5.0 ns
t
GLQX 0 0 0 ns
Page 22
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8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. MT55L512L18P_C.p65 – Rev. 2/02 ©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
NOP, STALL, AND DESELECT CYCLES
READ Q(A3)
45678910
CLK
CE#
R/W#
CKE#
BWx#
ADV/LD#
ADDRESS
A3 A4
A5
D(A4)
DQ
COMMAND
A1
Q(A5)
WRITE
D(A4)
STALLWRITE
D(A1)
123
READ Q(A2)
STALL NOP READ
Q(A5)
DESELECT CONTINUE
DESELECT
DON’T CARE UNDEFINED
t
KHQZ
t
KHQX
A2
D(A1) Q(A2) Q(A3)
NOTE: 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a “pause.” A WRITE is not
performed during this cycle.
2. For this waveform, ZZ and OE# are tied LOW.
3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register.
NOP, STALL, AND DESELECT TIMING PARAMETERS
-6 -7.5 -10
SYM MIN MAX MIN MAX MIN MAX UNITS
t
KHQX 1.5 1.5 1.5 ns
t
KHQZ 1.5 3.5 1.5 3.5 1.5 3.5 ns
Page 23
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8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. MT55L512L18P_C.p65 – Rev. 2/02 ©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
100-PIN PLASTIC TQFP (JEDEC LQFP)
14.00 ±0.10
20.10 ±0.10
0.62
22.10
+0.10
-0.15
16.00
+0.20
-0.05
PIN #1 ID
0.65
1.50 ±0.10
0.25
0.60 ±0.15
1.40 ±0.05
0.32
+0.06
-0.10
0.15
+0.03
-0.02
0.10
+0.10
-0.05
DETAIL A
DETAIL A
1.00 (TYP)
GAGE PLANE
0.10
NOTE: 1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
Page 24
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8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. MT55L512L18P_C.p65 – Rev. 2/02 ©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
165-PIN FBGA
NOTE: 1. All dimensions in millimeters
MAX
or typical where noted.
MIN
10.00
14.00
15.00 ±0.10
1.00 TYP
1.00 TYP
5.00 ±0.05
13.00 ±0.10
PIN A1 ID
PIN A1 ID
BALL A1
MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE: PLASTIC LAMINATE
6.50 ±0.05
7.00 ±0.05
7.50 ±0.05
1.20 MAX
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb SOLDER BALL PAD: Ø .33mm
SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø 0.40
SEATING PLANE
0.85 ±0.075
0.12
C
C
165X Ø 0.45
BALL A11
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark of Micron Technology, Inc.
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc.,
and the architecture is supported by Micron Technology, Inc., and Motorola Inc.
Page 25
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8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. MT55L512L18P_C.p65 – Rev. 2/02 ©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
REVISION HISTORY
Removed "Preliminary Package Data" from front page ....................................................................... February 22/02
Removed 119-pin PBGA package and references ................................................................................. February 14/02
Removed note "Not Recommended for New Designs," Rev. 6/01 ................................................................ June 7/01
Added industrial temperature references and notes, Rev. 3/01 ................................................................ March 19/01
Changed 16Mb references to 18Mb Changed NC/DQPx to NF/DQPx
Added 119-pin PBGA package, Rev. 1/01, FINAL ............................................................................................ 1/10/01
Removed FBGA Part Marking Guide, Rev. 8/00, FINAL .................................................................................... 8/1/00
Added FBGA Part Marking Guide, REV 7/00, FINAL ...................................................................................... 7/20/00
Added Revision History Removed 119-Pin PBGA package and references
Added 165-pin FBGA Package........................................................................................................................... 6/13/00
Removed "Smart ZBT" references ....................................................................................................................... 6/13/00
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