Page 1
TECHNOLOGY, INC.
VCC
DQ1
DQ2
WE#
RAS#
*NC/A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
VSS
DQ4
DQ3
CAS#
OE#
A9
A8
A7
A6
A5
A4
V
SS
DRAM
4 MEG x 4
EDO DRAM
MT4LC4M4E8, MT4C4M4E8
MT4LC4M4E9, MT4C4M4E9
FEATURES
• Industry-standard x4 pinout, timing, functions and
PIN ASSIGNMENT (Top View)
packages
• State-of-the-art, high-performance, low-power CMOS
silicon-gate process
24/26-Pin SOJ
(DA-2)
24/26-Pin TSOP
(DB-2)
• Single power supply (+3.3V ±0.3V or +5V ±10%)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, HIDDEN and CAS#BEFORE-RAS# (CBR)
• Optional Self Refresh (S) for low-power data retention
• 11 row, 11 column addresses (2K refresh) or
12 row, 10 column addresses (4K refresh)
• Extended Data-Out (EDO) PAGE MODE access cycle
• 5V-tolerant inputs and I/Os on 3.3V devices
DQ1
DQ2
WE#
RAS#
*NC/A11
A10
V
1
2
3
4
5
6
8
A0
9
A1
10
A2
11
A3
12
CC
13
SS
26
V
DQ4
25
DQ3
24
CAS#
23
OE#
22
A9
21
A8
19
A7
18
A6
17
A5
16
A4
15
SS
V
14
V
CC
OPTIONS MARKING
• Voltages
3.3V LC
5V C
• Refresh Addressing
2,048 (i.e. 2K) Rows E8
4,096 (i.e. 4K) Rows E9
• Packages
Plastic SOJ (300 mil) DJ
Plastic TSOP (300 mil) TG
• Timing
50ns access -5
60ns access -6
• Refresh Rates
Standard Refresh None
Self Refresh (128ms period) S
• Part Number Example: MT4LC4M4E8DJ-6
Note: The 4 Meg x 4 EDO DRAM base number differentiates the offerings in
two places - MT4LC4M4E8. The third field distinguishes the low voltage
offering: LC designates VCC = 3.3V and C designates VCC = 5V. The fifth field
distinguishes various options: E8 designates a 2K refresh and E9 designates a
4K refresh for EDO DRAMs.
* NC on 2K refresh and A11 on 4K refresh options.
Note: The “#” symbol indicates signal is active LOW.
4 MEG x 4 EDO DRAM PART NUMBERS
PART NUMBER Vcc REFRESH PACKAGE REFRESH
MT4LC4M4E8DJ 3.3V 2K SOJ Standard
MT4LC4M4E8DJS 3.3V 2K SOJ Self
MT4LC4M4E8TG 3.3V 2K TSOP Standard
MT4LC4M4E8TGS 3.3V 2K TSOP Self
MT4LC4M4E9DJ 3.3V 4K SOJ Standard
MT4LC4M4E9DJS 3.3V 4K SOJ Self
MT4LC4M4E9TG 3.3V 4K TSOP Standard
MT4LC4M4E9TGS 3.3V 4K TSOP Self
MT4C4M4E8DJ 5V 2K SOJ Standard
MT4C4M4E8DJS 5V 2K SOJ Self
MT4C4M4E8TG 5V 2K TSOP Standard
MT4C4M4E8TGS 5V 2K TSOP Self
MT4C4M4E9DJ 5V 4K SOJ Standard
MT4C4M4E9DJS 5V 4K SOJ Self
MT4C4M4E9TG 5V 4K TSOP Standard
MT4C4M4E9TGS 5V 4K TSOP Self
KEY TIMING PARAMETERS
SPEEDtRC
t
RAC
t
PC
t
AA
t
CACtCAS
-5 84ns 50ns 20ns 25ns 13ns 8ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
-6 104ns 60ns 25ns 30ns 15ns 10ns
GENERAL DESCRIPTION
The 4 Meg x 4 DRAM is a randomly accessed, solid-state
memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11
bits for 2K and first 12 bits for 4K). Once the page has been
opened by RAS#, CAS# is used to latch the column address
1
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TECHNOLOGY, INC.
,
,,
,,
,,,
,,
GENERAL DESCRIPTION (continued)
(the latter 11 bits for 2K and the latter 10 bits for 4K, address
pins A10 and A11 are “don’t care”). READ and WRITE
cycles are selected with the WE# input.
A logic HIGH on WE# dictates READ mode, while a logic
LOW on WE# dictates WRITE mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE# or
CAS#, whichever occurs last. An EARLY WRITE occurs
when WE# is taken LOW prior to CAS# falling. A LATE
WRITE or READ-MODIFY-WRITE occurs when WE# falls
after CAS# is taken LOW. During EARLY WRITE cycles,
the data outputs (Q) will remain High-Z regardless of the
state of OE#. During LATE WRITE or READ-MODIFYWRITE cycles, OE# must be taken HIGH to disable the data
outputs prior to applying input data. If a LATE WRITE or
READ-MODIFY-WRITE is attempted while keeping OE#
LOW, no write will occur, and the data outputs will drive
read data from the accessed location.
The four data inputs and the four data outputs are routed
through four pins using common I/O, and pin direction is
controlled by WE# and OE#.
PAGE ACCESS
PAGE operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row addressdefined page boundary. The PAGE cycle is always initiated
4 MEG x 4
EDO DRAM
with a row address strobed-in by RAS#, followed by a
column address strobed-in by CAS#. CAS# may be
toggled-in by holding RAS# LOW and strobing-in different
column addresses, thus executing faster memory cycles.
Returning RAS# HIGH terminates the PAGE MODE of
operation, i.e., closes the page.
EDO PAGE MODE
The 4 Meg x 4 EDO DRAM provides EDO PAGE MODE,
which is an accelerated FAST PAGE MODE cycle. The
primary advantage of EDO is the availability of data-out
even after CAS# returns HIGH. EDO allows CAS# precharge
time (tCP) to occur without the output data going invalid.
This elimination of CAS# output control allows pipeline
READs.
FAST PAGE MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS#. EDO PAGE MODE DRAMs operate like FAST
PAGE MODE DRAMs, except data will remain valid or
become valid after CAS# goes HIGH during READs, provided RAS# and OE# are held LOW. If OE# is pulsed while
RAS# and CAS# are LOW, data will toggle from valid data
to High-Z and back to the same valid data. If OE# is toggled
or pulsed after CAS# goes HIGH while RAS# remains
LOW, data will transition to and remain High-Z (refer to
RAS#
CAS#
ADDR
OE#
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IOH
DQ
V
IOL
V
IH
V
IL
ROW
OPEN
COLUMN (A)
VALID DATA (A)
t
OD
t
OES
The DQs go back to
Low-Z if
t
OE
t
OES is met.
COLUMN (B)
VALID DATA (A)
VALID DATA (B)
t
OD
t
OEHC
The DQs remain High-Z
until the next CAS# cycle
t
if
OEHC is met.
COLUMN (C)
VALID DATA (C)
t
OD
t
OEP
The DQs remain High-Z
until the next CAS# cycle
t
if
OEP is met.
COLUMN (D)
VALID DATA (D)
DON’T CARE
UNDEFINED
Figure 1
OE# CONTROL OF DQs
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
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TECHNOLOGY, INC.
,
,
,
,,,
4 MEG x 4
EDO DRAM
Figure 1). WE# can also perform the function of disabling
the output devices under certain conditions, as shown in
Figure 2.
During an application, if the DQ outputs are wire OR’d,
OE# must be used to disable idle banks of DRAMs. Alternatively, pulsing WE# to the idle banks during CAS# high
time will also High-Z the outputs. Independent of OE#
control, the outputs will disable after tOFF, which is referenced from the rising edge of RAS# or CAS#, whichever
occurs last.
REFRESH
Preserve correct memory cell data by maintaining power
and executing any RAS# cycle (READ, WRITE) or RAS#
refresh cycle (RAS#-ONLY, CBR or HIDDEN) so that all
combinations of RAS# addresses (2,048 for 2K and 4,096 for
4K) are executed within tREF (MAX), regardless of sequence. The CBR and Self Refresh cycles will invoke the
internal refresh counter for automatic RAS# addressing.
An optional Self Refresh mode is also available on the S
version. The “S” option allows the user the choice of a fully
static, low-power data retention mode or a dynamic refresh
mode at the extended refresh period of 128ms. The optional
Self Refresh feature is initiated by performing a CBR Re-
fresh cycle and holding RAS# LOW for the specified tRASS.
Additionally, the “S” option allows for an extended refresh
period of 128ms, or 31.25µs per row for a 4K refresh and
62.5µs per row for a 2K refresh if using distributed CBR
Refresh. This refresh rate can be applied during normal
operation, as well as during a standby or BATTERY BACKUP
mode.
The Self Refresh mode is terminated by driving
RAS#
HIGH for a minimum time of tRPS. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the
RAS# LOW-to-HIGH transition.
If the DRAM controller uses a distributed refresh sequence, a burst refresh is not required upon exiting
Self Refresh
RAS#-ONLY or
refreshed within the average internal refresh rate
. However, if the DRAM controller utilizes
burst refresh sequence, all rows must be
, prior to
the resumption of normal operation.
STANDBY
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
The chip is preconditioned for the next cycle during the
RAS# HIGH time.
a
RAS#
CAS#
ADDR
DQ
WE#
OE#
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IOH
V
IOL
V
IH
V
IL
V
IH
V
IL
ROW
OPEN
COLUMN (A)
COLUMN (B)
VALID DATA (A)
t
WHZ
t
WPZ
The DQs go to High-Z if WE# falls and, if tWPZ is met,
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
VALID DATA (B)
COLUMN (C)
INPUT DATA (C)
t
WHZ
WE# may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
DON’T CARE
UNDEFINED
COLUMN (D)
Figure 2
WE# CONTROL OF DQs
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
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TECHNOLOGY, INC.
4 MEG x 4
EDO DRAM
FUNCTIONAL BLOCK DIAGRAM - 2K REFRESH
WE#
CAS#
A10
RAS#
4
4
4
4
(1 OF 2)
ROW TRANSFER
ROW TRANSFER
(1 OF 2)
DD
V
VSS
DQ1
DQ2
DQ3
DQ4
OE#
DATA-IN
BUFFER
NO. 2 CLOCK
GENERATOR
COLUMN
ADDRESS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
11
11
NO. 1 CLOCK
GENERATOR
BUFFER(11)
REFRESH
CONTROLLER
REFRESH
COUNTER
11
ROW
ADDRESS
BUFFERS (11)
11
10
ROW
DECODER
1
2048
2048
2048
2048
2048
SELECT
COMPLEMENT
DATA-OUT
BUFFER
COLUMN
DECODER
1024
SENSE AMPLIFIERS
I/O GATING
1024
4096 x 1024 x 4
MEMORY
ARRAY
(2 of 4096)
ROW SELECT
WE#
CAS#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
RAS#
NO. 2 CLOCK
GENERATOR
10
12
NO. 1 CLOCK
GENERATOR
FUNCTIONAL BLOCK DIAGRAM - 4K REFRESH
COLUMN
ADDRESS
BUFFER(10)
REFRESH
CONTROLLER
REFRESH
COUNTER
12
ROW
ADDRESS
BUFFERS (12)
12
10
ROW
DECODER
4096
4096
4096
SELECT
COMPLEMENT
ROW SELECT
DATA-IN
BUFFER
DATA-OUT
BUFFER
COLUMN
DECODER
1024
SENSE AMPLIFIERS
I/O GATING
1024
4096 x 1024 x 4
MEMORY
ARRAY
(1 of 4096)
4
4
DQ1
DQ2
DQ3
DQ4
4
OE#
4
DD
V
V
SS
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
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4 MEG x 4
TECHNOLOGY, INC.
TRUTH TABLE
ADDRESSES DATA-IN/OUT
FUNCTION RAS# CAS# WE# OE#
t
R
Standby H H→XXXXX High-Z
READ L L H L ROW COL Data-Out
EARLY WRITE L L L X ROW COL Data-In
READ WRITE L L H→LL→H ROW COL Data-Out, Data-In
EDO-PAGE-MODE 1st Cycle L H→L H L ROW COL Data-Out
READ 2nd Cycle L H→L H L n/a COL Data-Out
EDO-PAGE-MODE 1st Cycle L H→L L X ROW COL Data-In
EARLY WRITE 2nd Cycle L H→L L X n/a COL Data-In
Any Cycle L L→H H L n/a n/a Data-Out
EDO-PAGE-MODE 1st Cycle L H→LH→LL→H ROW COL Data-Out, Data-In
READ-WRITE 2nd Cycle L H→LH→LL→H n/a COL Data-Out, Data-In
HIDDEN READ L→H→L L H L ROW COL Data-Out
REFRESH WRITE L→H→L L L X ROW COL Data-In
RAS#-ONLY REFRESH L H X X ROW n/a High-Z
CBR REFRESH H→L L H X X X High-Z
SELF REFRESH H→L L H X X X High-Z
t
C DQ1-DQ4
EDO DRAM
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
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TECHNOLOGY, INC.
4 MEG x 4
EDO DRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Pin Relative to VSS:
3.3V ................................................................ -1V to +4.6V
5V ...................................................................... -1V to +7V
Voltage on NC, Inputs or I/O Pins Relative to VSS:
3.3V ................................................................ -1V to +5.5V
5V ...................................................................... -1V to +7V
Operating Temperature, TA (ambient) .......... 0°C to +70°C
Storage Temperature (plastic).................... -55°C to +150°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... 50mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1)
3.3V 5V
PARAMETER/CONDITION SYMBOL MIN MAX MIN MAX UNITS NOTES
Supply Voltage VCC 3.0 3.6 4.5 5.5 V
Input High Voltage:
Valid Logic 1; all inputs, I/Os and any NC VIH 2.0 5.5 2.4 VCC +1 V
Input Low Voltage:
Valid Logic 0; all inputs, I/Os and any NCVIL-1.00.8-0.5 0.8V
Input Leakage Current:
Any input at VIN (0V ≤ VIN ≤ VIH [MAX]); II -2 2 -2 2 µA 4
all other pins not under test = 0V
Output High Voltage:
IOUT = -2mA (3.3V), -5mA (5V) VOH 2.4 - 2.4 - V
Output Low Voltage:
IOUT = 2mA (3.3V), 4.2mA (5V) VOL - 0.4 - 0.4 V
Output Leakage Current:
Any output at VOUT (0V ≤ VOUT ≤ 5.5V); IOZ -5 5 -5 5 µA
DQ is disabled and in High-Z state
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
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4 MEG x 4
TECHNOLOGY, INC.
Icc OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3)
3.3V 5V
2K 4K 2K 4K
PARAMETER/CONDITION SYM SPEED Refresh Refresh Refresh Refresh UNITS NOTES
STANDBY CURRENT: TTL ICC1 ALL1111mA
(RAS# = CAS# = VIH)
STANDBY CURRENT: CMOS (non-S version only) ICC2 ALL 500 500 500 500 µA
(RAS# = CAS# = other inputs = VCC -0.2V)
STANDBY CURRENT: CMOS (S version only) ICC2 ALL 150 150 150 150 µA
(RAS# = CAS# = other inputs = VCC -0.2V)
OPERATING CURRENT: Random READ/WRITE -5 110 90 140 120 mA 5, 6
Average power supply current ICC3 -6 100 80 130 110
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
OPERATING CURRENT: EDO PAGE MODE -5 110 100 110 100 mA 5, 6
Average power supply current (RAS# = VIL,ICC4 -6 100 90 100 90
CAS#, address cycling: tPC = tPC [MIN])
REFRESH CURRENT: RAS#-ONLY -5 110 90 140 120 mA 5, 6
Average power supply current ICC5 -6 100 80 130 110
(RAS# cycling, CAS# = VIH: tRC = tRC [MIN])
REFRESH CURRENT: CBR -5 110 90 140 120 mA 5, 7
Average power supply current ICC6 -6 100 80 130 110
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
REFRESH CURRENT: Extended (S version only)
Average power supply current: CAS# = 0.2V or ALL 300 300 300 300 µA 5, 7
CBR cycling; RAS# = tRAS (MIN); WE# = ICC7
VCC -0.2V; A0-A11,OE# and DIN = VCC -0.2V or
0.2V (DIN may be left open)
REFRESH CURRENT: Self (S version only)
Average power supply current: CBR with
RAS# ≥ tRASS (MIN) and CAS# held LOW; WE# = ICC8 ALL 300 300 300 300 µA 5, 7
VCC -0.2V; A0-A11, OE# and DIN = VCC -0.2V
or 0.2V (DIN may be left open)
t
RC 62.5 31.25 62.5 31.25 µs25
EDO DRAM
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
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4 MEG x 4
TECHNOLOGY, INC.
CAPACITANCE
PARAMETER SYMBOL MAX UNITS NOTES
Input Capacitance: Address pins CI1 5pF8
Input Capacitance: RAS#, CAS#, WE#, OE# CI2 7pF8
Input/Output Capacitance: DQ CIO 7pF8
AC ELECTRICAL CHARACTERISTICS
(Notes: 2, 3, 9, 10, 11, 12, 17) (VCC [MIN] ≤ VCC ≤ VCC [MAX])
AC CHARACTERISTICS -5 -6
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
Access time from column address
Column address setup to CAS# precharge
Column address hold time (referenced to RAS#)
Column address setup time
Row address setup time
Column address to WE# delay time
Access time from CAS#
Column address hold time
CAS# pulse width
CAS# LOW to “don’t care” during Self Refresh
CAS# hold time (CBR Refresh)
CAS# to output in Low-Z
Data output hold after next CAS# LOW
CAS# precharge time
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CAS# setup time (CBR Refresh)
CAS# to WE# delay time
Write command to CAS# lead time
Data-in hold time
Data-in setup time
Output disable
Output Enable
OE# hold time from WE# during
READ-MODIFY-WRITE cycle
OE# HIGH hold from CAS# HIGH
OE# HIGH pulse width
OE# LOW to CAS# HIGH setup time
Output buffer turn-off delay
t
AA 25 30 ns
t
ACH 12 15 ns
t
AR 38 45 ns
t
ASC 0 0 ns
t
ASR 0 0 ns
t
AWD 42 49 ns 13
t
CAC 13 15 ns 14
t
CAH 8 10 ns
t
CAS 8 10,000 10 10,000 ns
t
CHD 15 15 ns
t
CHR 8 10 ns 7
t
CLZ 0 0 ns
t
COH 3 3 ns
t
CP 8 10 ns 15
t
CPA 28 35 ns
t
CRP 5 5 ns
t
CSH 38 45 ns
t
CSR 5 5 ns
t
CWD 28 35 ns 13
t
CWL 8 10 ns
t
DH 8 10 ns 16
t
DS 0 0 ns 16
t
OD 0 12 0 15 ns
t
OE 12 15 ns 17
t
OEH 8 10 ns 18
t
OEHC 5 10 ns 18
t
OEP 5 5 ns
t
OES 4 5 ns
t
OFF 0 12 0 15 ns 20
EDO DRAM
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
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4 MEG x 4
TECHNOLOGY, INC.
AC ELECTRICAL CHARACTERISTICS
(Notes: 2, 3, 9, 10, 11, 12, 17) (VCC [MIN] ≤ VCC ≤ VCC [MAX])
AC CHARACTERISTICS -5 -6
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
OE# setup prior to RAS# during
HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE cycle time
EDO-PAGE-MODE READ-WRITE cycle time
Access time from RAS#
RAS# to column address delay time
Row address hold time
RAS# pulse width
RAS# pulse width (EDO PAGE MODE)
RAS# pulse width during Self Refresh
Random READ or WRITE cycle time
RAS# to CAS# delay time
Read command hold time (referenced to CAS#)
Read command setup time
Refresh period (2,048 cycles)
Refresh period (4,096 cycles)
Refresh period S version
RAS# precharge time
RAS# to CAS# precharge time
RAS# precharge time exiting Self Refresh
Read command hold time (referenced to RAS#)
RAS# hold time
READ WRITE cycle time
RAS# to WE# delay time
Write command to RAS# lead time
Transition time (rise or fall)
Write command hold time
Write command hold time (referenced to RAS#)
WE# command setup time
Output disable delay from WE#
Write command pulse width
WE# pulse to disable at CAS# HIGH
WE# hold time (CBR Refresh)
WE# setup time (CBR Refresh)
t
ORD 0 0 ns
t
PC 20 25 ns
t
PRWC 47 56 ns
t
RAC 50 60 ns 19
t
RAD 9 12 ns 21
t
RAH 9 10 ns
t
RAS 50 10,000 60 10,000 ns
t
RASP 50 125,000 60 125,000 ns
t
RASS 100 100 µs
t
RC 84 104 ns
t
RCD 11 14 ns 22
t
RCH 0 0 ns 23
t
RCS 0 0 ns
t
REF 32 32 ms
t
REF 64 64 ms
t
REF 128 128 ms
t
RP 30 40 ns
t
RPC 5 5 ns
t
RPS 90 105 ns
t
RRH 0 0 ns 23
t
RSH 13 15 ns
t
RWC 116 140 ns
t
RWD 67 79 ns 13
t
RWL 13 15 ns
t
T250250ns
t
WCH 8 10 ns
t
WCR 38 45 ns
t
WCS 0 0 ns 13
t
WHZ 0 12 0 15 ns
t
WP 5 5 ns
t
WPZ 10 10 ns
t
WRH 8 10 ns
t
WRP 8 10 ns
EDO DRAM
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
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TECHNOLOGY, INC.
NOTES
1. All voltages referenced to VSS.
2. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (0˚C ≤ TA ≤ 70˚C) is ensured.
3. An initial pause of 100µs is required after power-up,
followed by eight RAS# refresh cycles (RAS#-ONLY
or CBR with WE# HIGH), before proper device
operation is ensured. The eight RAS# cycle wake-ups
should be repeated any time the tREF refresh
requirement is exceeded.
4. NC pins are assumed to be left floating and are not
tested for leakage.
5. ICC is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
6. Column address changed once each cycle.
7. Enables on-chip refresh and address counters.
8. This parameter is sampled. VCC = VCC
9. AC characteristics assume tT = 2.5ns.
10. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
11. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
12. Measured with a load equivalent to two TTL gates
and 100pF; and VOL = 0.8V and VOH = 2V.
13.tWCS, tRWD, tAWD and tCWD are not restrictive
operating parameters. tWCS applies to EARLY
WRITE cycles. tRWD, tAWD and tCWD apply to
READ-MODIFY-WRITE cycles. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
the entire cycle. If tWCS < tWCS (MIN) and tRWD ≥
t
RWD (MIN), tAWD ≥ tAWD (MIN) and tCWD ≥
t
CWD (MIN), the cycle is a READ-MODIFY-WRITE
and the data output will contain data read from the
selected cell. If neither of the above conditions is met,
the state of data-out is indeterminate. OE# held HIGH
and WE# taken LOW after CAS# goes LOW results in
a LATE WRITE (OE#-controlled) cycle. tWCS, tRWD,
t
CWD and tAWD are not applicable in a LATE
WRITE cycle.
14. Requires that tAA and tRAC are not violated.
15. If CAS# is LOW at the falling edge of RAS#, Q will be
maintained from the previous cycle. To initiate a new
; f = 1 MHz.
MIN
4 MEG x 4
EDO DRAM
cycle and clear the data-out buffer, CAS# must be
pulsed HIGH for tCP.
16. These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading edge
in LATE WRITE or READ-MODIFY-WRITE cycles.
17. If OE# is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not permissible and should not be attempted. Additionally, WE#
must be pulsed during CAS# HIGH time in order to
place I/O buffers in High-Z.
18. LATE WRITE and READ-MODIFY-WRITE cycles
must have both tOD and tOEH met (OE# HIGH
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE cycle.
The DQs will provide the previously read data if
CAS# remains LOW and OE# is taken back LOW
after tOEH is met. If CAS# goes HIGH prior to OE#
going back LOW, the DQs will remain open.
19. Requires that tAA and tCAC are not violated.
20.tOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL. It is referenced from the
rising edge of RAS# or CAS#, whichever occurs last.
21. The tRAD (MAX) limit is no longer specified. tRAD
(MAX) was specified as a reference point only. If
t
RAD was greater than the specified tRAD (MAX)
limit, then access time was controlled exclusively by
t
AA (tRAC and tCAC no longer applied). With or
without the tRAD (MAX) limit, tAA, tRAC and tCAC
must always be met.
22. The tRCD (MAX) limit is no longer specified. tRCD
(MAX) was specified as a reference point only. If
t
RCD was greater than the specified tRCD (MAX)
limit, then access time was controlled exclusively by
t
CAC (tRAC [MIN] no longer applied). With or
without the tRCD limit, tAA and tCAC must always
be met.
23. Either tRCH or tRRH must be satisfied for a READ
cycle.
24. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# is LOW and
OE# is HIGH.
25. The refresh period is extended from 32ms (2K refresh)
or 64ms (4K refresh) to 128ms (both 2K and 4K
refreshes). For 4K refresh, tRC = 31.25µs (128ms/
4,096 rows = 31.25µs) and for 2K refresh, tRC = 62.5µs
(128ms/2,048 rows = 62.5µs).
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
10
Page 11
TECHNOLOGY, INC.
,
,,,
,,
,
,,
,,,,
,,,
,,
,,,,
,,
,,,
READ CYCLE
t
RC
t
RAS
4 MEG x 4
EDO DRAM
t
RP
RAS#VV
CAS#
ADDRVV
WE#
DQ
OE#VV
IH
IL
t
CRP
V
IH
V
IL
t
RAD
ROW
t
RAH
OPEN
t
ASR
IH
IL
V
IH
V
IL
V
OH
V
OL
IH
IL
t
t
t
t
t
RCS
RCD
AR
ASC
ACH
COLUMN
t
CSH
t
RSH
t
CAS
t
CAH
t
AA
t
RAC
t
CAC
t
CLZ
t
RRH
ROW
t
RCH
NOTE 1
t
OFF
VALID DATA
t
OE
t
OD
OPEN
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL MIN MAX MIN MAX UNITS
t
AA 25 30 ns
t
ACH 12 15 ns
t
AR 38 45 ns
t
ASC 0 0 ns
t
ASR 0 0 ns
t
CAC 13 15 ns
t
CAH 8 10 ns
t
CAS 8 10,000 10 10,000 ns
t
CLZ 0 0 ns
t
CRP 5 5 ns
t
CSH 38 45 ns
t
OD 0 12 0 15 ns
t
OE 12 15 ns
NOTE: 1.tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last.
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
-5 -6
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
OFF 0 12 0 15 ns
t
RAC 50 60 ns
t
RAD 9 12 ns
t
RAH 9 10 ns
t
RAS 50 10,000 60 10,000 ns
t
RC 84 104 ns
t
RCD 11 14 ns
t
RCH 0 0 ns
t
RCS 0 0 ns
t
RP 30 40 ns
t
RRH 0 0 ns
t
RSH 13 15 ns
11
Page 12
,,,
,,,
,,,
,
,,
,,,
,,,
,,
RAS#
,,,
,,
,,,
,,,
,,,
,,,
,,,
,,
,,,
,,,
,,,
,,
CAS#
ADDR
WE#
DQ
V
V
V
V
V
V
V
V
V
IOH
V
IOL
TECHNOLOGY, INC.
IH
IL
IH
IL
IH
IL
IH
IL
t
CRP
t
ASR
t
RAD
t
RAH
EARLY WRITE CYCLE
t
RC
t
RAS
t
CSH
t
RSH
t
CAS
t
CAH
t
CWL
t
RWL
t
WCR
t
WCH
t
WP
t
DH
t
ACH
t
WCS
t
RCD
t
t
t
DS
AR
ASC
COLUMNROW
VALID DATA
4 MEG x 4
EDO DRAM
t
RP
ROW
V
IH
OE#
V
IL
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
ACH 12 15 ns
t
AR 38 45 ns
t
ASC 0 0 ns
t
ASR 0 0 ns
t
CAH 8 10 ns
t
CAS 8 10,000 10 10,000 ns
t
CRP 5 5 ns
t
CSH 38 45 ns
t
CWL 8 10 ns
t
DH 8 10 ns
t
DS 0 0 ns
t
RAD 9 12 ns
DON’T CARE
UNDEFINED
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
RAH 9 10 ns
t
RAS 50 10,000 60 10,000 ns
t
RC 84 104 ns
t
RCD 11 14 ns
t
RP 30 40 ns
t
RSH 13 15 ns
t
RWL 13 15 ns
t
WCH 8 10 ns
t
WCR 38 45 ns
t
WCS 0 0 ns
t
WP 5 5 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
12
Page 13
,,,
,
,,,
,,
,,,
,,,,
,
RAS#
,,,
,,,,
,,
CAS#
ADDR
WE#
DQ
OE#
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IOH
V
IOL
V
IH
V
IL
TECHNOLOGY, INC.
READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
t
RWC
t
RAS
t
CSH
t
t
t
CRP
ASR
ROW
t
t
RAD
t
RAH
t
RCD
AR
t
ASC
COLUMN ROW
t
RCS
t
CLZ
t
t
CAH
t
t
RSH
CAS
RWD
CWD
t
AWD
t
AA
t
RAC
t
CAC
t
t
DStDH
VALID D
OE
OUT
t
OD
VALID D
t
ACH
t
CWL
t
RWL
t
WP
IN
t
OEH
4 MEG x 4
EDO DRAM
t
RP
OPENOPEN
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
AA 25 30 ns
t
ACH 12 15 ns
t
AR 38 45 ns
t
ASC 0 0 ns
t
AWD 42 49 ns
t
ASR 0 0 ns
t
CAC 13 15 ns
t
CAH 8 10 ns
t
CAS 8 10,000 10 10,000 ns
t
CLZ 0 0 ns
t
CRP 5 5 ns
t
CSH 38 45 ns
t
CWD 28 35 ns
t
CWL 8 10 ns
t
DH 8 10 ns
t
DS 0 0 ns
DON’T CARE
UNDEFINED
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
OD 0 12 0 15 ns
t
OE 12 15 ns
t
OEH 8 10 ns
t
RAC 50 60 ns
t
RAD 9 12 ns
t
RAH 9 10 ns
t
RAS 50 10,000 60 10,000 ns
t
RCD 11 14 ns
t
RCS 0 0 ns
t
RP 30 40 ns
t
RSH 13 15 ns
t
RWC 116 140 ns
t
RWD 67 79 ns
t
RWL 13 15 ns
t
WP 5 5 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
13
Page 14
TECHNOLOGY, INC.
,,,
,,,
,,
,
,
,
,,
4 MEG x 4
EDO DRAM
EDO-PAGE-MODE READ CYCLE
RAS#
CAS#
ADDR
WE#
DQ
OE#
t
RASP
V
IH
V
IL
t
CRP
V
IH
V
IL
t
ASR
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
t
RAD
t
RAH
t
CSH
t
CAH
t
CAS
t
AA
t
RAC
t
CAC
t
OE
t
OES
t
RCD
t
AR
t
ACH
t
ASC
t
RCS
t
CLZ
t
PC
t
CP
VALID
DATA
t
t
ACH
ASC
t
t
COH
t
CAS
CAH
t
t
t
AA
CPA
CAC
VALID
DATA
t
CP
t
ACH
t
ASC
t
CLZ
t
OEHC
t
t
OD
OD
t
OEP
t
RSH
t
CAS
t
CAH
COLUMNCOLUMNCOLUMNROW ROW
t
AA
t
CPA
t
CAC
VALID
t
OE
t
OES
DATA
t
RP
t
CP
t
RCH
t
RRH
t
OFF
OPENOPEN
t
OD
DON’T CARE
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
AA 25 30 ns
t
ACH 12 15 ns
t
AR 38 45 ns
t
ASC 0 0 ns
t
ASR 0 0 ns
t
CAC 13 15 ns
t
CAH 8 10 ns
t
CAS 8 10,000 10 10,000 ns
t
CLZ 0 0 ns
t
COH 3 3 ns
t
CP 8 10 ns
t
CPA 28 35 ns
t
CRP 5 5 ns
t
CSH 38 45 ns
t
OD 0 12 0 15 ns
t
OE 12 15 ns
UNDEFINED
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
OEHC 5 10 ns
t
OEP 5 5 ns
t
OES 4 5 ns
t
OFF 0 12 0 15 ns
t
PC 20 25 ns
t
RAC 50 60 ns
t
RAD 9 12 ns
t
RAH 9 10 ns
t
RASP 50 125,000 60 125,000 ns
t
RCD 11 14 ns
t
RCH 0 0 ns
t
RCS 0 0 ns
t
RP 30 40 ns
t
RRH 0 0 ns
t
RSH 13 15 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
14
Page 15
TECHNOLOGY, INC.
,
,
,
,,
,
,,,
,
,,,
,,,
,,,,
,,,,
,,,
,,,
,,
,,
4 MEG x 4
EDO DRAM
EDO-PAGE-MODE EARLY WRITE CYCLE
RAS#
CAS#
ADDR
WE#
DQ
OE#
t
RASP
V
IH
V
IL
t
CSH
t
CRP
V
IH
V
IL
t
RAD
ASR
t
RAH
t
V
IH
V
IL
V
IH
V
IL
V
IOH
V
IOL
V
IH
V
IL
t
RCD
t
AR
t
ASC
t
WCS
t
DS
VALID DATA VALID DATA VALID DATA
t
ACH
t
t
CAH
t
t
t
t
t
CAS
CWL
WCH
WP
WCR
DH
t
PC
t
ACH
t
CAH
t
t
CWL
t
WCH
t
WP
t
DH
CAS
t
CP
t
ASC
t
WCS
t
DS
t
CP
t
ASC
t
WCS
t
DS
t
RSH
t
CAS
t
ACH
t
CAH
COLUMNCOLUMNCOLUMNROW ROW
t
CWL
t
WCH
t
WP
t
RWL
t
DH
t
RP
t
CP
DON’T CARE
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
ACH 12 15 ns
t
AR 38 45 ns
t
ASC 0 0 ns
t
ASR 0 0 ns
t
CAH 8 10 ns
t
CAS 8 10,000 10 10,000 ns
t
CP 8 10 ns
t
CRP 5 5 ns
t
CSH 38 45 ns
t
CWL 8 10 ns
t
DH 8 10 ns
t
DS 0 0 ns
UNDEFINED
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
PC 20 25 ns
t
RAD 9 12 ns
t
RAH 9 10 ns
t
RASP 50 125,000 60 125,000 ns
t
RCD 11 14 ns
t
RP 30 40 ns
t
RSH 13 15 ns
t
RWL 13 15 ns
t
WCH 8 10 ns
t
WCR 38 45 ns
t
WCS 0 0 ns
t
WP 5 5 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
15
Page 16
,,,
,,,,
,
,
,,
RAS#
,
CAS#
ADDR
WE#
OE#
4 MEG x 4
TECHNOLOGY, INC.
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
t
RASP
V
IH
V
IL
t
CRP
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IOH
DQ
V
IOL
V
IH
V
IL
t
AR
t
RAD
t
ASRtRAH
ROW COLUMN COLUMN COLUMN ROW
t
RAC
t
RCD
t
ASC
t
RCS
OPEN
t
t
t
t
AA
CAC
CLZ
CSH
VALID
D
t
CP
t
ASCtCAH
t
AA
t
CPA
t
CAC
t
CLZ
IN
t
OD
t
CAS
t
CAH
t
RWD
t
CWL
t
WP
t
AWD
t
CWD
t
DH
t
DS
VALID
D
OUT
t
OE
t
t
PC
t
OE
t
AWD
t
CWD
PRWC
t
CAS
t
t
DS
VALID
D
OUT
CWL
t
WP
t
NOTE 1
t
CP
t
ASCtCAH
t
AA
DH
VALID
D
IN
t
OD
t
CAC
t
CLZ
t
CPA
t
OE
t
AWD
t
CWD
t
VALID
D
t
RSH
t
CAS
DS
OUT
EDO DRAM
t
RP
t
CP
t
RWL
t
CWL
t
WP
t
DH
VALID
D
IN
OPEN
t
OD
t
OEH
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
AA 25 30 ns
t
AR 38 45 ns
t
ASC 0 0 ns
t
ASR 0 0 ns
t
AWD 42 49 ns
t
CAC 13 15 ns
t
CAH 8 10 ns
t
CAS 8 10,000 10 10,000 ns
t
CLZ 0 0 ns
t
CP 8 10 ns
t
CPA 28 35 ns
t
CRP 5 5 ns
t
CSH 38 45 ns
t
CWD 28 35 ns
t
CWL 8 10 ns
t
DH 8 10 ns
t
DS 0 0 ns
NOTE: 1.tPC is for LATE WRITE cycles only.
DON’T CARE
UNDEFINED
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
OD 0 12 0 15 ns
t
OE 12 15 ns
t
OEH 8 10 ns
t
PC 20 25 ns
t
PRWC 47 56 ns
t
RAC 50 60 ns
t
RAD 9 12 ns
t
RAH 9 10 ns
t
RASP 50 125,000 60 125,000 ns
t
RCD 11 14 ns
t
RCS 0 0 ns
t
RP 30 40 ns
t
RSH 13 15 ns
t
RWD 67 79 ns
t
RWL 13 15 ns
t
WP 5 5 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
16
Page 17
TECHNOLOGY, INC.
,
,,
,,,,
,,
,
,,,
,
4 MEG x 4
EDO DRAM
EDO-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
RAS#
CAS#
ADDR
WE#
DQ
OE#
t
RASP
V
IH
V
IL
t
CRP
V
IH
V
IL
t
t
ASRtRAH
V
IH
V
IL
V
IH
V
IL
V
IOH
V
IOL
V
IH
V
IL
RAD
ROW
OPEN
t
RCD
t
CSH
t
AR
t
ASC
COLUMN (A)
t
RCS
t
RAC
t
PC
t
CAS
t
CAH
t
AA
t
CAC
t
OE
t
CP
t
ASCtCAH
COLUMN (B)
t
CPA
VALID DATA (A)
t
CAS
t
AA
t
t
COH
CAC
t
RCH
t
PC
t
WHZ
DATA (B)
VALID
t
CP
t
WCS
t
ASCtCAH
COLUMN (N)
tDSt
VALID DATA
t
RSH
t
CAS
t
ACH
t
WCH
DH
IN
t
RP
t
CP
ROW
DON’T CARE
TIMING PARAMETERS
SYMBOL MIN MAX MIN MAX UNITS
t
AA 25 30 ns
t
ACH 12 15 ns
t
AR 38 45 ns
t
ASC 0 0 ns
t
ASR 0 0 ns
t
CAC 13 15 ns
t
CAH 8 10 ns
t
CAS 8 10,000 10 10,000 ns
t
COH 3 3 ns
t
CP 8 10 ns
t
CPA 28 35 ns
t
CRP 5 5 ns
t
CSH 38 45 ns
t
DH 8 10 ns
t
DS 0 0 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
-5 -6
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
OE 12 15 ns
t
PC 20 25 ns
t
RAC 50 60 ns
t
RAD 9 12 ns
t
RAH 9 10 ns
t
RASP 50 125,000 60 125,000 ns
t
RCD 11 14 ns
t
RCH 0 0 ns
t
RCS 0 0 ns
t
RP 30 40 ns
t
RSH 13 15 ns
t
WCH 8 10 ns
t
WCS 0 0 ns
t
WHZ 0 12 0 15 ns
17
UNDEFINED
Page 18
TECHNOLOGY, INC.
,
,
,,
,,,,
,,,
,,
,,,,
,
,,,
4 MEG x 4
EDO DRAM
READ CYCLE
(With WE#-controlled disable)
RAS#VV
CAS#
ADDRVV
WE#
V
DQ
V
OE#VV
V
V
V
V
OH
OL
IH
IL
t
CRP
IH
IL
t
RAD
ROW
t
RAH
OPEN
t
ASR
IH
IL
IH
IL
IH
IL
t
t
RCS
RCD
t
AR
t
ASC
COLUMN
t
CSH
t
CAS
t
CAH
t
AA
t
RAC
t
CAC
t
CLZ
t
CP
t
ASC
COLUMN
t
t
WPZ
t
WHZ
t
RCS
OPEN
t
CLZ
RCH
VALID DATA
t
OE
t
OD
DON’T CARE
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
AA 25 30 ns
t
AR 38 45 ns
t
ASC 0 0 ns
t
ASR 0 0 ns
t
CAC 13 15 ns
t
CAH 8 10 ns
t
CAS 8 10,000 10 10,000 ns
t
CLZ 0 0 ns
t
CP 8 10 ns
t
CRP 5 5 ns
t
CSH 38 45 ns
UNDEFINED
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
OD 0 12 0 15 ns
t
OE 12 15 ns
t
RAC 50 60 ns
t
RAD 9 12 ns
t
RAH 9 10 ns
t
RCD 11 14 ns
t
RCH 0 0 ns
t
RCS 0 0 ns
t
WHZ 0 12 0 15 ns
t
WPZ 10 10 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
18
Page 19
,,,
,,,,
,
RAS#
,,,
,
,,
,,
CAS#
ADDR
DQ
V
V
V
V
V
V
V
OH
V
OL
IH
IL
IH
IL
IH
IL
TECHNOLOGY, INC.
t
CRP
t
ASR
RAS#-ONLY REFRESH CYCLE
(OE# and WE# = DON’T CARE)
t
RC
OPEN
ROW
t
RAH
t
RAS
CBR REFRESH CYCLE
(Addresses and OE# = DON’T CARE)
t
RPC
4 MEG x 4
EDO DRAM
t
RP
ROW
RAS#
CAS#
DQ
WE#
t
RP
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
t
RPC
t
CP
t
CSR
t
WRPtWRH
t
RAS
t
CHR
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
ASR 0 0 ns
t
CHR 8 10 ns
t
CP 8 10 ns
t
CRP 5 5 ns
t
CSR 5 5 ns
t
RAH 9 10 ns
t
RPC
t
RP
OPEN
t
CSR
t
WRPtWRH
t
CHR
t
RAS
DON’T CARE
UNDEFINED
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
RAS 50 10,000 60 10,000 ns
t
RC 84 104 ns
t
RP 30 40 ns
t
RPC 5 5 ns
t
WRH 8 10 ns
t
WRP 8 10 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
19
Page 20
TECHNOLOGY, INC.
,
,,,
,,,
,,,
,,
,,,,
,,,
,,
4 MEG x 4
EDO DRAM
RAS#
CAS#
ADDR
DQ
OE#
HIDDEN REFRESH CYCLE
24
(WE# = HIGH; OE# = LOW)
t
RAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
t
CRP
t
ASR
t
RAH
t
RAD
t
RCD
t
AR
t
ASC
COLUMNROW
t
RAC
t
CAH
t
AA
t
CLZ
t
CAC
t
RSH
t
OE
t
ORD
t
RP
t
RAS
t
CHR
t
OFF
OPENVALID DATAOPEN
t
OD
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
AA 25 30 ns
t
AR 38 45 ns
t
ASC 0 0 ns
t
ASR 0 0 ns
t
CAC 13 15 ns
t
CAH 8 10 ns
t
CHR 8 10 ns
t
CLZ 0 0 ns
t
CRP 5 5 ns
t
OD 0 12 0 15 ns
DON’T CARE
UNDEFINED
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
OE 12 15 ns
t
OFF 0 12 0 15 ns
t
ORD 0 0 ns
t
RAC 50 60 ns
t
RAD 9 12 ns
t
RAH 9 10 ns
t
RAS 50 10,000 60 10,000 ns
t
RCD 11 14 ns
t
RP 30 40 ns
t
RSH 13 15 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
20
Page 21
TECHNOLOGY, INC.
,,
,,
,,,,
,,,,
,,
,,,
,,,
,,,
4 MEG x 4
EDO DRAM
SELF REFRESH CYCLE
(Addresses and OE# = DON’T CARE)
CSR
t
RASS
t
CHD
t
WRH
()(
)
()(
)
()(
)
()(
)
()(
OPEN
)
()(
)
()(
)
RAS#
CAS#
DQ
WE#
t
RP
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
t
RPC
t
CP
t
t
WRP
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
CHD 15 15 ns
t
CP 8 10 ns
t
CSR 5 5 ns
t
RASS 100 100 µs
t
RP 30 40 ns
NOTE 1
t
RPS
t
RPC
NOTE 2
()(
t
WRH
)
t
CP
t
WRP
DON'T CARE
UNDEFINED
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
t
RPC 5 5 ns
t
RPS 90 105 ns
t
WRH 8 10 ns
t
WRP 8 10 ns
NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter Self Refresh mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
21
Page 22
.340 (8.64)
.330 (8.38)
.305 (7.75)
.299 (7.59)
TECHNOLOGY, INC.
24/26-PIN PLASTIC SOJ (300 mil)
DA-2
.679 (17.25)
.673 (17.09)
4 MEG x 4
EDO DRAM
PIN #1 INDEX
SEATING PLANE
.037 (0.94) MAX
DAMBAR PROTRUSION
.050 (1.27) TYP
.600 (15.24) TYP
.032 (0.81)
.026 (0.66)
.020 (0.51)
.015 (0.38)
.142 (3.61)
.132 (3.35)
.109 (2.77)
.094 (2.39)
.040 (1.02)
R
.030 (0.76)
.275 (6.99)
.260 (6.60)
.025 (0.64)
MIN
NOTE: 1. All dimensions in inches (millimeters)
MAX
or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
22
Page 23
TECHNOLOGY, INC.
4 MEG x 4
EDO DRAM
24/26-PIN PLASTIC TSOP (300 mil)
DB-2
PIN #1 INDEX
.050 (1.27)
TYP
.678 (17.23)
.672 (17.07)
.020 (0.50)
.012 (0.30)
.037 (0.95)
.302 (7.67)
.298 (7.57)
.047 (1.20)
MAX
.367 (9.32)
.359 (9.12)
.004 (0.10)
.006 (0.15)
.002 (0.05)
DETAIL A
SEE DETAIL A
.007 (0.18)
.005 (0.13)
.032 (0.80)
TYP
.010 (0.25)
.024 (0.60)
.016 (0.40)
GAGE PLANE
SEATING PLANE
NOTE: 1. All dimensions in inches (millimeters)
MAX
or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900, Micron DataFax: 208-368-5800
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
23
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