Datasheet MT4LC4M16F5-5, MT4LC4M16F5-6 Datasheet (MICRON)

1

4 MEG x 16 FPM DRAM

FEATURES

• Single +3.3V ±0.3V power supply

• Industry-standard x16 pinout, timing, functions, and packages

• 12 row, 10 column addresses

• High-performance CMOS silicon-gate process

• All inputs, outputs and clocks are LVTTL-compatible

• FAST PAGE MODE (FPM) access

• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms

OPTIONS MARKING

• Plastic Package 50-pin TSOP (400 mil) TG

• Timing 50ns access -5 60ns access -6

• Refresh Rate Standard Refresh None

Part Number Example

MT4LC4M16F5TG-5

PIN ASSIGNMENT (Top View)

DRAM

MT4LC4M16F5

For the latest data sheet, please refer to the Micron Web site: www.micron.com/mti/msp/html/ datasheet.html

50-Pin TSOP

KEY TIMING PARAMETERS

SPEED

t

RC

t

RAC

t

PC

t

AA

t

CAC

-5 90ns 50ns 30ns 25ns 13ns

-6 110ns 60ns 35ns 30ns 15ns

V

CC

DQ0 DQ1 DQ2 DQ3

V

CC

DQ4 DQ5 DQ6 DQ7

NC

V

CC

WE#

RAS#

NC NC NC NC

A0 A1 A2 A3 A4 A5

V

CC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26

V

SS

DQ15 DQ14 DQ13 DQ12

V

SS

DQ11 DQ10 DQ9 DQ8

NC V

SS

CASL# CASH# OE# NC NC NC

A11 A10 A9 A8 A7 A6

V

SS

GENERAL DESCRIPTION

The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits organized in a x16 configuration. The MT4LC4M16F5 is functionally organized as 4,194,304 locations containing 16 bits each. The 4,194,304 memory locations are arranged in 4,096 rows by 1,024 columns. During READ or WRITE cycles, each location is uniquely addressed via the address bits: 12 rowaddress bits (A0-A11) and 10 column-address bits (A0A9). In addition, both byte and word accesses are supported via the two CAS# pins (CASL# and CASH#). The CAS# functionality and timing related to address and control functions (e.g., latching column addresses or selecting CBR REFRESH) are such that the internal

CAS# signal is determined by the first external CAS# signal (CASL# or CASH#) to transition LOW and the last to transition back HIGH. The CAS# functionality and timing related to driving or latching data are such that each CAS# signal independently controls the associated eight DQ pins.

The row address is latched by the RAS# signal, then the column address by CAS#. The device provides FASTPAGE-MODE operation, allowing for fast successive data operations (READ, WRITE, or READ-MODIFYWRITE) within a given row.

The MT4LC4M16F5 must be refreshed periodi-

cally in order to retain stored data.

NOTE: 1. The # symbol indicates signal is active LOW.

2

4 MEG x 16 FPM DRAM

FUNCTIONAL BLOCK DIAGRAM

MT4LC4M16F5 (12 row addresses)

A0-

A11

RAS#

12

10

REFRESH

CONTROLLER

NO. 1 CLOCK

GENERATOR

V

DD

V

SS

12

10

COLUMNADDRESS

BUFFER(10)

ROW-

ADDRESS

BUFFERS (12)

4,096

1,024

COLUMN

DECODER

16

REFRESH

COUNTER

ROW SELECT

ROW

DECODER

4,096 x 1,024 x 16

MEMORY

ARRAY

COMPLEMENT

SELECT

1,024 x 16

4,096 x 16

NO. 2 CLOCK

GENERATOR

WE#

OE#

DQ0DQ15

16

DATA-OUT

BUFFER

CASL#

CAS#

CASH#

DATA-IN BUFFER

16

SENSE AMPLIFIERS

I/O GATING

FAST PAGE MODE ACCESS

Each location in the DRAM is uniquely addressable, as mentioned in the General Description. Use of both CAS# signals results in a word access via the 16 I/O pins (DQ0-DQ15). Use of only one of the two results in a BYTE access cycle. CASL# transitioning LOW selects an access cycle for the lower byte (DQ0-DQ7), and CASH# transitioning LOW selects an access cycle for the upper byte (DQ8-DQ15). General byte and word access timing is shown in Figures 1 and 2.

Additionally, both bytes must always be of the same mode of operation if both bytes are active. A CAS# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. For example, an EARLY WRITE on one byte and a LATE WRITE on the other byte are not allowed during the same cycle. However, an EARLY WRITE on one byte and

a LATE WRITE on the other byte, after a CAS# precharge has been satisfied, are permissible.

The WE# signal must be activated to execute a WRITE operation; otherwise a READ operation will be performed. The OE# signal must be activated to enable the DQ output drivers for a read access and can be deactivated to disable output data if necessary.

FAST-PAGE-MODE operations are always initiated with a row address strobed in by the RAS# signal, followed by a column address strobed in by CAS#, just like for single location accesses. However, subsequent column locations within the row may then be accessed at the page mode cycle time. This is accomplished by cycling CAS# while holding RAS# LOW and entering new column addresses with each CAS# cycle. Returning RAS# HIGH terminates the FAST-PAGE-MODE operation.

3

4 MEG x 16 FPM DRAM

STORED

DATA

1 1 0 1 1 1 1 1

RAS#

CASL#

WE#

X = NOT EFFECTIVE (DON'T CARE)

ADDRESS 1ADDRESS 0

0 1 0 1 0 0 0 0

WORD WRITE LOWER BYTE WRITE

CASH#

INPUT DATA

0 0 1 0 0 0 0 0

1 0 1 0 1 1 1 1

X X X X X X X X

INPUT DATA

1 1 0 1 1 1 1 1

INPUT DATA

STORED

DATA

1 1 0 1 1 1 1 1

INPUT DATA

STORED

DATA

0 0 1 0 0 0 0 0

1 0 1 0 1 1 1 1

STORED

DATA

0 0 1 0 0 0 0 0

1 0 1 0 1 1 1 1

X X X X X X X X

1 0 1 0 1 1 1 1

UPPER BYTE (DQ8-DQ15)

OF WORD

LOWER BYTE

(DQ0-DQ7)

OF WORD

Figure 1

WORD and BYTE WRITE Example

DRAM REFRESH

The supply voltage must be maintained at the specified levels, and the refresh requirements must be met in order to retain stored data in the DRAM. The refresh requirements are met by refreshing all rows in the DRAM array at least once every 64ms. The recommended procedure is to execute 4,096 CBR REFRESH cycles, either uniformly spaced or grouped in bursts, every 64ms. The MT4LC4M16F5 internally refreshes one row for every CBR cycle, so executing 4,096 CBR cycles covers all rows. The CBR REFRESH will invoke the internal refresh counter for automatic RAS# address-

ing. Alternatively, RAS#-ONLY REFRESH capability is inherently provided. However, with this method some compatibility issues may become apparent. JEDEC strongly recommends the use of CBR REFRESH for this device.

STANDBY

Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is preconditioned for the next cycle during the RAS# HIGH time.

4

4 MEG x 16 FPM DRAM

STORED

DATA

1 1 0 1 1 1 1 1

RAS#

CASL#

WE#

Z = High-Z

ADDRESS 1ADDRESS 0

0 1 0 1 0 0 0 0

WORD READ LOWER BYTE READ

STORED

DATA

1 1 0 1 1 1 1 1

CASH#

OUTPUT

DATA

1 1 0 1 1 1 1 1

STORED

DATA

1 1 0 1 1 1 1 1

Z Z Z Z Z Z Z Z

OUTPUT

DATA

1 1 0 1 1 1 1 1

OUTPUT

DATA

1 1 0 1 1 1 1 1

OUTPUT

DATA

1 1 0 1 1 1 1 1

STORED

DATA

1 1 0 1 1 1 1 1

UPPER BYTE (DQ8-DQ15)

OF WORD

LOWER BYTE

(DQ0-DQ7)

OF WORD

0 1 0 1 0 0 0 0

Z Z Z Z Z Z Z Z

0 1 0 1 0 0 0 0

Figure 2

WORD and BYTE READ Example

5

4 MEG x 16 FPM DRAM

ABSOLUTE MAXIMUM RATINGS*

Voltage on VCC Relative to VSS ................-1V to +4.6V

Voltage on NC, Inputs or I/O Pins

Relative to VSS ....................................... -1V to +4.6V

Operating Temperature, TA (ambient) ... 0°C to +70°C

Storage Temperature (plastic) ............ -55°C to +150°C

Power Dissipation ................................................... 1W

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1, 5, 6) (VCC = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

SUPPLY VOLTAGE VCC 3 3.6 V INPUT HIGH VOLTAGE:

Valid Logic 1; All inputs, I/Os and any NC VIH 2VCC + 0.3 V 37 INPUT LOW VOLTAGE:

Valid Logic 0; All inputs, I/Os and any NC VIL -0.3 0.8 V 37 INPUT LEAKAGE CURRENT:

Any input at VIN (0V £ VIN £ VCC + 0.3V); II -2 2 µA All other pins not under test = 0V

OUTPUT HIGH VOLTAGE: IOUT = -2mA VOH 2.4–V

OUTPUT LOW VOLTAGE: IOUT = 2mA VOL – 0.4 V

OUTPUT LEAKAGE CURRENT: Any output at VOUT (0V £ VOUT £ VCC + 0.3V); IOZ -5 5 µA DQ is disabled and in High-Z state

IDD OPERATING CONDITIONS AND MAXIMUM LIMITS

(Notes: 1, 2, 3, 5, 6) (VCC = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL SPEED MAX UNITS NOTES

STANDBY CURRENT: TTL IDD1 ALL 1 mA (RAS# = CAS# = VIH)

STANDBY CURRENT: CMOS (RAS# = CAS# ³ VCC - 0.2V; DQs may be left open; IDD2 ALL 500 µA Other inputs: VIN ³ VCC - 0.2V or VIN £ 0.2V)

OPERATING CURRENT: Random READ/WRITE -5 150 Average power supply current IDD3 -6 165 mA 25 (RAS#, CAS#, address cycling: tRC = tRC [MIN])

OPERATING CURRENT: FAST PAGE MODE -5 105 Average power supply current (RAS# = VIL,IDD4 -6 95 mA 25 CAS#, address cycling: tPC = tPC [MIN])

REFRESH CURRENT: RAS# ONLY -5 150 Average power supply current IDD5 -6 165 mA 22 (RAS# cycling, CAS# = VIH: tRC = tRC [MIN])

REFRESH CURRENT: CBR -5 150 Average power supply current IDD6 -6 165 mA 4, 7 (RAS#, CAS#, address cycling: tRC = tRC [MIN])

6

4 MEG x 16 FPM DRAM

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 10, 11, 12, 13) (VCC = +3.3V ±0.3V)

AC CHARACTERISTICS -5 -6 PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

Access time from column address

t

AA 25 30 ns

Column-address hold time (referenced to RAS#)

t

AR 40 45 ns

Column-address setup time

t

ASC 0 0 ns 26

Row-address setup time

t

ASR 0 0 ns

Column address to WE# delay time

t

AWD 48 55 ns 18

Access time from CAS#

t

CAC 13 15 ns 28

Column-address hold time

t

CAH 8 10 ns 26

CAS# pulse width

t

CAS 13 10,000 15 10,000 ns 32, 34

CAS# hold time (CBR Refresh)

t

CHR 15 15 ns 4, 27

Last CAS# going LOW to first CAS# to return HIGH

t

CLCH 5 5 ns 29

CAS# to output in Low-Z

t

CLZ 3 3 ns 26, 28

CAS# precharge time (FAST PAGE MODE)

t

CP 8 10 ns 13, 32

Access time from CAS# precharge

t

CPA 30 35 ns 27

CAS# to RAS# precharge time

t

CRP 5 5 ns 27

CAS# hold time

t

CSH 50 60 ns 27

CAS# setup time (CBR Refresh)

t

CSR 5 5 ns 4, 26

CAS# to WE# delay time

t

CWD 36 40 ns 18, 26

WRITE command to CAS# lead time

t

CWL 13 15 ns 28

Data-in hold time

t

DH 8 10 ns 19, 28

Data-in setup time

t

DS 0 0 ns 19, 28

Output disable

t

OD 3 13 3 15 ns 23, 24, 36

Output enable time

t

OE 13 15 ns 20

OE# hold time from WE# during

t

OEH 13 15 ns 24

READ-MODIFY-WRITE cycle Output buffer turn-off delay

t

OFF 3 13 3 15 ns 17, 23, 28

OE# setup prior to RAS# during HIDDEN REFRESH cycle

t

ORD 0 0 ns

FAST-PAGE-MODE READ or WRITE cycle time

t

PC 30 35 ns 30

FAST-PAGE-MODE READ-WRITE cycle time

t

PRWC 76 85 ns 30

Access time from RAS#

t

RAC 50 60 ns

RAS# to column-address delay time

t

RAD 13 15 ns 15

Row-address hold time

t

RAH 8 10 ns

CAPACITANCE

(Note: 2)

PARAMETER SYMBOL M AX UNITS

Input Capacitance: Address pins CI1 5pF Input Capacitance: RAS#, CAS#, WE#, OE# CI2 7pF Input/Output Capacitance: DQ CIO 7pF

7

4 MEG x 16 FPM DRAM

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 10, 11, 12, 13) (VCC = +3.3V ±0.3V)

AC CHARACTERISTICS -5 -6 PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

RAS# pulse width

t

RAS 50 10,000 60 10,000 ns

RAS# pulse width (FAST PAGE MODE)

t

RASP 50 125,000 6 0 125,000 ns

Random READ or WRITE cycle time

t

RC 90 110 ns

RAS# to CAS# delay time

t

RCD 18 20 ns 14, 26

READ command hold time (referenced to CAS#)

t

RCH 0 0 ns 16, 27

READ command setup time

t

RCS 0 0 ns 26

Refresh period

t

REF 64 64 ms 22

RAS# precharge time

t

RP 30 40 ns

RAS# to CAS# precharge time

t

RPC 0 0 ns

READ command hold time (referenced to RAS#)

t

RRH 0 0 ns 16

RAS# hold time

t

RSH 13 15 ns 35

READ-WRITE cycle time

t

RWC 131 155 ns

RAS# to WE# delay time

t

RWD 73 85 ns 18

WRITE command to RAS# lead time

t

RWL 13 15 ns

Transition time (rise or fall)

t

T250250ns

WRITE command hold time

t

WCH 8 10 ns 35

WRITE command hold time (referenced to RAS#)

t

WCR 40 45 ns

WE# command setup time

t

WCS 0 0 ns 18, 26

WRITE command pulse width

t

WP 8 10 ns

WE# hold time (CBR Refresh)

t

WRH 10 10 ns

WE# setup time (CBR Refresh)

t

WRP 10 10 ns

8

4 MEG x 16 FPM DRAM

NOTES

1. All voltages referenced to VSS.

2. This parameter is sampled. VCC = +3.3V; f = 1

MHz.

3. IDD is dependent on output loading and cycle

rates. Specified values are obtained with minimum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to

indicate cycle time at which proper operation over the full temperature range is ensured.

6. An initial pause of 100µs is required after power-

up, followed by eight RAS# refresh cycles (RAS#ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded.

7. AC characteristics assume tT = 5ns.

8. VIH (MIN) and VIL (MAX) are reference levels for

measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH).

9. In addition to meeting the transition rate

specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.

10. If CAS# = VIH, data output is High-Z.

11. If CAS# = VIL, data output may contain data from

the last valid READ cycle.

12. Measured with a load equivalent to two TTL

gates, 100pF and VOL = 0.8V and VOH = 2V.

13. If CAS# is LOW at the falling edge of RAS#,

output data will be maintained from the previous cycle. To initiate a new cycle and clear the dataout buffer, CAS# must be pulsed HIGH for tCP.

14. The tRCD (MAX) limit is no longer specified.

t

RCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD limit, tAA and tCAC must always be met.

15. The tRAD (MAX) limit is no longer specified.

t

RAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit,

t

AA, tRAC, and tCAC must always be met.

16. Either tRCH or tRRH must be satisfied for a READ cycle.

17.tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL.

18.tWCS, tRWD, tAWD, and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. If tWCS > tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. tRWD, tAWD and tCWD define READ-MODIFY-WRITE cycles. Meeting these limits allows for reading and disabling output data and then applying input data. The values shown were calculated for reference allowing 10ns for the external latching of read data and application of write data. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-controlled) cycle. tWCS,

t

RWD, tCWD, and tAWD are not applicable in a

LATE WRITE cycle.

19. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles.

20. If OE# is tied permanently LOW, LATE WRITE, or READ-MODIFY-WRITE operations are not possible.

21. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH.

22. RAS#-ONLY REFRESH requires that all 4,096 rows be refreshed at least once every 64ms. CBR REFRESH requires that at least 4,096 cycles be completed every 64ms.

23. The DQs go High-Z during READ cycles once tOD or tOFF occur. If CAS# goes HIGH before OE#, the DQs will go High-Z regardless of the state of OE#. If CAS# stays LOW while OE# is brought HIGH, the DQs will go High-Z. If OE# is brought back LOW (CAS# still LOW), the DQs will provide the previously read data.

24. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. If OE# is taken back LOW while CAS# remains LOW, the DQs will remain open.

25. Column address changed once each cycle.

26. The first CASx# edge to transition LOW.

27. The last CASx# edge to transition HIGH.

28. Output parameter (DQx) is referenced to corresponding CAS# input; DQ0-DQ7 by CASL# and DQ8-DQ15 by CASH#.

29. Last falling CASx# edge to first rising CASx# edge.

9

4 MEG x 16 FPM DRAM

NOTES (continued)

30. Last rising CASx# edge to next cycle’s last rising CASx# edge.

31. Last rising CASx# edge to first falling CASx# edge.

32. First DQs controlled by the first CASx# to go LOW.

33. Last DQs controlled by the last CASx# to go HIGH.

34. Each CASx# must meet minimum pulse width.

35. Last CASx# to go LOW.

36. All DQs controlled, regardless CASL# and CASH#.

37. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width £ 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width £ 3ns, and the pulse width cannot be greater than one third of the cycle rate.

10

4 MEG x 16 FPM DRAM

READ CYCLE

t

RRH

t

CLZ

t

CAC

t

RAC

t

AA

VALID DATA

OPEN

t

OFF

t

RCH

ROW

t

RCS

t

ASC

t

RAH

t

RAD

t

AR

t

CAH

t

RCD

t

CAS

t

RSH

t

CSH

t

RP

t

RC

t

RAS

t

CRP

t

ASR

ROW

OPEN

RAS#VV

IH IL

CAS#VV

IH IL

ADDRVV

IH IL

DQ

V V

IOH IOL

V V

IH IL

COLUMN

WE#

DON’T CARE

UNDEFINED

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

OFF 3 13 3 15 ns

t

RAC 50 60 ns

t

RAD 13 15 ns

t

RAH 8 10 ns

t

RAS 50 10,000 60 10,000 ns

t

RC 90 110 ns

t

RCD 18 20 ns

t

RCH 0 0 ns

t

RCS 0 0 ns

t

RP 30 40 ns

t

RRH 0 0 ns

t

RSH 13 15 ns

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

AA 25 30 ns

t

AR 40 45 ns

t

ASC 0 0 ns

t

ASR 0 0 ns

t

CAC 13 15 ns

t

CAH 8 10 ns

t

CAS 13 10,000 15 10,000 ns

t

CLCH 5 5 ns

t

CLZ 3 3 ns

t

CRP 5 5 ns

t

CSH 50 60 ns

t

OD 3 13 3 15 ns

t

OE 13 15 ns

11

4 MEG x 16 FPM DRAM

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

AR 40 45 ns

t

ASC 0 0 ns

t

ASR 0 0 ns

t

CAH 8 10 ns

t

CAS 13 10,000 15 10,000 ns

t

CLCH 5 5 ns

t

CRP 5 5 ns

t

CSH 50 60 ns

t

CWL 13 15 ns

t

DH 8 10 ns

t

DS 0 0 ns

t

RAD 13 15 ns

EARLY WRITE CYCLE

DON’T CARE

UNDEFINED

V V

IH IL

CAS#

VALID DATA

ROW

COLUMNROW

t

DS

t

DH

t

WP

t

WCH

t

WCS

t

WCR

t

RWL

t

CWL

t

CAH

t

ASC

t

RAH

t

ASR

t

RAD

t

AR

t

CAS

t

RSH

t

CSH

t

RCD

t

CRP

t

RAS

t

RC

t

RP

V V

IH IL

ADDR

V V

IH IL

WE#

V V

IH IL

DQ

V V

IOH IOL

RAS#

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

RAH 8 10 ns

t

RAS 50 10,000 60 10,000 ns

t

RC 90 110 ns

t

RCD 18 20 ns

t

RP 30 40 ns

t

RSH 13 15 ns

t

RWL 13 15 ns

t

WCH 8 10 ns

t

WCR 40 45 ns

t

WCS 0 0 ns

t

WP 8 10 ns

12

4 MEG x 16 FPM DRAM

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

AA 25 30 ns

t

AR 40 45 ns

t

ASC 0 0 ns

t

ASR 0 0 ns

t

AWD 48 55 ns

t

CAC 13 15 ns

t

CAH 8 10 ns

t

CAS 13 10,000 15 10,000 ns

t

CLCH 5 5 ns

t

CLZ 3 3 ns

t

CRP 5 5 ns

t

CSH 50 60 ns

t

CWD 36 40 ns

t

CWL 13 15 ns

t

DH 8 10 ns

t

DS 0 0 ns

READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

VALID D

OUT

VALID D

IN

ROW COLUMN ROW

V V

IH IL

CAS#

V V

IH IL

ADDR

V V

IH IL

V V

IH IL

DQ

V V

IOH IOL

V V

IH IL

RAS#

OPENOPEN

t

OE

t

OD

t

CAC

t

RAC

t

AA

t

CLZ

t

DStDH

t

AWD

t

WP

t

RWL

t

CWL

t

CWD

t

RWD

t

RCS

t

ASC

t

CAH

t

AR

t

ASR

t

RAD

t

CRP

t

RCD

t

CAS

t

RSH

t

CSH

t

RAS

t

RWC

t

RP

t

RAH

OE#

t

OEH

WE#

DON’T CARE

UNDEFINED

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

OD 3 13 3 15 ns

t

OE 13 15 ns

t

OEH 13 15 ns

t

RAC 50 60 ns

t

RAD 13 15 ns

t

RAH 8 10 ns

t

RAS 50 10,000 60 10,000 ns

t

RCD 18 20 ns

t

RCS 0 0 ns

t

RP 30 40 ns

t

RSH 13 15 ns

t

RWC 131 155 ns

t

RWD 73 85 ns

t

RWL 13 15 ns

t

WP 8 10 ns

13

4 MEG x 16 FPM DRAM

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

AA 25 30 ns

t

AR 40 45 ns

t

ASC 0 0 ns

t

ASR 0 0 ns

t

CAC 13 15 ns

t

CAH 8 10 ns

t

CAS 13 10,000 15 10,000 ns

t

CLCH 5 5 ns

t

CLZ 3 3 ns

t

CP 8 10 ns

t

CPA 30 35 ns

t

CRP 5 5 ns

t

CSH 50 60 ns

t

OD 3 13 3 15 ns

VALID DATA

COLUMNCOLUMNCOLUMNROW ROW

t

RCS

t

CAH

t

ASC

t

CP

t

CAS

t

RSH

t

CP

t

CAS

t

CP

t

CAS

t

RCD

t

CRP

t

PC

t

CSH

t

RASP

t

RP

t

CAH

t

ASC

t

CAH

t

ASC

t

AR

t

RAH

t

RAD

t

ASR

t

RCS

t

RCH

t

RCH

t

RCS

t

RRH

t

RCH

t

OFF

t

CAC

t

CPA

t

AA

t

CLZ

t

OFF

t

CAC

t

CPA

t

AA

t

CLZ

t

OFF

t

CAC

t

RAC

t

AA

t

CLZ

t

OE

t

OD

t

OE

t

OD

t

OE

t

OD

OPENOPEN

V V

IH IL

CAS#

V V

IH IL

ADDR

V V

IH IL

WE#

V V

IH IL

DQ

V V

IOH IOL

V V

IH IL

RAS#

OE#

DON’T CARE

UNDEFINED

FAST-PAGE-MODE READ CYCLE

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

OE 13 15 ns

t

OFF 3 13 3 15 ns

t

PC 30 35 ns

t

RAC 50 60 ns

t

RAD 13 15 ns

t

RAH 8 10 ns

t

RASP 50 125,000 60 125,000 ns

t

RCD 18 20 ns

t

RCH 0 0 ns

t

RCS 0 0 ns

t

RP 30 40 ns

t

RRH 0 0 ns

t

RSH 13 15 ns

14

4 MEG x 16 FPM DRAM

FAST-PAGE-MODE EARLY WRITE CYCLE

t

DS

t

DH

t

DS

t

DH

t

DS

t

DH

t

WCR

VALID DATA VALID DATA VALID DATA

t

RWL

t

WP

t

CWL

t

WCH

t

WCS

t

WP

t

CWL

t

WCH

t

WCS

t

WP

t

CWL

t

WCH

t

WCS

t

CAH

t

ASC

t

CAH

t

ASC

t

CAH

t

ASC

t

RAH

t

ASR

t

RAD

t

AR

COLUMNCOLUMNCOLUMNROW ROW

t

CP

t

CAS

t

RSH

t

CP

t

CAS

t

CP

t

CAS

t

RCD

t

CRP

t

PC

t

CSH

t

RASP

t

RP

V V

IH IL

CAS#

V V

IH IL

ADDR

V V

IH IL

WE#

V V

IH IL

DQ

V V

IOH IOL

RAS#

OE#

V V

IH IL

DON’T CARE

UNDEFINED

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

PC 30 35 ns

t

RAD 13 15 ns

t

RAH 8 10 ns

t

RASP 50 125,000 60 125,000 ns

t

RCD 18 20 ns

t

RP 30 40 ns

t

RSH 13 15 ns

t

RWL 13 15 ns

t

WCH 8 10 ns

t

WCR 40 45 ns

t

WCS 0 0 ns

t

WP 8 10 ns

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

AR 40 45 ns

t

ASC 0 0 ns

t

ASR 0 0 ns

t

CAH 8 10 ns

t

CAS 13 10,000 15 10,000 ns

t

CLCH 5 5 ns

t

CP 8 10 ns

t

CRP 5 5 ns

t

CSH 50 60 ns

t

CWL 13 15 ns

t

DH 8 10 ns

t

DS 0 0 ns

15

4 MEG x 16 FPM DRAM

FAST-PAGE-MODE READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

DON’T CARE

UNDEFINED

t

OE

t

OE

t

OE

OPEN

D

OUT

VALID

D

IN

VALID

D

OUT

VALID

D

IN

VALID

D

OUT

VALID

D

IN

VALID

OPEN

t

DH

t

DS

t

AA

t

CPA

t

CLZ

t

CAC

t

DH

t

DS

t

AA

t

CPA

t

CLZ

t

CAC

t

DH

t

DS

t

AA

t

CLZ

t

CAC

t

RAC

t

WP

t

CWL

t

RWL

t

CWD

t

AWD

t

WP

t

CWL

t

CWD

t

AWD

t

WP

t

CWL

t

CWD

t

AWD

t

RCS

t

RWD

t

ASRtRAH

t

ASC

t

RAD

t

AR

t

CAH

t

ASCtCAH

t

ASCtCAH

t

CP

t

CAS

t

RSH

t

CP

t

RP

t

RASP

t

CAS

t

CP

t

CAS

t

RCD

t

CSH

t

PCNOTE 1

t

CRP

ROW COLUMN COLUMN COLUMN ROW

V V

IH IL

CAS#

V V

IH IL

ADDR

V V

IH IL

V V

IH IL

DQ

V V

IOH IOL

V V

IH IL

RAS#

OE#

WE#

t

PRWC

t

OEH

t

OD

t

OD

t

OD

NOTE: 1.tPC is for LATE WRITE only.

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

DS 0 0 ns

t

OD 3 13 3 15 ns

t

OE 13 15 ns

t

OEH 13 15 ns

t

PC 30 35 ns

t

PRWC 76 85 ns

t

RAC 50 60 ns

t

RAD 13 15 ns

t

RAH 8 10 ns

t

RASP 50 125,000 60 125,000 ns

t

RCD 18 20 ns

t

RCS 0 0 ns

t

RP 30 40 ns

t

RSH 13 15 ns

t

RWD 73 85 ns

t

RWL 13 15 ns

t

WP 8 10 ns

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

AA 25 30 ns

t

AR 40 45 ns

t

ASC 0 0 ns

t

ASR 0 0 ns

t

AWD 48 55 ns

t

CAC 13 15 ns

t

CAH 8 10 ns

t

CAS 13 10,000 15 10,000 ns

t

CLCH 5 5 ns

t

CLZ 3 3 ns

t

CP 8 10 ns

t

CPA 30 35 ns

t

CRP 5 5 ns

t

CSH 50 60 ns

t

CWD 36 40 ns

t

CWL 13 15 ns

t

DH 8 10 ns

16

4 MEG x 16 FPM DRAM

FAST-PAGE-MODE READ EARLY WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

ROW

VALID

DATA

VALID DATA

OPEN

t

CRP

t

RCD

t

CAS

t

RSH

t

RASP

t

RP

t

PC

t

ASC

t

CAH

t

AR

t

ASR

t

RAD

t

RAH

t

WCS

t

WP

t

RWL

t

RCS

t

DH

t

DS

t

CAC

t

OFF

V V

IH IL

CAS#

V V

IH IL

ADDR

V V

IH IL

RAS#

DQ

V V

OH OL

WE#

V V

IH IL

t

CSH

COLUMN

t

CP

t

CP

t

ASC

t

CAH

t

CWL

t

WCH

t

CLZ

t

AA

RAC

DON’T CARE

UNDEFINED

t

NOTE 1

ROW

COLUMN

t

CAS

NOTE: 1. Do not drive input data prior to output data going High-Z.

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

OFF 3 13 3 15 ns

t

PC 30 35 ns

t

RAC 50 60 ns

t

RAD 13 15 ns

t

RAH 8 10 ns

t

RASP 50 125,000 60 125,000 ns

t

RCD 18 20 ns

t

RCS 0 0 ns

t

RP 30 40 ns

t

RSH 13 15 ns

t

RWL 13 15 ns

t

WCH 8 10 ns

t

WCS 0 0 ns

t

WP 8 10 ns

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

AA 25 30 ns

t

AR 40 45 ns

t

ASC 0 0 ns

t

ASR 0 0 ns

t

CAC 13 15 ns

t

CAH 8 10 ns

t

CAS 13 10,000 15 10,000 ns

t

CLZ 3 3 ns

t

CP 8 10 ns

t

CRP 5 5 ns

t

CSH 50 60 ns

t

CWL 13 15 ns

t

DH 8 10 ns

t

DS 0 0 ns

17

4 MEG x 16 FPM DRAM

RAS#-ONLY REFRESH CYCLE

(OE# and WE# = DON’T CARE)

ROW

V V

IH IL

CAS#

V V

IH IL

ADDR

V V

IH IL

RAS#

t

RC

t

RAS

t

RP

t

CRP

t

ASR

t

RAH

ROW

OPEN

DQ

V V

OH OL

t

RPC

CBR REFRESH CYCLE

(Addresses and OE# = DON’T CARE)

t

RP

V V

IH IL

RAS#

t

RAS

OPEN

t

CHR

t

CSR

V V

IH IL

V V

OH OL

CAS#

DQ

t

RP

t

RAS

t

RPC

t

CSR

t

RPC

t

CHR

t

CP

V V

IH IL

t

WRPtWRH

t

WRPtWRH

WE#

DON’T CARE

UNDEFINED

NOTE 1

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

RAS 50 10,000 60 10,000 ns

t

RC 90 110 ns

t

RP 30 40 ns

t

RPC 0 0 ns

t

WRH 10 10 ns

t

WRP 10 10 ns

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

ASR 0 0 ns

t

CHR 15 15 ns

t

CP 8 10 ns

t

CRP 5 5 ns

t

CSR 5 5 ns

t

RAH 8 10 ns

NOTE: 1. End of first CBR REFRESH cycle.

18

4 MEG x 16 FPM DRAM

HIDDEN REFRESH CYCLE

1

(WE# = HIGH; OE# = LOW)

DON’T CARE

UNDEFINED

t

CLZ

t

OFF

OPENVALID DATAOPEN

COLUMNROW

t

CAC

t

RAC

t

AA

t

CAH

t

ASC

t

RAH

t

ASR

t

RAD

t

AR

t

CRP

t

RCD

t

RSH

t

RAS

t

RC

t

RP

t

CHR

t

RAS

DQx

V V

IOH IOL

V V

IH IL

ADDR

V V

IH IL

V V

IH IL

RAS#

V V

IH IL

t

OE

t

OD

OE#

t

ORD

CASL#/CASH#

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

OE 13 15 ns

t

OFF 3 13 3 15 ns

t

ORD 0 0 ns

t

RAC 50 60 ns

t

RAD 13 15 ns

t

RAH 8 10 ns

t

RAS 50 10,000 60 10,000 ns

t

RCD 18 20 ns

t

RP 30 40 ns

t

RSH 13 15 ns

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

AA 25 30 ns

t

AR 40 45 ns

t

ASC 0 0 ns

t

ASR 0 0 ns

t

CAC 13 15 ns

t

CAH 8 10 ns

t

CHR 15 15 ns

t

CLZ 3 3 ns

t

CRP 5 5 ns

t

OD 3 13 3 15 ns

NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH.

19

4 MEG x 16 FPM DRAM

50-PIN PLASTIC TSOP (400 mil)

.10

10.21

10.11

.45 .30

.80 TYP

50

125

SEE DETAIL A

1.2

MAX

.25

DETAIL A

GAGE PLANE

PIN #1 ID

.20 .25

.18 .13

21.04

20.88

11.86

11.66

.80

TYP

.60 .40

.88

TYP

NOTE: 1. All dimensions in millimeters

MAX

or typical where noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is .25mm per side.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron is a registered trademark of Micron Technology, Inc.

Datasheet MT4LC4M16F5-5, MT4LC4M16F5-6 Datasheet (MICRON)

Specifications and Main Features

Frequently Asked Questions

User Manual