Datasheet MT4LC1M16C3TG-6, MT4LC1M16C3TG-6S, MT4LC1M16C3DJ-6, MT4LC1M16C3DJ-6S Datasheet (MICRON)

1 MEG x 16

V

CC

DQ0
DQ1
DQ2
DQ3

V

CC

DQ4
DQ5
DQ6
DQ7

NC

NC
NC

WE#

RAS#

NC
NC

A0
A1
A2
A3

V

CC

1
2
3
4
5
6
7
8
9
10
11

15
16
17
18
19
20
21
22
23
24
25

50
49
48
47
46
45
44
43
42
41
40

36
35
34
33
32
31
30
29
28
27
26

V

SS

DQ15
DQ14
DQ13
DQ12

V

SS

DQ11
DQ10
DQ9
DQ8

NC

NC
CASL#
CASH#
OE#

A9
A8
A7
A6
A5
A4

V

SS

V

CC

DQ0
DQ1
DQ2
DQ3

V

CC

DQ4
DQ5
DQ6
DQ7

NC
NC

WE#

RAS#

NC
NC

A0
A1
A2
A3

V

CC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

V

SS

DQ15
DQ14
DQ13
DQ12

V

SS

DQ11
DQ10
DQ9
DQ8

NC
CASL#
CASH#
OE#

A9
A8
A7
A6
A5
A4

V

SS

FPM DRAM

FPM DRAM

FEATURES

• JEDEC- and industry-standard x16 timing,
functions, pinouts, and packages

• High-performance, low-power CMOS silicon-gate
process

• Single power supply (+3.3V ±0.3V or 5V ±0.5V)

• All inputs, outputs and clocks are TTL-compatible

• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR) and HIDDEN

• Optional self refresh (S) for low-power data
retention

• BYTE WRITE and BYTE READ access cycles

• 1,024-cycle refresh (10 row, 10 column addresses)

• FAST-PAGE-MODE (FPM) access

OPTIONS MARKING

• Voltage

3.3V LC
5V C

1

MT4C1M16C3, MT4LC1M16C3

For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/datasheets

PIN ASSIGNMENT (Top View)

42-Pin SOJ

44/50-Pin TSOP

• Packages
Plastic SOJ (400 mil) DJ

NOTE: The # symbol indicates signal is active LOW.

Plastic TSOP (400 mil) TG

• Timing
50ns access -5
60ns access -6

• Refresh Rates
Standard Refresh (16ms period) None
Self Refresh (128ms period) S

2

• Operating Temperature Range
Commercial (0oC to +70oC) None
Extended (-20oC to +80oC) ET

Part Number Example:

3

MT4LC1M16C3DJ-5

NOTE: 1. The third field distinguishes the low voltage offering:

KEY TIMING PARAMETERS

SPEEDtRCtRAC

-5 84ns 50ns 20ns 25ns 15ns 30ns

-6 110ns 60ns 35ns 30ns 15ns 40ns

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

LC designates VCC = 3.3V and C designates VCC = 5V.

2. Contact factory for availability.

t

PC

t

AAtCAC

3. Available only on MT4C1M16C3 (5V)

t

RP

1 MEG x 16 FPM DRAM PART NUMBERS

PART NUMBER SUPPLY PACKAGE REFRESH

MT4LC1M16C3DJ-6 3.3V SOJ Standard
MT4LC1M16C3DJ-6 S 3.3V SOJ Self
MT4LC1M16C3TG-6 3.3V TSOP Standard
MT4LC1M16C3TG-6 S 3.3V TSOP Self
MT4C1M16C3DJ-6 5V SOJ Standard
MT4C1M16C3TG-6 5V TSOP Standard

GENERAL DESCRIPTION

The 1 Meg x 16 DRAM is a randomly accessed, solid­state memory containing 16,777,216 bits organized in
a x16 configuration. The 1 Meg x 16 DRAM has both
BYTE WRITE and WORD WRITE access cycles via two
CAS# pins (CASL# and CASH#). These function identi­cally to a single CAS# on other DRAMs in that either
CASL# or CASH# will generate an internal CAS#.

The CAS# function and timing are determined by
the first CAS# (CASL# or CASH#) to transition LOW and

1

GENERAL DESCRIPTION (continued)

the last CAS# to transition back HIGH. Use of only one
of the two results in a BYTE access cycle. CASL#
transitioning LOW selects an access cycle for the lower
byte (DQ0-DQ7), and CASH# transitioning LOW se­lects an access cycle for the upper byte (DQ8-DQ15).

Each bit is uniquely addressed through the 20 ad­dress bits during READ or WRITE cycles. These are
entered ten bits (A0-A9) at a time. RAS# is used to latch
the first ten bits and CAS# the latter ten bits. The CAS#
function is determined by the first CAS# (CASL# or
CASH#) to transition LOW and the last one to transition
back HIGH. The CAS# function also determines
whether the cycle will be a refresh cycle (RAS#-ONLY)
or an active cycle (READ, WRITE, or READ-WRITE) once
RAS# goes LOW.

The CASL# and CASH# inputs internally generate a
CAS# signal that functions identically to a single CAS#
input on other DRAMs. The key difference is that each
CAS# input (CASL# and CASH#) controls its corre-

1 MEG x 16

FPM DRAM

sponding DQ tristate logic (in conjunction with OE#
and WE#). CASL# controls DQ0-DQ7 and CASH# con­trols DQ8-DQ15. The two CAS# controls give the
1 Meg x 16 DRAM BYTE WRITE cycle capabilities.

A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE#
or CAS, whichever occurs last. Taking WE# LOW will
initiate a WRITE cycle, selecting DQ0-DQ15. If WE#
goes LOW prior to CAS# going LOW, the output pin(s)
remain open (High-Z) until the next CAS# cycle. If WE#
goes LOW after CAS# goes LOW and data reaches the
output pins, data-out (Q) is activated and retains the
selected cell data as long as CAS# and OE# remain LOW
(regardless of WE# or RAS#). This late WE# pulse re­sults in a READ-WRITE cycle.

The 16 data inputs and 16 data outputs are routed
through 16 pins using common I/O. Pin direction is
controlled by OE# and WE#.

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

WE#

CASL#

CASH#

10

10

NO. 2 CLOCK

GENERATOR

COLUMN-

ADDRESS

BUFFER

REFRESH

CONTROLLER

REFRESH

COUNTER

10

ROW-

ADDRESS

BUFFERS (10)

CAS#

FUNCTIONAL BLOCK DIAGRAM

DATA-IN BUFFER

COLUMN

10

DECODER

1,024

SENSE AMPLIFIERS

I/O GATING

1,024 x 16

10

ROW

DECODER

1,024

1,024 x 1,024 x 16

MEMORY

ARRAY

DQ0

16

DQ15

DATA-OUT

BUFFER

16

16

OE#

RAS#

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

NO. 1 CLOCK

GENERATOR

2

V

DD

V

SS

1 MEG x 16

FPM DRAM

GENERAL DESCRIPTION (continued)

The MT4LC1M16C3 must be refreshed periodically

in order to retain stored data.

FAST PAGE MODE ACCESS

FAST-PAGE-MODE operations allow faster data op­erations (READ, WRITE or READ-MODIFY-WRITE)
within a row-address-defined (A0-A9) page boundary.
The FAST-PAGE-MODE cycle is always initiated with a
row address strobed in by RAS#, followed by a column
address strobed in by CAS#. Additional columns may
be accessed by providing valid column addresses,
strobing CAS# and holding RAS# LOW, thus executing
faster memory cycles. Returning RAS# HIGH termi­nates the FAST-PAGE-MODE operation.

Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standbylevel. The chip is also preconditioned for the
next cycle during the RAS# HIGH time. Memory cell
data is retained in its correct state by maintaining power

WORD WRITE LOWER BYTE WRITE

RAS#

and executing anyRAS# cycle (READ, WRITE) or RAS#
REFRESH cycle (RAS# ONLY, CBR or HIDDEN) so that
all 1,024 combinations of RAS# addresses (A0-A9) are
executed at least every 16ms (128ms on the “S” ver­sion), regardless of sequence. The CBR REFRESH cycle
will also invoke the refresh counter and controller for
row-address control.

BYTE ACCESS CYCLE

The BYTE WRITEs and BYTE READs are determined
by the use of CASL# and CASH#. Enabling CASL# will
select a lower byte access (DQ0-DQ7), while enabling
CASH# will select an upper byte access (DQ0-DQ15).
Enabling both CASL# and CASH# selects a WORD
WRITE cycle.

The 1 Meg x 16 DRAM may be viewed as two 1 Meg x
8 DRAMs that have common input controls, with the
exception of the CAS# inputs. Figure 1 illustrates the
BYTE WRITE and WORD WRITE cycles. Figure 2 illus­trates BYTE READ and WORD READ cycles.

CASL#

CASH#

WE#

LOWER BYTE

(DQ0-DQ7)

OF WORD

UPPER BYTE
(DQ8-DQ15)

OF WORD

STORED

DATA

X = NOT EFFECTIVE (DON'T CARE)

INPUT
DATA

1
1
0
1
1
1
1
1

0
1
0
1
0
0
0
0

0
0
1
0
0
0
0
0

X
X
X
X
X
X
X
X

ADDRESS 0

INPUT

DATA

STORED

STORED

DATA

DATA

0

0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1
0
1
0
1
1
1
1

1

1

0

0

1

1

0

0

1

1

1

1

1

1

1

1

Figure 1

WORD and BYTE WRITE Example

INPUT
DATA

1
1
0
1
1
1
1
1

X
X
X
X
X
X
X
X

ADDRESS 1

INPUT
DATA

STORED

DATA

1
1
0
1
1
1
1
1

1
0
1
0
1
1
1
1

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

3

1 MEG x 16

FPM DRAM

Additionally, both bytes must always be of the same
mode of operation if both bytes are active. A CAS#
precharge must be satisfied prior to changing modes of
operation between the upper and lower bytes. For ex­ample, an EARLY WRITE on one byte and a LATE WRITE
on the other byte are not allowed during the same cycle.
However, an EARLY WRITE on one byte and a LATE
WRITE on the other byte, after a CAS# precharge has
been satisfied, are permissible.

DRAM REFRESH

Preserve correct memory cell data by maintaining
power and executing any RAS# cycle (READ, WRITE) or
RAS# REFRESH cycle (RAS#-ONLY, CBR or HIDDEN)
so that all 1,024 combinations of RAS# addresses are
executed within tREF (MAX), regardless of sequence.
The CBR and EXTENDED and SELF REFRESH cycles
will invoke the internal refresh counter for automatic
RAS# addressing.

An optional self refresh mode is available on the “S”
version. The self refresh feature is initiated by per­forming a CBR REFRESH cycle and holding RAS# LOW
for the specified tRASS. The “S” option allows the user

WORD READ LOWER BYTE READ

RAS#

the choice of a fully static, low-power data retention
mode or a dynamic refresh mode at the extended re­fresh period of 128ms, or 125µs per row, when using a
distributed CBR REFRESH. This refresh rate can be
applied during normal operation, as well as during a
standby or battery backup mode.

The self refresh mode is terminated by driving
RAS# HIGH for a minimum time of tRPS. This delay
allows for the completion of any internal refresh cycles
that may be in process at the time of the RAS# LOW­to-HIGH transition. If the DRAM controller uses a dis­tributed CBR refresh sequence, a burst refresh is not
required upon exiting self refresh. However, if the
DRAM controller utilizes a RAS#-ONLY or burst CBR
refresh sequence, all 1,024 rows must be refreshed us­ing a minimum tRC refresh rate prior to resuming nor­mal operation.

STANDBY

Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. The chip is preconditioned for the next
cycle during the RAS# HIGH time.

CASL#

CASH#

LOWER BYTE

(DQ0-DQ7)

OF WORD

UPPER BYTE
(DQ8-DQ15)

OF WORD

WE#

STORED

Z = High-Z

DATA

1
1
0
1
1
1
1
1

0
1
0
1
0
0
0
0

OUTPUT

DATA

1
1
0
1
1
1
1
1

0
1
0
1
0
0
0
0

OUTPUT

DATA

1
1
0
1
1
1
1
1

0
1
0
1
0
0
0
0

STORED

DATA

1
1
0
1
1
1
1
1

0
1
0
1
0
0
0
0

STORED

DATA

1
1
0
1
1
1
1
1

0
1
0
1
0
0
0
0

OUTPUT

Figure 2

WORD and BYTE READ Example

DATA

1
1
0
1
1
1
1
1

0
1
0
1
0
0
0
0

ADDRESS 1ADDRESS 0

OUTPUT

DATA

1
1
0
1
1
1
1
1

0
1
0
1
0
0
0
0

STORED

DATA

1
1
0
1
1
1
1
1

0
1
0
1
0
0
0
0

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

4

1 MEG x 16

FPM DRAM

ABSOLUTE MAXIMUM RATINGS*

Voltage on VCC Pin Relative to VSS

3.3V ..................................................... -1V to +4.6V

5V ........................................................... -1V TO +7V

Voltage on NC, Inputs or I/O Pins Relative to V

3.3V ..................................................... -1V to +5.5V

5V ........................................................... -1V TO +7V

Operating Temperature

TA (commercial) ...................................... 0°C to +70°C

TA (extended "ET") ............................ -20°C to +80°C

Storage Temperature (plastic) ............-55°C to +150°C

Power Dissipation ........................................................ 1W

SS

*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1, 5, 6; notes can be found on page 9); VCC (MIN) ≤ VCC ≤ VCC (MAX)

3.3V 5V

PARAMETER/CONDITION SYMBOL MIN MAX MIN MAX UNITS NOTES

SUPPLY VOLTAGE VCC 3 3.6 4.5 5.5 V

INPUT HIGH VOLTAGE:
Valid Logic 1; All inputs, I/Os and any NC VIH 2 5.5 2.4 VCC + 1 V

INPUT LOW VOLTAGE:
Valid Logic 0; All inputs, I/Os and any NC VIL -1.0 0.8 -0.5 0.8 V

INPUT LEAKAGE CURRENT:
Any input at VIN (0V ≤ VIN ≤ VCC + 0.3V); II -2 2 -2 2 µA

All other pins not under test = 0V

OUTPUT HIGH VOLTAGE:
IOUT = -2mA VOH 2.4 – 2.4 – V

OUTPUT LOW VOLTAGE:
IOUT = 2mA VOL – 0.4 – 0.4 V

OUTPUT LEAKAGE CURRENT:
Any output at VOUT [0V ≤ VOUT ≤ VCC (MAX)]; IOZ -5 5 -5 5 µA
DQ is disabled and in High-Z state

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

5

1 MEG x 16

FPM DRAM

ICC OPERATING CONDITIONS AND MAXIMUM LIMITS

(Notes: 1, 2, 3, 5, 6; notes can be found on page 9); VCC (MIN) ≤ VCC ≤ VCC (MAX)

PARAMETER/CONDITION SYMBOL SPEED 3.3V 5V UNITS NOTES

STANDBY CURRENT: TTL ICC1 ALL 1 2 mA
(RAS# = CAS# = VIH)

STANDBY CURRENT: CMOS (non-“S” version only) I
(RAS# = CAS# = other inputs = VCC - 0.2V)

STANDBY CURRENT: CMOS (“S” version only) ICC2 ALL 150 150 µA
(RAS# = CAS# = other inputs = VCC - 0.2V)

OPERATING CURRENT: Random READ/WRITE -5 180 190
Average power supply current I
(RAS#, CAS#, address cycling: tRC = tRC [MIN])

OPERATING CURRENT: FAST PAGE MODE -5 110 120
Average power supply current ICC4 -6 90 110 mA 23
(RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN])

REFRESH CURRENT: RAS#-ONLY -5 180 190
Average power supply current ICC5 -6 170 180 mA
(RAS# cycling, CAS# = VIH: tRC = tRC [MIN])

REFRESH CURRENT: CBR -5 180 180
Average power supply current ICC6 -6 170 180 mA 4, 7
(RAS#, CAS#, address cycling: tRC = tRC [MIN])

REFRESH CURRENT: Extended (“S” version only)
Average power supply current: CAS# = 0.2V or CBR cycling; ICC7 A LL 300 300 µA 4, 7
RAS# = tRAS (MIN); WE# = VCC - 0.2V; A0-A11, OE# and
DIN = VCC - 0.2V or 0.2V (DIN may be left open)

REFRESH CURRENT: Self (“S” version only)
Average power supply current: CBR with RAS# ž ICC8 ALL 300 300 µA 4, 7

t

RASS (MIN) and CAS# held LOW; WE# = VCC - 0.2V;
A0-A11, OE# and DIN = VCC - 0.2V or 0.2V
(DIN may be left open)

CC2 ALL 500 500 µ A

CC3 -6 170 180 mA 23

CAPACITANCE

(Note: 2; notes can be found on page 9);

PARAMETER SYMBOL MAX UNITS

Input Capacitance: Addresses CI1 5pF

Input Capacitance: RAS#, CASL#, CASH#, WE#, OE# CI2 7pF

Input/Output Capacitance: DQ CIO 7pF

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

6

1 MEG x 16

FPM DRAM

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 10, 11, 12; notes can be found on page 9); VCC (MIN) ≤ VCC ≤ VCC (MAX)

AC CHARACTERISTICS -5 -6
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

Access time from column address
Column-address hold time (referenced to RAS#)
Column-address setup time
Row-address setup time
Column address to WE# delay time
Access time from CAS
Column-address hold time
CAS# pulse width
CAS# LOW to “Don’t Care” during Self Refresh
CAS# hold time (CBR Refresh)
Last CAS# going LOW to first CAS# to return HIGH
CAS# to output in Low-Z
CAS# precharge time
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CAS# setup time (CBR Refresh)
CAS# to WE# delay time
WRITE command to CAS# lead time
Data-in hold time
Data-in setup time
Output disable
Output enable
OE# hold time from WE# during

READ-MODIFY-WRITE cycle

Output buffer turn-off delay
OE# setup prior to RAS# during HIDDEN Refresh cycle
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS#
RAS# to column-address delay time
Row-address hold time
RAS# pulse width
RAS# pulse width (FAST PAGE MODE)
RAS# pulse width (Self Refresh)
Random READ or WRITE cycle time
RAS# to CAS# delay time
READ command hold time (referenced to CAS)
READ command setup time
Refresh period (1,024 cycles)
Refresh period (1,024 cycles) “S” version
RAS# precharge time
RAS# to CAS# precharge time
RAS# precharge time (Self Refresh)
READ command hold time (referenced to RAS#)
RAS# hold time
READ-WRITE cycle time

t

AA 25 30 ns

t

AR 38 45 ns

t

ASC 0 0 ns 27

t

ASR 0 0 ns

t

AWD 42 49 ns 18

t

CAC 15 15 ns 29

t

CAH 8 10 ns 27

t

CAS 8 10,000 10 10,000 ns 32, 35

t

CHD 15 15 ns

t

CHR 8 10 ns 4, 28

t

CLCH 10 10 ns 30

t

CLZ 0 0 ns 26, 29

t

CP 8 5 ns 30

t

CPA 28 35 ns 28

t

CRP 5 5 ns 28

t

CSH 38 45 ns 28

t

CSR 5 5 ns 4, 27

t

CWD 28 35 ns 18, 27

t

CWL 8 10 ns 23, 29

t

DH 8 10 ns 19, 29

t

DS 0 0 ns 19, 29

t

OD 0 12 0 15 ns 17, 26, 29

t

OE 12 15 ns 22

t

OEH 8 10 ns 20

t

OFF 0 12 0 15 ns 11, 17, 23

t

ORD 0 0 ns

t

PC 20 25 ns 31

t

PRWC 47 56 ns 31

t

RAC 50 60 ns

t

RAD 9 12 ns 20

t

RAH 9 10 ns

t

RAS 50 10,000 60 10,000 ns

t

RASP 50 125,000 60 125,000 ns

t

RASS 100 100 µs

t

RC 84 104 ns

t

RCD 11 14 ns 14, 27

t

RCH 0 0 ns 16, 28

t

RCS 0 0 ns 27

t

REF 16 16 ms

t

REF 128 128 ms

t

RP 30 40 ns

t

RPC 5 5 ns

t

RPS 90 105 ns

t

RRH 0 0 ns 16

t

RSH 13 15 ns 36

t

RWC 116 140 ns

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

7

1 MEG x 16

FPM DRAM

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 10, 11, 12; notes can be found on page 9); VCC (MIN) ≤ VCC ≤ VCC (MAX)

AC CHARACTERISTICS -5 -6
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

RAS# to WE# delay time
WRITE command to RAS# lead time
Transition time (rise or fall)
WRITE command hold time
WRITE command hold time (referenced to RAS#)
WE# command setup time
WRITE command pulse width
WE# hold time (CBR Refresh)
WE# setup time (CBR Refresh)

t

RWD 67 79 ns 18

t

RWL 13 15 ns

t

T250250ns

t

WCH 8 10 ns 36

t

WCR 38 45 ns

t

WCS 0 0 ns 18, 27

t

WP 5 5 ns

t

WRH 8 10 ns

t

WRP 8 10 ns

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

8

NOTES

1. All voltages referenced to VSS.

2. This parameter is sampled. VCC = +3.3V or 5.0V;
f = 1 MHz.

CC is dependent on output loading. Specified

3. I
values are obtained with minimum cycle time
and the output open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to
indicate cycle time at which proper operation
over the full temperature range (0°C ≤ TA ≤ 70°C)
for commercial and (-20°C ≤ T
extended “ET” is ensured.

6. An initial pause of 100µs is required after power­up, followed by eight RAS# refresh cycles (RAS#­ONLY or CBR), before proper device operation is
ensured. The eight RAS# cycle wake-ups should
be repeated any time the tREF refresh require­ment is exceeded.

7. AC characteristics assume tT = 5ns.

8. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition
times are measured between VIH and VIL (or
between VIL and VIH).

9. In addition to meeting the transition rate
specification, all input signals must transit
between VIH and VIL (or between VIL and VIH) in a
monotonic manner.

10. If CAS# = VIH, data output is High-Z.

11. If CAS# = VIL, data output may contain data from
the last valid READ cycle.

12. Measured with a load equivalent to two TTL
gates, 100pF and VOL = 0.8V and VOH = 2V.

13. If CAS# is LOW at the falling edge of RAS#, Q will
be maintained from the previous cycle. To
initiate a new cycle and clear the Q buffer, CAS#
must be pulsed HIGH for tCP.

14. The tRCD (MAX) limit is no longer specified. tRCD
(MAX) was specified as a reference point only. If

t

RCD was greater than the specified tRCD (MAX)
limit, then access time was controlled exclusively
by tCAC (tRAC [MIN] no longer applied). With or
without the tRCD limit, tAA and tCAC must
always be met.

15. The tRAD (MAX) limit is no longer specified. tRAD
(MAX) was specified as a reference point only. If

t

RAD was greater than the specified tRAD (MAX)
limit, then access time was controlled exclusively
by tAA (tRAC and tCAC no longer applied). With or
without the tRAD (MAX) limit, tAA, tRAC, and

t

CAC must always be met.

16. Either tRCH or tRRH must be satisfied for a READ
cycle.

≤ 80°C) for

A

1 MEG x 16

FPM DRAM

17.tOFF (MAX) defines the time at which the output
achieves the open circuit condition; it is not a
reference to VOH or VOL.

t

WCS, tRWD, tAWD, and tCWD are restrictive

18.
operating parameters in LATE WRITE and READ­MODIFY-WRITE cycles only. If
(MIN), the cycle is an EARLY WRITE cycle and the
data out-put will remain an open circuit through­out the entire cycle. If tRWD ≥ tRWD (MIN),

t

AWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN),
the cycle is a READ WRITE and the data output
will contain data read from the selected cell. If
neither of the above conditions is met, the state
of Q (at access time and until CAS# or OE# goes
back to V

IH) is indeterminate. OE# held HIGH and

WE# taken LOW after CAS# goes LOW result in a
LATE WRITE (OE#-controlled) cycle.

19. These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.

20. During a READ cycle, if OE# is LOW then taken
HIGH before CAS# goes HIGH, Q goes open. If
OE# is tied permanently LOW, LATE WRITE and
READ-MODIFY-WRITE operations are not
permissible and should not be attempted.

21. A HIDDEN REFRESH may also be performed
after a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.

22. All other inputs at 0.2V or VCC - 0.2V.

23. Column address changed once each cycle.

24. LATE WRITE and READ-MODIFY-WRITE cycles
must have both tOD and tOEH met (OE# HIGH
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE
cycle. The DQs will provide the previously read
data if CAS# remains LOW and OE# is taken back
LOW after tOEH is met. If CAS# goes HIGH prior
to OE# going back LOW, the DQs will remain
open.

25. The DQs open during READ cycles once tOD or

t

OFF occur.

26. The 3ns minimum is a parameter guaranteed by
design.

27. The first CASx edge to transition LOW.

28. The last CASx edge to transition HIGH.

29. Output parameter (DQx) is referenced to
corresponding CAS# input; DQ0-DQ7 by CASL#
and DQ8-DQ15 by CASH#.

30. Last falling CASx edge to first rising CASx edge.

31. Last rising CASx edge to next cycle’s last rising
CASx edge.

t

WCS ≥ tWCS

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

9

NOTES (continued)

32. Last rising CASx edge to first falling CASx edge.

33. First DQs controlled by the first CASx to go LOW.

34. Last DQs controlled by the last CASx to go HIGH.

35. Each CASx must meet minimum pulse width.

36. Last CASx to go LOW.

1 MEG x 16

FPM DRAM

37. All DQs controlled, regardless CASL# and CASH#.

38. If OE# is tied permanently LOW, LATE WRITE, or
READ-MODIFY-WRITE operations are not
permissible and should not be attempted.

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

10

RAS#VV

1 MEG x 16

FPM DRAM

READ CYCLE

t

RC

t

RAS

IH
IL

t

CRP

t

RCD

t

t

t

CSH

RSH

CAS

t

CLCH

t

t

RP

RRH

CASL#/CASH#

ADDRVV

WE#

DQ

OE#VV

V

IH

V

IL

t

RAD

ROW

t

RAH

OPEN

t

ASR

IH
IL

V

IH

V

IL

V

IOH

V

IOL

IH
IL

t

t

t

RCS

AR

ASC

COLUMN

t

CAH

t

AA

t

RAC

t

CAC

t

CLZ

ROW

t

RCH

t

OFF

VALID DATA

t

OE

t

OD

OPEN

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

A A 25 30 n s

t

A R 38 45 n s

t

ASC 0 0 ns

t

ASR 0 0 ns

t

C AC 15 15 n s

t

CAH 8 10 ns

t

CAS 8 10,000 10 10,000 ns

t

CLCH 10 10 ns

t

CLZ 0 0 ns

t

CRP 5 5 ns

t

C SH 38 45 n s

t

OD 0 12 0 15 ns

t

OE 12 15 n s

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

SYMBOL MIN MAX MIN MAX UNITS

t

OFF 0 12 0 15 ns

t

R AC 50 60 n s

t

RAD 9 12 ns

t

RAH 9 10 ns

t

RAS 50 10,000 60 10,000 ns

t

RC 84 104 ns

t

R CD 11 14 n s

t

RCH 0 0 ns

t

RCS 0 0 ns

t

RP 30 40 n s

t

RRH 0 0 ns

t

RSH 13 15 ns

11

-5 -6

RAS#

CASL#/CASH#

ADDR

WE#

1 MEG x 16

FPM DRAM

EARLY WRITE CYCLE

t

RC

t

RAS

V

IH

V

IL

t

CRP

V

IH

V

IL

t

RAD

t

ASR

V

IH

V

IL

V

IH

V

IL

t

RAH

t

WCS

t

t

RCD

t

AR

t

ASC

DS

COLUMNROW

t

CSH

t

RSH

t

CAS

t

CAH

t

CWL

t

RWL

t

WCR

t

WCH

t

WP

t

DH

t

CLCH

t

RP

ROW

V

IOH

DQ

V

IOL

V

IH

OE#

V

IL

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

A R 38 45 n s

t

ASC 0 0 ns

t

ASR 0 0 ns

t

CAH 8 10 ns

t

CAS 8 10,000 10 10,000 ns

t

CLCH 10 10 ns

t

CRP 5 5 ns

t

C SH 38 45 n s

t

CWL 8 10 ns

t

DH 8 10 ns

t

DS 0 0 ns

t

RAD 9 12 ns

VALID DATA

DON’T CARE

UNDEFINED

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

RAH 9 10 ns

t

RAS 50 10,000 60 10,000 ns

t

RC 84 104 ns

t

R CD 11 14 n s

t

RP 30 40 n s

t

RSH 13 15 ns

t

R WL 13 15 n s

t

WCH 8 10 ns

t

W CR 38 45 n s

t

WCS 0 0 ns

t

WP 5 5 ns

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

12

RAS#

CASL#/CASH#

ADDR

WE#

DQ

OE#

1 MEG x 16

FPM DRAM

READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

t

RWC

t

RAS

V

IH

V

IL

t

CRP

V

IH

V

IL

t

ASR

V

IH

V

IL

V

IH

V

IL

V

IOH

V

IOL

V

IH

V

IL

t

AR

t

RAD

t

RAH

ROW COLUMN ROW

t

RCD

t

ASC

t

RCS

t

CLZ

t

t

t

t

CAH

t

CSH

RSH

CAS

t

RWD

CWD

t

AWD

t

t

t

AA

RAC

CAC

t

OE

VALID D

t

CLCH

OUT

t

OD

t

DStDH

VALID D

t

CWL

t

RWL

t

WP

IN

t

OEH

t

RP

OPENOPEN

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

A A 25 30 n s

t

A R 38 45 n s

t

ASC 0 0 ns

t

ASR 0 0 ns

t

A WD 42 49 n s

t

C AC 15 15 n s

t

CAH 8 10 ns

t

CAS 8 10,000 10 10,000 ns

t

CLCH 10 10 ns

t

CLZ 0 0 ns

t

CRP 5 5 ns

t

C SH 38 45 n s

t

CWD 28 35 ns

t

CWL 8 10 ns

t

DH 8 10 ns

t

DS 0 0 ns

DON’T CARE

UNDEFINED

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

OD 0 12 0 15 ns

t

OE 12 15 n s

t

OEH 8 10 ns

t

R AC 50 60 n s

t

RAD 9 12 ns

t

RAH 9 10 ns

t

RAS 50 10,000 60 10,000 ns

t

R CD 11 14 n s

t

RCS 0 0 ns

t

RP 30 40 n s

t

RSH 13 15 ns

t

RW C 116 140 ns

t

RWD 67 79 ns

t

R WL 13 15 n s

t

WP 5 5 ns

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

13

FAST-PAGE-MODE READ CYCLE

1 MEG x 16

FPM DRAM

RAS#

CASL#/CASH#

ADDR

WE#

DQ

OE#

t

RASP

V

IH

V

IL

t

CRP

V

IH

V

IL

t

ASR

V

IH

V

IL

V

IH

V

IL

V

IOH

V

IOL

V

IH

V

IL

t

RAD

t

RAH

t

CSH

t

RCD

t

AR

t

ASC

t

RCS

t

CLZ

t

CAS,

t

CAH

t

t

t

AA

RAC

CAC

t

t

RCH

OE

t

CLCH

t

VALID
DATA

OFF

t

OD

t

PC

t

CP

t

ASC

t

CLZ

t

CAS,

t

CAH

t

RCS

t

t

t

AA

CPA

CAC

t

t

OE

t

RCH

CLCH

VALID

DATA

t

CP

t

ASC

t

OFF

t

CLZ

t

OD

t

RSH

t

t

CLCH

CAS,

t

CAH

COLUMNCOLUMNCOLUMNROW ROW

t

RCS

t

AA

t

CPA

t

CAC

VALID
DATA

t

t

OE

OD

t

RCH

t

RP

t

CP

t

RRH

t

OFF

OPENOPEN

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

A A 25 30 n s

t

A R 38 45 n s

t

ASC 0 0 ns

t

ASR 0 0 ns

t

C AC 15 15 n s

t

CAH 8 10 ns

t

CAS 8 10,000 10 10,000 ns

t

CLCH 10 10 ns

t

CLZ 0 0 ns

t

CP 8 5 ns

t

CP A 28 35 ns

t

CRP 5 5 ns

t

C SH 38 45 n s

t

OD 0 12 0 15 ns

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

SYMBOL MIN MAX MIN MAX UNITS

t

OE 12 15 n s

t

OFF 0 12 0 15 ns

t

PC 20 25 n s

t

R AC 50 60 n s

t

RAD 9 12 ns

t

RAH 9 10 ns

t

RAS P 50 125,000 60 125,000 ns

t

R CD 11 14 n s

t

RCH 0 0 ns

t

RCS 0 0 ns

t

RP 30 40 n s

t

RRH 0 0 ns

t

RSH 13 15 ns

14

-5 -6

FAST-PAGE-MODE EARLY WRITE CYCLE

1 MEG x 16

FPM DRAM

RAS#

CASL#/CASH#

ADDR

WE#

DQ

OE#

t

RASP

V

IH

V

IL

t

CRP

V

IH

V

IL

t

ASR

V

IH

V

IL

V

IH

V

IL

V

IOH

V

IOL

V

IH

V

IL

t

RAH

t

RAD

t

CSH

t

RCD

t

AR

t

ASC

t

WCS

t

DS

VALID DATA VALID DATA VALID DATA

t

t

CAS,

CAH

t

t

t

t

t

CWL

WCH

WP

WCR

DH

t

CLCH

t

PC

t

CP

t

ASC

t

WCS

t

DS

t

CAS,

t

CAH

t

CWL

t

WCH

t

WP

t

DH

t

CLCH

t

CP

t

ASC

t

WCS

t

DS

t

RSH

t

t

CLCH

CAS,

t

CAH

COLUMNCOLUMNCOLUMNROW ROW

t

CWL

t

WCH

t

WP

t

RWL

t

DH

t

RP

t

CP

DON’T CARE

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

A R 38 45 n s

t

ASC 0 0 ns

t

ASR 0 0 ns

t

CAH 8 10 ns

t

CAS 8 10,000 10 10,000 ns

t

CLCH 10 10 ns

t

CP 8 5 ns

t

CRP 5 5 ns

t

C SH 38 45 n s

t

CWL 8 10 ns

t

DH 8 10 ns

t

DS 0 0 ns

UNDEFINED

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

PC 20 25 n s

t

RAD 9 12 ns

t

RAH 9 10 ns

t

RAS P 50 125,000 60 125,000 ns

t

R CD 11 14 n s

t

RP 30 40 n s

t

RSH 13 15 ns

t

R WL 13 15 n s

t

WCH 8 10 ns

t

W CR 38 45 n s

t

WCS 0 0 ns

t

WP 5 5 ns

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

15

FAST-PAGE-MODE READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

1 MEG x 16

FPM DRAM

RAS#

CASL#/CASH#

ADDR

WE#

DQ

OE#

t

RASP

V

IH

V

IL

t

CRP

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IOH

V

IOL

V

IH

V

IL

t

AR

t

RAD

t

ASRtRAH

ROW COLUMN COLUMN COLUMN ROW

t

RAC

t

RCD

OPEN

t

CSH

t

ASC

t

RCS

t

AA

t

CAC

t

CLZ

t

OE

t

CAH

t

CAS,

t

RWD

t

AWD

t

CWD

VALID

t

CLCH

t

CWL
t

WP

t

DH

t

DS

VALID

D

D

OUT

t

CP

t

ASCtCAH

t

AA

t

CPA

t

CAC

t

CLZ

IN

t

OD

t

OE

t

PCNOTE 1

t

t

AWD

t

CWD

VALID

CAS,

t

D

DS

OUT

t

t

PRWC

CWL
t

WP

t

DH

t

CLCH

VALID

D

IN

t

OD

t

CP

t

ASCtCAH

t

AA

t

CPA

t

CAC

t

CLZ

t

OE

t

CAS,

t

t

AWD

CWD

t

DS

VALID

D

t

RSH

OUT

t

CLCH

VALID
D

IN

t

RP

t

CP

t

RWL

t

CWL

t

WP

t

DH

OPEN

t

OD

OEH

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

A A 25 30 n s

t

A R 38 45 n s

t

ASC 0 0 ns

t

ASR 0 0 ns

t

A WD 42 49 n s

t

C AC 15 15 n s

t

CAH 8 10 ns

t

CAS 8 10,000 10 10,000 ns

t

CLCH 10 10 ns

t

CLZ 0 0 ns

t

CP 8 5 ns

t

CP A 28 35 ns

t

CRP 5 5 ns

t

C SH 38 45 n s

t

CWD 28 35 ns

t

CWL 8 10 ns

t

DH 8 10 ns

NOTE: 1.tPC is for LATE WRITE only.

DON’T CARE

UNDEFINED

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

DS 0 0 ns

t

OD 0 12 0 15 ns

t

OE 12 15 n s

t

OEH 8 10 ns

t

PC 20 25 n s

t

PRWC 47 56 ns

t

R AC 50 60 n s

t

RAD 9 12 ns

t

RAH 9 10 ns

t

RAS P 50 125,000 60 125,000 ns

t

R CD 11 14 n s

t

RCS 0 0 ns

t

RP 30 40 n s

t

RSH 13 15 ns

t

RWD 67 79 ns

t

R WL 13 15 n s

t

WP 5 5 ns

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

16

RAS#

CASL#/CASH#

ADDR

WE#

OE#

1 MEG x 16

FPM DRAM

FAST-PAGE-MODE READ EARLY WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

t

RASP

V

IH

V

IL

t

t

RCS

t

ASC

t

RAC

t

CSH

AR

COLUMN

t

AA

t

CAS

t

CAH

t

CAC

t

CLZ

t

VALID

DATA

NOTE 1

OFF

t

CRP

V

IH

V

IL

t

ASR

V

IH

V

IL

V

IH

V

IL

V

OH

Q

V

OL

V

IH

V

IL

t

ROW

RAH

t

RAD

OPEN

t

RCD

t

CP

t

PC

t

ASC

COLUMN

t

WCS

t

DS

VALID DATA

t

DH

t

CAH

t

CWL

t

WP

t

WCH

t

CAS

t

RWL

t

RSH

t

RP

t

CP

ROW

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

A A 25 30 n s

t

A R 38 45 n s

t

ASC 0 0 ns

t

ASR 0 0 ns

t

C AC 15 15 n s

t

CAH 8 10 ns

t

CAS 8 10,000 10 10,000 ns

t

CLZ 0 0 ns

t

CP 8 5 ns

t

CRP 5 5 ns

t

C SH 38 45 n s

t

CWL 8 10 ns

t

DH 8 10 ns

t

DS 0 0 ns

NOTE: 1.tPC is for LATE WRITE only.

DON’T CARE

UNDEFINED

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

OFF 0 12 0 15 ns

t

PC 20 25 n s

t

R AC 50 60 n s

t

RAD 9 12 ns

t

RAH 9 10 ns

t

RAS P 50 125,000 60 125,000 ns

t

R CD 11 14 n s

t

RCS 0 0 ns

t

RP 30 40 n s

t

RSH 13 15 ns

t

R WL 13 15 n s

t

WCH 8 10 ns

t

WCS 0 0 ns

t

WP 5 5 ns

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

17

RAS#

CASL#/CASH#

ADDR

RAS#

CASL#/CASH#

DQ

WE#

1 MEG x 16

FPM DRAM

RAS#-ONLY REFRESH CYCLE

(OE# and WE# = DON’T CARE)

t

t

RPC

OPEN

t

OPEN

RC

RP

t

CSR

t

WRPtWRH

t

CHR

t

RPC

t

RAS

t

RP

ROW

t

RAS

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

OH

Q

V

OL

t

CRP

t

ASR

ROW

t

RAH

CBR REFRESH CYCLE

(Addresses and OE# = DON’T CARE)

t

RP

V

IH

V

IL

V

IH

V

IL

V

OH

V

OL

V

IH

V

IL

t

RPC

t

CP

t

CSR

t

WRPtWRH

t

t

CHR

RAS

NOTE 1

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

ASR 0 0 ns

t

CHR 8 10 ns

t

CP 8 5 ns

t

CRP 5 5 ns

t

CSR 5 5 ns

t

RAH 9 10 ns

SYMBOL MIN MAX MIN MAX UNITS

t

RAS 50 60 10,000 ns

t

RC 84 104 ns

t

RP 30 40 n s

t

RPC 5 5 ns

t

WRH 8 10 ns

t

WRP 8 10 ns

NOTE: 1. End of CBR REFRESH cycle.

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

18

-5 -6

1 MEG x 16

FPM DRAM

RAS#

CASL#/CASH#

ADDR

DQx

OE#

HIDDEN REFRESH CYCLE

1

(WE# = HIGH; OE# = LOW)

t

RAS

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IOH

V

IOL

V

IH

V

IL

t

CRP

t

ASR

t

RAH

t

AR

t

RAD

t

RCD

t

ASC

COLUMNROW

t

CAH

t

AA

t

RAC

t

CAC

t

CLZ

t

RSH

t

OE

t

t

RP

ORD

t

RAS

t

CHR

t

OFF

OPENVALID DATAOPEN

t

OD

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

A A 25 30 n s

t

A R 38 45 n s

t

ASC 0 0 ns

t

ASR 0 0 ns

t

C AC 15 15 n s

t

CAH 8 10 ns

t

CHR 8 10 ns

t

CLZ 0 0 ns

t

CRP 5 5 ns

t

OD 0 12 0 15 ns

DON’T CARE

UNDEFINED

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

OE 12 15 n s

t

OFF 0 12 0 15 ns

t

ORD 0 0 ns

t

R AC 50 60 n s

t

RAD 9 12 ns

t

RAH 9 10 ns

t

RAS 50 10,000 60 10,000 ns

t

R CD 11 14 n s

t

RP 30 40 n s

t

RSH 13 15 ns

NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH.

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

19

SELF REFRESH CYCLE

(Addresses and OE# = DON’T CARE)

1 MEG x 16

FPM DRAM

t

RASS

t

CHD

t

WRH

()(

)

()(

)

()(

)

()(

)

()(

OPEN

)

()(

)

()(

)

RAS#

CAS#

DQ

WE#

t

RP

V

IH

V

IL

V

IH

V

IL

V

OH

V

OL

V

IH

V

IL

t

t

RPC

CP

t

t

WRP

CSR

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

C HD 15 15 n s

t

CLCH 10 10 ns

t

CP 8 5 ns

t

CSR 5 5 ns

t

RASS 100 100 µs

NOTE 1

t

t

RPS

RPC

NOTE 2

()(

t

WRH

)

t

CP

t

WRP

DON’T CARE

UNDEFINED

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

t

RP 30 40 n s

t

RPC 5 5 ns

t

RPS 90 105 ns

t

WRH 8 10 ns

t

WRP 8 10 ns

NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode.

2. Once tRPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR refresh is used.

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

20

.445 (11.30)
.435 (11.05)

.405 (10.29)
.399 (10.13)

42-PIN PLASTIC SOJ (400 mil)

1.079 (27.41)

1.073 (27.25)

1 MEG x 16

FPM DRAM

PIN #1 INDEX

SEATING PLANE

.050 (1.27) TYP

1.000 (25.40)

.032 (0.81)
.026 (0.66)

.037 (0.94) MAX
DAMBAR PROTRUSION

NOTE: 1. All dimensions in inches (millimeters)

2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per
side.

.020 (0.51)
.015 (0.38)

MAX

or typical where noted.

MIN

.148 (3.76)
.138 (3.51)

.095 (2.40)
.080 (2.02)

.380 (9.65)
.360 (9.14)

.030 (0.76)

MIN

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

21

44/50-PIN PLASTIC TSOP (400 mil)

1 MEG x 16

FPM DRAM

PIN #1 INDEX

50

1

.031 (0.80)

TYP

.828 (21.04)
.822 (20.88)

.018 (0.45)
.012 (0.30)

.402 (10.21)
.398 (10.11)

25

.047 (1.20)

MAX

.029 (0.75) TYP

.467 (11.86)
.459 (11.66)

.004 (0.10)

SEATING PLANE

.008 (0.20)
.002 (0.05)

DETAIL A

SEE DETAIL A

.007 (0.18)
.005 (0.13)

.010 (0.25)

.024 (0.60)
.016 (0.40)

.032 (0.80)

TYP

NOTE: 1. All dimensions in inches (millimeters)

MAX

or typical where noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per
side.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: [phone]

E-mail: [e-mail], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.

1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.

22