Datasheet MT4C4001JECJ-8-IT, MT4C4001JECJ-8-883C, MT4C4001JECJ-12-IT, MT4C4001JECJ-12-XT, MT4C4001JECJ-7-883C Datasheet (AUSTIN)
...Page 1
DRAM
MT4C4001J
Austin Semiconductor, Inc.
MT4C4001J
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
For more products and information
please visit our web site at
www.austinsemiconductor.com
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-90847
• MIL-STD-883
1 MEG x 4 DRAM
Fast Page Mode DRAM
FEATURES
• Industry standard x4 pinout, timing, functions, and
packages
• High-performance, CMOS silicon-gate process
• Single +5V±10% power supply
• Low-power, 2.5mW standby; 300mW active, typical
• All inputs, outputs, and clocks are fully TTL and CMOS
compatible
• 1,024-cycle refresh distributed across 16ms
• Refresh modes: RAS\-ONLY, CAS\-BEFORE-RAS\
(CBR), and HIDDEN
• FAST PAGE MODE access cycle
• CBR with WE\ a HIGH (JEDEC test mode capable via
WCBR)
OPTIONS MARKING
• Timing
70ns access -7
80ns access -8
100ns access -1 0
120ns access -1 2
• Packages
Ceramic DIP (300 mil) CN No. 103
Ceramic DIP (400 mil) C No. 104
Ceramic LCC* ECN No. 202
Ceramic ZIP CZ No. 400
Ceramic SOJ EC J No. 504
Ceramic Gull Wing ECG No. 600
*NOTE: If solder-dip and lead-attach is desired on LCC
packages, lead-attach must be done prior to the solderdip operation.
PIN ASSIGNMENT
(Top View)
20-Pin DIP (C, CN)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DQ1
DQ2
WE\
RAS\
A9
A0
A1
A2
A3
Vcc
Vss
DQ4
DQ3
CAS\
OE\
A8
A7
A6
A5
A4
1
2
3
4
5
9
10
11
12
13
26
25
24
23
22
18
17
16
15
14
DQ1
DQ2
WE\
RAS\
A9
A0
A1
A2
A3
Vcc
Vss
DQ4
DQ3
CAS\
OE\
A8
A7
A6
A5
A4
20-Pin SOJ (ECJ),
20-Pin LCC (ECN), &
20-Pin Gull Wing (ECG)
GENERAL DESCRIPTION
The MT4C4001J is a randomly accessed solid-state
memory containing 4,194,304 bits organized in a x4
configuration. During READ or WRITE cycles each bit is
uniquely addressed through the 20 address bits which are
entered 10 bits (A0-A9) at a time. RAS\ is used to latch the
first 10 bits and CAS\ the later 10 bits. A READ or WRITE
cycle is selected with the WE\ input. A logic HIGH on WE\
dictates READ mode while a logic LOW on WE\ dictates
WRITE mode. During a WRITE cycle, data-in (D) is latched
by the falling edge of WE\ or CAS\, whichever occurs last. If
WE\ goes LOW prior to CAS\ going LOW, the output pin(s)
remain open (High-Z) until the next CAS\ cycle. If WE\ goes
LOW after data reaches the output pin(s), Qs are activated and
retain the selected cell data as long as CAS\ remains low
(regardless of WE\ or RAS\). This LATE WE\ pulse results in
a READ-WRITE cycle. The four data inputs and four data
outputs are routed through four pins using common I/O and
pin direction is controlled by WE\ and OE\. FAST-PAGEMODE operations allow faster data operations (READ,
WRITE, or READ-MODIFY-WRITE) within a row address
(A0-A9) defined page boundary . The FAST PAGE MODE
(continued)
20-Pin DIP (CZ)
OE\ 1
DQ3 3
Vss 5
DQ2 7
RAS\ 9
A0 11
A2 13
Vcc 15
A5 17
A7 19
2 CAS\
4 DQ4
6 DQ1
8 WE\
10 A9
12 A1
14 A3
16 A4
18 A6
20 A8
Page 2
DRAM
MT4C4001J
Austin Semiconductor, Inc.
MT4C4001J
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
GENERAL DESCRIPTION (cont.)
cycle is always initiated with a row address strobe-in by RAS\
followed by a column address strobed-in by CAS\. CAS\ may
be toggled-in by holding RAS\ LOW and strobing-in different
column addresses, thus executing faster memory cycles.
Returning RAS\ HIGH terminates the FAST PAGE MODE
operation.
Returning RAS\ and CAS\ HIGH terminates a memory cycle
and decreases chip current to a reduced standby level. Also,
the chip is preconditioned for the next cycle during the RAS\
HIGH time. Memory cell data is retained in its corrected
stated by maintaining power and executing any RAS\ cycle
(READ, WRITE, RAS\-ONLY, CAS\-BEFORE-RAS\, or
HIDDEN REFRESH) so that all 1,024 combinations of RAS\
addresses (A0-A9) are executed at least every 16ms,
regardless of sequence. The CBR REFRESH cycle will
invoke the internal refresh counter for automatic RAS\
addressing.
FUNCTIONAL BLOCK DIAGRAM
FAST PAGE MODE
WE\ DQ1
CAS\ DQ2
DQ3
DQ4
OE\
Vcc
A0 Vss
A1
A2
A3
A4
A5
A6
A7
A8
A9
RAS\
NO. 2 CLOCK
GENERATOR
NO. 1 CLOCK
GENERATOR
COLUMN
ADDRESS
BUFFER
REFRESH
CONTROLLER
REFRESH
COUNTER
ROW ADDRESS
BUFFERS (10)
*EARLY-WRITE
DETECTION CIRCUIT
DATA IN
BUFFER
DATA OUT
BUFFER
COLUMN
DECODER
SENSE AMPLIFIERS
I/O GATING
MEMORY
ARRAY
ROW
DECODER
1024
1024 x 4
4
4
4
4
10
10
10
10
10
NOTE: WE\ LOW prior to CAS\ LOW, EW detection circuit output is a HIGH (EARLY-WRITE)
CAS\ LOW prior to WE\ LOW, EW detection circuit output is a LOW (LATE-WRITE)
Page 3
DRAM
MT4C4001J
Austin Semiconductor, Inc.
MT4C4001J
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
TRUTH TABLE
DATA IN/OUT
t
R
t
C
DQ1-DQ4
HH
XXXXX High-Z
L L H L ROW COL Data Out
L L L X ROW COL Data In
LLH
LLH ROW COL Data Out/Data In
1st Cycle L HL H L ROW COL Data Out
2nd Cycle L HL H L n/a COL Data Out
1st Cycle L HL L X ROW COL Data In
2nd Cycle L HL L X n/a COL Data In
1st Cycle L HLHLLH ROW COL Data Out/Data In
2nd Cycle L HLHLLH n/a COL Data Out/Data In
L H X X ROW n/a High-Z
READ LHL L H L ROW COL Data Out
WRITE LHL L L X ROW COL Data In
HL L H X X X High-Z
HIDDEN REFRESH
CAS\-BEFORE-RAS\ REFRESH
FAST-PAGE-MODE
READ-WRITE
FAST-PAGE-MODE
READ
FAST-PAGE-MODE
EARLY-WRITE
RAS\-ONLY REFRESH
Standby
READ
EARLY-WRITE
READ-WRITE
ADDRESSES
FUNCTION RAS\ CAS\ WE\ OE\
Page 4
DRAM
MT4C4001J
Austin Semiconductor, Inc.
MT4C4001J
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Vss.................-1.0V to +7.0V
Storage Temperature.......................................-65oC to +150oC
Power Dissipation.................................................................1W
Short Circuit Output Current...........................................50mA
Lead Temperature (soldering 5 seconds).....................+270oC
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(NOTES: 1, 3, 4, 6, 7) (-55°C < TA < 125°C; VCC = 5V ±10%)
PARAMETER/CONDITION SYM MIN MAX UNITS NOTES
Supply Voltage
V
CC
4.5 5.5 V
Input High (Logic 1) Voltage, All Inputs
V
IH
2.4
V
CC
+0.5
V
Input Low (Logic 0) Voltage, All Inputs
V
IL
-0.5 0.8 V
INPUT LEAKAGE CURRENT
Any Input 0V <
V
IN
< 5.5V Vcc = 5.5V
(All other pints not under test = 0V)
I
I
-5 5 µA
OUTPUT LEAKAGE CURRENT
(Q is Disabled, 0V <
V
OUT
< 5.5V) Vcc = 5.5V
I
OZ
-5 5 µA
V
OH
2.4 V
V
OL
0.4 V
OUTPUT LEVELS
Output High Voltage (I
OUT
= -5mA)
Output Low Voltage (I
OUT
= 4.2mA)
PARAMETER/CONDITION SYM -7 -8 -10 -12 UNITS NOTES
STANDBY CURRENT (TTL)
(RAS\ = CAS\ = V
IH
)
I
CC1
4444mA
STANDBY CURRENT (CMOS)
(RAS\ = CAS\ = V
CC
-0.2V; all other inputs = VCC -0.2V)
I
CC2
2222mA
OPERATING CURRENT: Random READ/WRITE
Average Power-Supply Current
(RAS\, CAS\, Address Cycling: t
RC
= tRC(MIN))
I
CC3
85 75 65 70 mA 3, 4
OPERATING CURRENT: FAST PAGE MODE
Average Power-Supply Current
(RAS\ = V
IL
, CAS\, Address Cycling: tPC = tPC (MIN))
I
CC4
60 50 45 40 mA 3, 4
REFRESH CURRENT: RAS\-ONLY
Average Power-Supply Current
(RAS\ Cycling, CAS\ = V
IH
: tRC = tRC (MIN))
I
CC5
85 75 65 70 mA 3
REFRESH CURRENT: CAS\-BEFORE-RAS\
Average Power-Supply Current
(RAS\, CAS\, Address Cycling: t
RC
= tRC (MIN))
I
CC6
85 75 65 70 mA 3, 5
MAX
Page 5
DRAM
MT4C4001J
Austin Semiconductor, Inc.
MT4C4001J
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
CAPACITANCE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(NOTES: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C < TC < 125°C; VCC = 5V ±10%)
PARAMETER SYM MIN MAX UNITS NOTES
Input Capacitance: A0-A10
C
I1
7pF2
Input Capacitance: RAS\, CAS\, WE\, OE\
C
I2
7pF2
Input/Output Capacitance: DQ
C
IO
8pF2
PARAMETER SYM MIN MA X MIN MAX MIN MAX MIN MAX UNITS NOTES
Random READ or WRITE cycle time
t
RC
130 150 190 220 ns
READ-WRITE cycle time
t
RWC
180 200 240 255 ns
FAST-PAGE-MODE READ or WRITE cycle time
t
PC
40 45 55 70 ns
FAST-PAGE-MODE READ-WRITE cycle time
t
PRWC
90 90 110 140 ns
Access time from RAS\
t
RAC
70 80 90 120 ns 14
Access time from CAS\
t
CAC
20 20 25 30 ns 15
Access time from column address
t
AA
35 40 45 60 ns
Access time from CAS\ precharge
t
CPA
35 40 45 60 ns
RAS\ pulse width
t
RAS
70 10,000 80 10,000 100 10,000 120 100,000 ns
RAS\ pulse width (FAST PAGE MODE)
t
RASP
70 100,000 80 100,000 100 100,000 120 100,000 ns
RAS\ hold time
t
RSH
20 20 25 30 ns
RAS\ precharge time
t
RP
50 60 70 90 ns
CAS\ pulse width
t
CAS
20 10,000 20 10,000 25 10,000 30 ns
CAS\ hold time
t
CSH
70 80 100 120 ns
CAS\ precharge time
t
CPN
10 10 12 15 ns 16
CAS\ precharge time (FAST PAGE MODE)
t
CP
10 10 12 15 ns
RAS\ to CAS\ delay time
t
RCD
20 50 20 60 25 75 25 90 ns 17
CAS\ to RAS\ precharge time
t
CRP
5 5 5 10 ns
Row address setup time
t
ASR
0000ns
Row address hold time
t
RAH
10 10 15 15 ns
RAS\ to column address delay time
t
RAD
15 35 15 40 20 50 20 60 ns 18
Column address setup time
t
ASC
0000ns
Column address hold time
t
CAH
15 15 20 25 ns
Column address hold time (referenced to RAS\)
t
AR
50 60 70 85 ns
Column address to RAS\ lead time
t
RAL
35 40 50 60 ns
Read command setup time
t
RCS
0000ns
Read command hold time (referenced to CAS\)
t
RCH
0000ns19
Read command hold time (referenced to RAS\)
t
RRH
0000ns19
CAS\ to output in Low-Z
t
CLZ
0000ns
Output buffer turn-off delay
t
OFF
0 20 0 20 0 20 0 20 ns 20
WE\ command setup time
t
WCS
0000ns21, 27
-7 -8 -10 -12
Page 6
DRAM
MT4C4001J
Austin Semiconductor, Inc.
MT4C4001J
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(NOTES: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C < TC < 125°C; VCC = 5V ±10%)
PARAMETER SYM MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
Write command hold time
t
WCH
15 15 20 25 ns
Write command hold time (referenced to RAS\)
t
WCR
50 60 70 80 ns
Write command pulse width
t
WP
15 15 20 25 ns
Write command to RAS\ lead time
t
RWL
20 20 25 30 ns
Write commend to CAS\ lead time
t
CWL
20 20 25 30 ns
Data-in setup time
t
DS
0000ns22
Data-in hold time
t
DH
12 15 18 25 ns 22
Data-in hold time (referenced to RAS\)
t
DHR
50 60 70 90 ns
RAS\ to WE\ delay time
t
RWD
95 105 130 140 ns 21
Column address to WE\ delay time
t
AWD
60 65 80 90 ns 21
CAS\ to WE\ delay time
t
CWD
45 45 55 60 ns 21
Transition time (rise or fall)
t
T
3 50 3 50 3 50 3 50 ns
Refresh period (1,024 cycles)
t
REF
16 16 16 16 ns
RAS\ to CAS\ precharge time
t
RPC
0000ns
CAS\ setup time (CAS\-BEFORE-RAS\ REFRESH)
t
CSR
5 101010ns5
CAS\ hold time (CAS\-BEFORE-RAS\ REFRESH)
t
CHR
10 15 20 25 ns 5
WE\ hold time (CAS\-BEFORE-RAS\ REFRESH)
t
WRH
10 10 10 10 ns 25, 28
WE\ setup time (CAS\-BEFORE-RAS\ REFRESH)
t
WRP
10 10 10 10 ns 25, 28
WE\ hold time (WCBR test cycle)
t
WTH
10 10 10 10 ns 25, 28
WE\ setup time (WCBR test cycle)
t
WTS
10 10 10 10 ns 25, 28
OE\ setup prior to RAS during HIDDEN REFRESH cycle
t
ORD
0000ns
Output disable
t
OD
15 20 25 25 ns 27
Output enable
t
OE
15 20 25 25 ns 23
OE\ hold time from WE\ during READ-MODIFY-WRITE cycle
t
OEH
20 20 25 25 ns 26
-7 -8 -10 -12
Page 7
DRAM
MT4C4001J
Austin Semiconductor, Inc.
MT4C4001J
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
NOTES:
1. All voltages referenced to Vss.
2. This parameter is sampled, not 100% tested. Capacitance
is measured with Vcc=5V, f=1 MHz at less than 50mVrms,
TA = 25°C ±3°C, Vbias = 2.4V applied to each input and
output individually with remaining inputs and outputs open.
3. Icc is dependent on cycle rates.
4. Icc is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle time and
the output open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate cycle
time at which proper operation over the full temperature range
(-55°C < TA < 125°C) is assured.
7. An initial pause of 100µs is required after power-up
followed by eight RAS\ refresh cycles (RAS\-ONLY or CBR
with WE\ HIGH) before proper device operation is assured.
The eight RAS\ cycle wake-up should be repeated any time
the 16ms refresh requirement is exceeded.
8. AC characteristics assume tT = 5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times are
measured between VIH and V
IL
(or between VIL and VIH).
10. In addition to meeting the transition rate specification, all
input signals must transit between VIH and VIL (or between
VIL and VIH) in a monotonic manner.
11. If CAS\ = VIH, data outputs (DQs) are High-Z.
12. If CAS\ = VIL, data outputs (DQs) may contain data from
the last valid READ cycle.
13. Measured with a load equivalent to two TTL gates and
100pF.
14. Assumes that t
RCD
< t
RCD
(MAX). If t
RCD
is greater than
the maximum recommended value shown in this table, t
RAC
will increase by the amount that t
RCD
exceeds the value shown.
15. Assumes that t
RCD
> t
RCD
(MAX)
16. If CAS\ is LOW at the falling edge of RAS\, DQs will be
maintained from the previous cycle. To initiate a new cycle
and clear the data out buffer, CAS\ must be pulsed HIGH for
t
CPN
.
17. Operation within the t
RCD
(MAX) limit ensures that t
RAC
(MAX) can be met. t
RCD
(MAX) is specified as a reference
point only; if t
RCD
is greater than the specified t
RCD
(MAX)
limit, then access time is controlled exclusively by t
CAC
.
18. Operation within the t
RAD
(MAX) limit ensures that t
RCD
(MAX) can be met. t
RAD
(MAX) is specified as a reference
point only; if t
RAD
is greater than the specified t
RAD
(MAX)
limit, then access time is controlled exclusively by tAA.
19. Either t
RCH
or t
RRH
must be satisfied for a READ cycle.
20. t
OFF
(MAX) defines the time at which the output achieves
the open circuit conditions and is not referenced to VOH or
VOL.
21. t
WCS
, t
RWD
, t
AWD
, and t
CWD
are not restrictive operating
parameters. t
WCS
applies to EARLY-WRITE cycles. t
RWD
,
t
AWD
, and t
CWD
apply to READ-MODIFY-WRITE cycles.
If t
WCS
> t
WCS
(MIN), the cycle is an EARLY-WRITE cycles
and the data output will remain an open circuit throughout the
entire cycle. If t
RWD
> t
RWD
(MIN), t
AWD
> t
AWD
(MIN) and
t
CWD
> t
CWD
(MIN), the cycle is a READ-MODIFY-WRITE
and the data output will contain data read from the selected
cell. If neither of the above conditions is met, the state of the
data out is indeterminate. OE\ held HIGH and WE\ taken LOW
after CAS\ goes LOW results in a LATE-WRITE (OE\
controlled) cycle. t
WCS
, t
RWD
, t
CWD
, and t
AWD
are not
applicable in a LA TE-WRITE cycle.
22. These parameters are referenced to CAS\ leading edge in
EARL Y-WRITE cycle and WE\ leading edge in LA TE-WRITE
cycles and WE\ leading edge in LATE-WRITE or
READ-MODIFY-WRITE cycle.
23. If OE\ is tied permanently LOW, LATE-WRITE or
READ-MODIFY-WRITE operations are not possible.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE\=LOW and OE\=HIGH.
25. t
WTS
and t
WTH
are setup and hold specifications for the
WE\ pin being held LOW to enable the JEDEC test mode (with
CBR timing constraints). These two parameters are the
inverts of t
WRP
and t
WRH
in the CBR REFRESH cycle.
26. LA TE-WRITE and READ-MODIFY-WRITE cycles must
have both tOD and t
OEH
met (OE\ HIGH during WRITE cycle)
in order to ensure that the output buffers will be open during
the WRITE cycle. The DQs will provide the previously read
data if CAS\ remains LOW and OE\ is taken back LOW after
t
OEH
is met. If CAS\ goes HIGH prior to OE\ going back LOW ,
the DQs will remain open.
27. The DQs open during READ cycles once tOD or t
OFF
occur. If CAS\ goes HIGH first, OE\ becomes a “don’t care.”
If OE\ goes HIGH and CAS\ stays LOW, OE\ is not a “don’t
care;” and the DQs will provide the previously read data if
OE\ is taken back LOW (while CAS\ remains LOW).
28. JEDEC test mode only.
Page 8
DRAM
MT4C4001J
Austin Semiconductor, Inc.
MT4C4001J
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
READ CYCLE
EARLY-WRITE CYCLE
Page 9
DRAM
MT4C4001J
Austin Semiconductor, Inc.
MT4C4001J
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
FAST-PAGE-MODE READ CYCLE
READ-WRITE CYCLE
(LATE-WRITE and READ-MODIFY-WRITE CYCLES)
Page 10
DRAM
MT4C4001J
Austin Semiconductor, Inc.
MT4C4001J
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
FAST-PAGE-MODE EARLY-WRITE CYCLE
FAST-PAGE-MODE READ-WRITE CYCLE
(LATE-WRITE and READ-MODIFY-WRITE CYCLES)
*tPC = LATE-WRITE cycle
t
PRWC
= F AST READ-MODIFY-WRITE cycle
Page 11
DRAM
MT4C4001J
Austin Semiconductor, Inc.
MT4C4001J
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11
RAS\-ONLY REFRESH CYCLE
(ADDR = A0-A9; WE\ = Don’t Care)
CAS\-BEFORE-RAS\ REFRESH CYCLE
(A0-A9, and OE\ = DON’T CARE)
HIDDEN REFRESH CYCLE
24
(WE\ = HIGH, OE\ = LOW)
Page 12
DRAM
MT4C4001J
Austin Semiconductor, Inc.
MT4C4001J
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
4 MEG POWER-UP AND REFRESH
CONSTRAINTS
The EIA/JEDEC 4 Meg DRAM introduces two potential
incompatibilities compared to the previous generation
1 Meg DRAM. The incompatibilities involve refresh and
power-up. Understanding these incompatibilities and
providing for them will offer the designer and system user
greater compatibility between the 1 Meg and 4 Meg.
REFRESH
The most commonly used refresh mode of the 1 Meg is
the CBR (CAS\-BEFORE-RAS\) REFRESH cycle. The CBR
for the 1 Meg specifies the WE\ pin as a “don’t care.” The 4
Meg, on the other hand, specifies the CBR REFRESH mode
with the WE\ pin held at a voltage HIGH level.
A CBR cycle with WE\ LOW will put the 4 Meg into the
JEDEC specified test mode (WCBR).
POWER-UP
The 4 Meg JEDEC test mode constraint may introduce
another problem. The 1 Meg POWER-UP cycle requires a
100µs delay followed by any eight RAS\ cycles. The 4 Meg
POWER-UP is more restrictive in that eight RAS\-ONLY or
CBR REFRESH (WE\ held HIGH) cycles must be used. The
restriction is needed since the 4 Meg may power-up in the
JEDEC specified test mode and must exit out of the test mode.
The only way to exit the 4 Meg JEDEC test mode is with
either a RAS\-ONLY or a CBR REFRESH cycle
(WE\ held HIGH).
SUMMARY
1. The 1 Meg CBR REFRESH allows the WE\ pin to be “don’t
care” while the 4 Meg CBR requires WE\ to be HIGH.
2. The eight RAS\ wake-up cycles on the 1 Meg may be any
valid RAS\ cycle while the 4 Meg may only use RAS\-ONLY
or CBR REFRESH cycles (WE\ held HIGH).
COMPARISON OF 4 MEG TEST MODE AND WCBR TO 1 MEG CBR
Page 13
DRAM
MT4C4001J
Austin Semiconductor, Inc.
MT4C4001J
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13
MECHANICAL DEFINITIONS*
ASI Case #103 (Package Designator CN)
SMD 5962-90847, Case Outline R
NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.
* All measurements are in inches.
D
E
Pin 1
A
Q
L
e
b
b2
S1
eA
c
R
MIN MAX
A --- 0.200
b 0.014 0.026
b2 0.045 0.065
c 0.008 0.018
D --- 1.060
E 0.220 0.310
eA
e
Q 0.015 0.070
L 0.125 0.200
S1 0.005 ---
R 90° 105°
SYMBOL
SMD Specifications
0.100 BSC
0.300 BSC
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Rev. 1.0 9/01
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14
MECHANICAL DEFINITIONS*
ASI Case #104 (Package Designator C)
SMD 5962-90847, Case Outline U
NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.
* All measurements are in inches.
eA
c
A
Q
L
e
b
b2
S1
D
E
D1
Pin 1
MIN MAX
A --- 0.175
b 0.015 0.021
b2 0.045 0.065
c 0.008 0.014
D 0.980 1.030
D1 0.890 0.910
E 0.380 0.410
eA 0.385 0.420
e
Q 0.015 0.060
L 0.125 0.200
S1 --- 0.070
SYMBOL
SMD Specifications
0.100 BSC
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MT4C4001J
Austin Semiconductor, Inc.
MT4C4001J
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
15
MECHANICAL DEFINITIONS*
ASI Case #400 (Package Designator CZ)
SMD 5962-90847, Case Outline N
NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.
* All measurements are in inches.
MIN MAX
A 0.355 0.405
b 0.016 0.023
b2 0.035 0.045
c 0.008 0.015
e 0.045 0.055
eA 0.085 0.115
D 1.035 1.065
E 0.100 0.130
L 0.125 0.200
L1 0.015 0.050
SYMBOL
SMD SPECIFICATIONS
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Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
16
* All measurements are in inches.
ASI Case #202 (Package Designator ECN)
SMD 5962-90847, Case Outline T
NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.
E
D
A
A1
E1
L
e
b
L1
S
R
MIN MAX
A 0.060 0.080
A1
b 0.022 0.028
D 0.343 0.357
E 0.665 0.685
E1 0.590 0.610
e
L 0.045 0.055
L1 0.080 0.100
R 0.006 0.010
S 0.025 0.050
0.050 TYP
SYMBOL
SMD SPECIFICATIONS
0.035 TYP
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Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
17
ASI Case #504 (Package Designator ECJ)
MECHANICAL DEFINITION*
*All measurements are in inches.
A
A1
e
b
D
E
D1
b2
b1
MIN MAX
A 0.120 0.140
A1 0.066 0.078
b 0.022 0.028
b1
b2 0.090 0.11
D 0.665 0.685
D1 0.592 0.608
E 0.345 0.355
E1 0.345 0.360
e 0.045 0.055
L 0.057 0.063
SYMBOL
ASI SPECIFICATIONS
0.050 TYP
L
E1
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Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
18
ASI Case #600 (Package Designator ECG)
MECHANICAL DEFINITION*
*All measurements are in inches.
MIN MAX
A 0.120 0.140
A1 0.066 0.078
b 0.022 0.028
b1
b2 0.090 0.110
D 0.665 0.685
D1 0.592 0.608
E 0.345 0.355
E1 0.482 0.498
E2 0.442 0.458
e 0.045 0.055
e1
L 0.057 0.063
SYMBOL
ASI PACKAGE SPECIFICATIONS
0.050 TYP
0.014 Dia. TYP
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Rev. 1.0 9/01
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19
ORDERING INFORMATION
*AVAILABLE PROCESSES
IT = Industrial T emperature Range -40oC to +85oC
XT = Extended T emperature Range -55oC to +125oC
883C = Full Military Processing -55oC to +125oC
EXAMPLE: MT4C4001JCN-8/883C EXAMPLE: MT4C4001JC-12/883C
Device
Number
Package
T
yp
e
Speed ns Process
Device
Number
Package
T
yp
e
Speed ns Process
MT4C4001J CN -7 /* MT4C4001J C -7 /*
MT4C4001J CN -8 /* MT4C4001J C -8 /*
MT4C4001J CN -10 /* MT4C4001J C -10 /*
MT4C4001J CN -12 /* MT4C4001J C -12 /*
EXAMPLE: MT4C4001JCZ-7/883C EXAMPLE: MT4C4001JECN-10/XT
Device
Number
Package
T
yp
e
Speed ns Process
Device
Number
Package
T
yp
e
Speed ns Process
MT4C4001J CZ -7 /* MT4C4001J ECN -7 /*
MT4C4001J CZ -8 /* MT4C4001J ECN -8 / *
MT4C4001J CZ -10 /* MT4C4001J ECN -10 / *
MT4C4001J CZ -12 /* MT4C4001J ECN -12 / *
EXAMPLE: MT4C4001JECJ-7/IT EXAMPLE: MT4C4001JECG-12/IT
Device
Number
Package
T
yp
e
Speed ns Process
Device
Number
Package
T
yp
e
Speed ns Process
MT4C4001J ECJ -7 /* MT4C4001J ECG -7 /*
MT4C4001J ECJ -8 /* MT4C4001J ECG -8 /*
MT4C4001J ECJ -10 /* MT4C4001J ECG -10 /*
MT4C4001J ECJ -12 /* MT4C4001J ECG -12 /*
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Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
20
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
ASI TO DSCC PART NUMBER
CROSS REFERENCE*
ASI Package Designator CZ
ASI Part # SMD Part #
MT4C4001JCZ-8/883C 5962-9084703MNA
MT4C4001JCZ-10/883C 5962-9084702MNA
MT4C4001JCZ-12/883C 5962-9084701MNA
ASI Package Designator C
ASI Part # SMD Part #
MT4C4001JC-8/883C 5962-9084703MUA
MT4C4001JC-10/883C 5962-9084702MUA
MT4C4001JC-12/883C 5962-9084701MUA
ASI Package Designator CN
ASI Part # SMD Part #
MT4C4001JCN-8/883C 5962-9084703MRA
MT4C4001JCN-10/883C 5962-9084702MRA
MT4C4001JCN-12/883C 5962-9084701MRA
ASI Package Designator ECN
ASI Part # SMD Part #
MT4C4001JECN-8/883C 5962-9084703MTA
MT4C4001JECN-10/883C 5962-9084702MTA
MT4C4001JECN-12/883C 5962-9084701MTA
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