Datasheet MT48LC64M8A2TG-75, MT48LC128M4A2TG-75, MT48LC128M4A2TG-7E, MT48LC64M8A2TG-7E, MT48LC32M16A2TG-7E Datasheet (MICRON)

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Page 1

ADVANCE

‡

‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE

BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

512Mb: x4, x8, x16

SDRAM

KEY TIMING PARAMETERS

SPEED CLOCK ACCESS TIME SETUP HOLD

GRADE FREQUENCY CL = 2* CL = 3* TIME TIME

-7E 143 MHz – 5.4ns 1.5ns 0.8ns

-75 133 MHz – 5.4ns 1.5ns 0.8ns

-7E 133 MHz 5.4ns – 1.5ns 0.8ns

-75 100 MHz 6ns – 1.5ns 0.8ns

128 Meg x 4 64 Meg x 8 32 Meg x 16

Configuration 32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks Refresh Count 8K 8K 8K Row Addressing 8K (A0–A12) 8K (A0–A12) 8K (A0–A12) Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) Column Addressing 4K (A0–A9, A11, A12) 2K (A0–A9, A11) 1K (A0–A9)

SYNCHRONOUS DRAM

MT48LC128M4A2 – 32 Meg x 4 x 4 banks MT48LC64M8A2 – 16 Meg x 8 x 4 banks MT48LC32M16A2 – 8 Meg x 16 x 4 banks

For the latest data sheet, please refer to the Micron Web site:

www.micron.com/dramds

Pin Assignment (Top View)

54-Pin TSOP

FEATURES

• PC100- and PC133-compliant

• Fully synchronous; all signals registered on positive edge of system clock

• Internal pipelined operation; column address can be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes

• Self Refresh Mode

• 64ms, 8,192-cycle refresh

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

OPTIONS MARKING

• Configurations 128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4

64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8 32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16

• WRITE Recovery (tWR)

WR = “2 CLK”

• Plastic Package – OCPL

54-pin TSOP II (400 mil) TG

• Timing (Cycle Time)

7.5ns @ CL = 2 (PC133) -7E

7.5ns @ CL = 3 (PC133) -75

• Self Refresh Standard None Low power L

• Operating Temperature Commercial (0oC to +70oC) None

NOTE: 1. Refer to Micron Technical Note TN-48-05.

2. Off-center parting line.

Part Number Example:

MT48LC32M16A2TG-75

NOTE: The # symbol indicates signal is active LOW. A dash

(–) indicates x8 and x4 pin function is same as x16 pin function.

DQ0

DQ1 DQ2

VssQ

DQ3 DQ4

DQ5 DQ6

VssQ

DQ7

DQML

WE#

CAS# RAS#

CS#

BA0 BA1 A10

A0 A1 A2 A3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28

Vss

DQ15

VssQ

DQ14 DQ13

DQ12 DQ11

VssQ

DQ10 DQ9

DQ8

Vss NC DQMH CLK CKE

A12 A11 A9 A8 A7 A6 A5 A4

Vss

x8x16 x16x8 x4x4

DQ0

DQ1

DQ2

DQ3

DQ0

NC NC

DQ1

DQ7

DQ6

DQ5

DQ4

DQM

DQ3

NC NC

DQ2

DQM

*CL = CAS (READ) latency

512Mb SDRAM PART NUMBERS

PART NUMBER ARCHITECTURE

MT48LC128M4A2TG 128 Meg x 4 MT48LC64M8A2TG 64 Meg x 8 MT48LC32M16A2TG 32 Meg x 16

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512Mb: x4, x8, x16

SDRAM

ADVANCE

page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.

The 512Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation.

The 512Mb SDRAM is designed to operate at 3.3V. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTLcompatible.

SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic columnaddress generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access.

GENERAL DESCRIPTION

The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 134,217,728-bit banks is organized as 8,192 rows by 4,096 columns by 4 bits. Each of the x8’s 134,217,728-bit banks is organized as 8,192 rows by 2,048 columns by 8 bits. Each of the x16’s 134,217,728-bit banks is organized as 8,192 rows by 1,024 columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full

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512Mb: x4, x8, x16

SDRAM

ADVANCE

TABLE OF CONTENTS

Functional Block Diagram – 128 Meg x 4 .................... 4

Functional Block Diagram – 64 Meg x 8 ................... 5

Functional Block Diagram – 32 Meg x 16 ................. 6

Pin Descriptions ........................................................... 7

Functional Description ............................................... 8

Initialization ............................................................ 8

Mode Register .................................................... 8

Burst Length ................................................. 8

Burst Type .................................................... 9

CAS Latency ................................................. 10

Operating Mode ........................................... 10

Write Burst Mode ......................................... 10

Commands.................................................................... 11

Truth Table 1 (Commands and DQM Operation) ............ 11

Command Inhibit ................................................... 12

No Operation (NOP) ............................................... 12

Load Mode Register ................................................ 12

Active ....................................................................... 12

Read ....................................................................... 12

Write ....................................................................... 12

Precharge ................................................................. 12

Auto Precharge ........................................................ 12

Burst Terminate ...................................................... 13

Auto Refresh ............................................................ 13

Self Refresh .............................................................. 13

Operation ...................................................................... 14

Bank/Row Activation .............................................. 14

Reads ....................................................................... 16

Writes ....................................................................... 21

Precharge ................................................................. 23

Power-Down ............................................................ 23

Clock Suspend ......................................................... 24

Burst Read/Single Write ......................................... 24

Concurrent Auto Precharge ................................... 25

Truth Table 2 (CKE) ..................................................... 27

Truth Table 3 (Current State, Same Bank) ...................... 28

Truth Table 4 (Current State, Different Bank) ................. 30

Absolute Maximum Ratings ........................................ 32

DC Electrical Characteristics and Operating

Conditions ................................................................ 32

DD Specifications and Conditions .............................. 32

Capacitance ................................................................... 33

AC Electrical Characteristics (Timing Table) ............ 33

Timing Waveforms

Initialize and Load Mode Register ......................... 36

Power-Down Mode ................................................. 37

Clock Suspend Mode .............................................. 38

Auto Refresh Mode ................................................. 39

Self Refresh Mode ................................................... 40

Reads

Read – Without Auto Precharge ....................... 41

Read – With Auto Precharge ............................. 42

Single Read – Without Auto Precharge ............ 43

Single Read – With Auto Precharge ................. 44

Alternating Bank Read Accesses ...................... 45

Read – Full-Page Burst ...................................... 46

Read – DQM Operation .................................... 47

Writes

Write – Without Auto Precharge ...................... 48

Write – With Auto Precharge ............................ 49

Single Write – Without Auto Precharge ........... 50

Single Write – With Auto Precharge ................. 51

Alternating Bank Write Accesses ..................... 52

Write – Full-Page Burst ..................................... 53

Write – DQM Operation .................................... 54

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512Mb: x4, x8, x16

SDRAM

ADVANCE

FUNCTIONAL BLOCK DIAGRAM

128 Meg x 4 SDRAM

RAS#

CAS#

ROW-

ADDRESS

MUX

CLK

CS#

WE#

CKE

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTER

COMMAND

DECODE

A0-A12,

BA0, BA1

DQM

ADDRESS REGISTER

4096

(x4)

8192

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(8,192 x 4,096 x 4)

BANK0

ROW-

ADDRESS

LATCH

DECODER

8192

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0DQ3

DATA INPUT

DATA

OUTPUT

BANK1

BANK2

BANK3

1 1

REFRESH

COUNTER

Page 5

512Mb: x4, x8, x16

SDRAM

ADVANCE

FUNCTIONAL BLOCK DIAGRAM

64 Meg x 8 SDRAM

RAS#

CAS#

ROW-

ADDRESS

MUX

CLK

CS#

WE#

CKE

CONTROL

LOGIC

COLUMNADDRESS

COUNTER/

LATCH

MODE REGISTER

COMMAND

DECODE

A0-A12,

BA0, BA1

DQM

ADDRESS REGISTER

2048

(x8)

8192

I/O GATING DQM MASK LOGIC READ DATA LATCH

WRITE DRIVERS

COLUMN DECODER

BANK0

MEMORY

ARRAY

(8,192 x 2,048 x 8)

BANK0

ROW-

ADDRESS

LATCH

DECODER

8192

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0DQ7

DATA INPUT

DATA

OUTPUT

BANK1

BANK2

BANK3

1 1

REFRESH

COUNTER

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512Mb: x4, x8, x16

SDRAM

ADVANCE

FUNCTIONAL BLOCK DIAGRAM

32 Meg x 16 SDRAM

RAS#

CAS#

ROW-

ADDRESS

MUX

CLK

CS#

WE#

CKE

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTER

COMMAND

DECODE

A0-A12,

BA0, BA1

DQML, DQMH

ADDRESS REGISTER

1024 (x16)

8192

I/O GATING DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(8,192 x 1,024 x 16)

BANK0

ROW-

ADDRESS

LATCH

DECODER

8192

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0DQ15

DATA INPUT

DATA

OUTPUT

BANK1

BANK2

BANK3

2 2

REFRESH

COUNTER

Page 7

512Mb: x4, x8, x16

SDRAM

ADVANCE

PIN DESCRIPTIONS

PIN NUMBERS SYMBOL TYPE DESCRIPTION

38 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are

sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers.

37 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.

Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH.

19 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH)

the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code.

18, 17, 16 RAS#, CAS#, Input Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the

WE# command being entered.

39 x4, x8: DQM Input Input/Output Mask: DQM is an input mask signal for write accesses and

an output enable signal for read accesses. Input data is masked when

15, 39 x16: DQML, DQM is sampled HIGH during a WRITE cycle. The output buffers are

DQMH placed in a High-Z state (two-clock latency) when DQM is sampled HIGH

during a READ cycle. On the x4 and x8, DQML (Pin 15) is a NC and DQMH is DQM. On the x16, DQML corresponds to DQ0-DQ7 and DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered same state when referenced as DQM.

20, 21 BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE,

READ, WRITE, or PRECHARGE command is being applied.

23-26, 29-34, 22, 35, 36 A0–A12 Input Address Inputs: A0-A12 are sampled during the ACTIVE command (row-

address A0-A12) and READ/WRITE command (column-address A0-A9, A11, A12 [x4]; A0-A9, A11 [x8]; A0-A9 [x16]; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 [HIGH]) or bank selected by (A10 [LOW]). The address inputs also provide the op-code during a LOAD MODE REGISTER command.

2, 4, 5, 7, 8, 10, 11, 13, 42, DQ0–DQ15 x16: I/O Data Input/Output: Data bus for x16 (4, 7, 10, 13, 15, 42, 45, 48, and 51 are

44, 45, 47, 48, 50, 51, 53 NCs for x8; and 2, 4, 7, 8, 10, 13, 15, 42, 45, 47, 48, 51, and 53 are NCs for x4). 2, 5, 8, 11, 44, 47, 50, 53 DQ0–DQ7 x8: I/O Data Input/Output: Data bus for x8 (2, 8, 47, and 53 are NCs for x4).

5, 11, 44, 50 DQ0–DQ3 x4: I/O Data Input/Output: Data bus for x4.

40 NC – No Connect: This pin should be left unconnected.

3, 9, 43, 49 VDDQ Supply DQ Power: Isolated DQ power to the die for improved noise immunity.

6, 12, 46, 52 VSSQ Supply DQ Ground: Isolated DQ ground to the die for improved noise immunity.

1, 14, 27 V

Supply Power Supply: +3.3V ±0.3V.

28, 41, 54 V

Supply Ground.

Page 8

512Mb: x4, x8, x16

SDRAM

ADVANCE

FUNCTIONAL DESCRIPTION

In general, the 512Mb SDRAMs (32 Meg x 4 x 4 banks, 16 Meg x 8 x 4 banks, and 8 Meg x 16 x 4 banks) are quadbank DRAMs that operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 134,217,728bit banks is organized as 8,192 rows by 4,096 columns by 4 bits. Each of the x8’s 134,217,728-bit banks is organized as 8,192 rows by 2,048 columns by 8 bits. Each of the x16’s 134,217,728-bit banks is organized as 8,192 rows by 1,024 columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0A12 select the row). The address bits (x4: A0-A9, A11, A12; x8: A0-A9, A11; x16: A0-A9) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.

Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.

Initialization

SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied.

Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for Mode Register programming. Because the Mode Register will power up in an unknown state, it should be loaded prior to applying any operational command.

MODE REGISTER

The Mode Register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 1. The Mode Register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power.

Mode Register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future use. Address A12 (M12) is undefined but should be driven LOW during loading of the Mode Register.

The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.

Burst Length

Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A9, A11, A12 (x4); A1-A9, A11 (x8); or A1-A9 (x16) when the burst length is set to two; by A2-A9, A11, A12 (x4); A2A9, A11 (x8) or A2-A9 (x16) when the burst length is set to four; and by A3-A9, A11, A12 (x4); A3-A9, A11 (x8) or A3-A9 (x16) when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached.

Page 9

512Mb: x4, x8, x16

SDRAM

ADVANCE

NOTE: 1. For full-page accesses: y = 4,096 (x4); y = 2,048

(x8); y = 1,024 (x16).

2. For a burst length of two, A1-A9, A11, A12 (x4); A1-A9, A11 (x8); or A1-A9 (x16) select the blockof-two burst; A0 selects the starting column within the block.

3. For a burst length of four, A2-A9, A11, A12 (x4); A2-A9, A11 (x8); or A2-A9 (x16) select the blockof-four burst; A0-A1 select the starting column within the block.

4. For a burst length of eight, A3-A9, A11, A12 (x4); A3-A9, A11 (x8); or A3-A9 (x16) select the blockof-eight burst; A0-A2 select the starting column within the block.

5. For a full-page burst, the full row is selected and A0-A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) select the starting column.

6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.

7. For a burst length of one, A0-A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) select the unique column to be accessed, and Mode Register bit M3 is ignored.

Table 1

Burst Definition

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

0-0-Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst LengthCAS Latency BT

A6 A5 A4

A3A8A2A1A0

Mode Register (Mx)

Address Bus

654

382

M6-M0

Op Mode

A10

A11

Reserved* WB

Write Burst Mode

Programmed Burst Length

Single Location Access

*Should program

M12, M11, M10 = “0, 0, 0”

to ensure compatibility

with future devices.

A12

Figure 1

Mode Register Definition

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1.

Burst Starting Column Order of Accesses Within a Burst

Length Address Type = Sequential Type = Interleaved

00-1 0-1 11-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full n = A0-A11/9/8

Cn, Cn + 1, Cn + 2

Page

Cn + 3, Cn + 4...

Not Supported

(y) (location 0-y)

…Cn - 1,

Cn…

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512Mb: x4, x8, x16

SDRAM

ADVANCE

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts.

Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.

CAS Latency

The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Table 2 below indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Figure 2

CAS Latency

CLK

T2T1 T3T0

CAS Latency = 3

OUT

COMMAND

NOPREAD

NOP

DON’T CARE

UNDEFINED

CLK

T2T1 T3T0

CAS Latency = 2

OUT

COMMAND

NOPREAD

NOP

Table 2

CAS Latency

ALLOWABLE OPERATING

FREQUENCY (MHz)

CAS CAS

SPEED LATENCY = 2 LATENCY = 3

-7E ≤ 133 ≤ 143

-75 ≤ 100 ≤ 133

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SDRAM

ADVANCE

TRUTH TABLE 1 – COMMANDS AND DQM OPERATION

(Note: 1)

NAME (FUNCTION) CS# RAS# CAS# WE# DQM ADDR DQs NOTES

COMMAND INHIBIT (NOP) H XXXX X X

NO OPERATION (NOP) L H H H X X X

ACTIVE (Select bank and activate row) L L H H X Bank/Row X 3

READ (Select bank and column, and start READ burst) L H L H L/H8Bank/Col X 4

WRITE (Select bank and column, and start WRITE burst) L H L L L/H8Bank/Col Valid 4

BURST TERMINATE L H H L X X Active

PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5

AUTO REFRESH or SELF REFRESH L L L H X X X 6, 7 (Enter self refresh mode)

LOAD MODE REGISTER L L L L X Op-Code X 2

Write Enable/Output Enable ––––L – Active 8

Write Inhibit/Output High-Z ––––H – High-Z 8

following the Operation section; these tables provide current state/next state information.

COMMANDS

Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0-A11 define the op-code written to the Mode Register, and A12 should be driven LOW.

3. A0-A12 provide row address, and BA0, BA1 determine which bank is made active.

4. A0-A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

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COMMAND INHIBIT

The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.

LOAD MODE REGISTER

The Mode Register is loaded via inputs A0-A11 (A12 should be driven LOW.) See Mode Register heading in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met.

ACTIVE

The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank.

READ

The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data.

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.

AUTO PRECHARGE

Auto precharge is a feature which performs the same individual-bank PRECHARGE function described above, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A PRECHARGE of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where auto precharge does not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command.

Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Operation section of this data sheet.

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ADVANCE

BURST TERMINATE

The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be PRECHARGED prior to issuing a AUTO REFRESH comand. The AUTO REFRESH command should not be issued until the minimum tRP has been met after the PRECHARGE command as shown in the operations section.

The addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an AUTO REFRESH command. The 512Mb SDRAM requires 8,192 AUTO REFRESH cycles every 64ms (tREF), regardless of width option. Providing a distributed AUTO REFRESH command every 7.81µs will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 8,192 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRC), once every 64ms.

SELF REFRESH

The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of CKE, which must remain LOW.

Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that.

The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for

XSR because time is required for the completion of any

internal refresh in progress.

Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every 7.81µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter.

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Operation

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Figure 3).

After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in Figure 4, which covers any case where 2 < tRCD (MIN)/tCK - 3. (The same procedure is used to convert other specification limits from time units to clock cycles.)

A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.

A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.

Figure 4

Example: Meeting tRCD (MIN) When 2

< tRCD (MIN)/tCK

CLK

T2T1 T3T0

COMMAND

NOPACTIVE

READ or

WRITE

NOP

RCD

DON’T CARE

Figure 3

Activating a Specific Row In a

Specific Bank

CS#

WE#

CAS#

RAS#

CKE

CLK

A0-A12

ROW

ADDRESS

HIGH

BA0, BA1

BANK

ADDRESS

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ADVANCE

Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A fullpage burst will continue until terminated. (At the end of the page, it will wrap to the start address and continue.)

Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 7 for CAS

READs

READ bursts are initiated with a READ command, as

shown in Figure 5.

The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled.

During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 6 shows general timing for each possible CAS latency setting.

Figure 5

READ Command

Figure 6

CAS Latency

CLK

T2T1 T3T0

CAS Latency = 3

OUT

COMMAND

NOPREAD

NOP

DON’T CARE

UNDEFINED

CLK

T2T1 T3T0

CAS Latency = 2

OUT

COMMAND

NOPREAD

NOP

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN ADDRESS

A0-A9, A11, A12: x4

A0-A9, A11: x8

A0-A9: x16

A10

BA0,1

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK

ADDRESS

A12: x4 A11, A12: x8 A9, A11, A12: x16

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ADVANCE

latencies of two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 512Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated

Figure 7

Consecutive READ Bursts

on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Figure 8, or each subsequent READ may be performed to a different bank.

DON’T CARE

NOTE: Each READ command may be to any bank. DQM is LOW.

CLK

DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

BANK, COL b

OUT

n + 1

OUT

n + 2

OUT

n + 3

OUT

READ

X = 1 cycle

CAS Latency = 2

CLK

DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1

OUT

n + 2

OUT

n + 3

OUT

READ

NOP

X = 2 cycles

CAS Latency = 3

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ADVANCE

Figure 8

Random READ Accesses

CLK

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP

BANK,

COL n

DON’T CARE

OUT

READ

NOTE: Each READ command may be to any bank. DQM is LOW.

READ READ NOP

BANK,

COL a

BANK,

COL x

BANK, COL m

CLK

OUT

T2T1 T4T3 T5T0

COMMAND

ADDRESS

READ NOP

BANK,

COL n

OUT

READ READ READ NOP

BANK,

COL a

BANK, COL x

BANK, COL m

CAS Latency = 2

CAS Latency = 3

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ADVANCE

Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixedlength READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/ O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go HighZ. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command.

The DQM input is used to avoid I/O contention, as shown in Figures 9 and 10. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers)

DON’T CARE

READ NOP NOPNOP NOP

DQM

CLK

OUT

T2T1 T4T3T0

COMMAND

ADDRESS

BANK, COL n

WRITE

DIN b

BANK, COL b

NOTE: A CAS latency of three is used for illustration. The

READ command

may be to any bank, and the WRITE command may be to any bank.

Figure 10

READ to WRITE with Extra Clock Cycle

Figure 9

READ to WRITE

READ NOP NOP

WRITE

NOP

CLK

T2T1 T4T3T0

DQM

OUT

COMMAND

DIN b

ADDRESS

BANK,

COL n

BANK,

COL b

NOTE: A CAS latency of three is used for illustration. The

READ command may be to any bank, and the WRITE command may be to any bank. If a burst of one is used, then DQM is not required.

to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z), regardless of the state of the DQM signal; provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 10, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid.

The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 10 shows the case where the additional NOP is needed.

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ADVANCE

Figure 11

READ to PRECHARGE

A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 11 for each possible CAS latency; data

element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s).

In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same op-

DON’T CARE

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOPNOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

PRECHARGE

ACTIVE

NOTE: DQM is LOW.

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOPNOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

PRECHARGE

ACTIVE

X = 1 cycle

CAS Latency = 2

CAS Latency = 3

X = 2 cycles

BANK a,

COL n

BANK a,

ROW

BANK

(a or all)

BANK a,

COL n

BANK a,

ROW

BANK

(a or all)

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ADVANCE

Figure 12

Terminating a READ Burst

eration that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.

Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 12 for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst.

CLK

DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

BURST

TERMINATE

NOP

DON’T CARE

NOTE: DQM is LOW.

CLK

DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

BURST

TERMINATE

NOP

X = 1 cycle

CAS Latency = 2

CAS Latency = 3

X = 2 cycles

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ADVANCE

WRITEs

WRITE bursts are initiated with a WRITE command,

as shown in Figure 13.

The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled.

During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see Figure 14). A fullpage burst will continue until terminated. (At the end of the page, it will wrap to the start address and continue.)

Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. An example is

Figure 15

WRITE to WRITE

shown in Figure 15. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. The 512Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 16, or each subsequent WRITE may be performed to a different bank.

CLK

T2T1 T3T0

COMMAND

ADDRESS

NOP NOPWRITE

n + 1

NOP

BANK,

COL n

Figure 14

WRITE Burst

CLK

T2T1T0

COMMAND

ADDRESS

NOPWRITE WRITE

BANK,

COL n

BANK,

COL b

n + 1

NOTE: DQM is LOW.

Each WRITE

command may be to any bank.

DON’T CARE

Figure 13

WRITE Command

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN ADDRESS

A10

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

A0-A9, A11, A12: x4

A0-A9, A11: x8

A0-A9: x16

A12: x4

A11, A12: x8

A9, A11, A12: x16

BA0, BA, 1

BANK

ADDRESS

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ADVANCE

registered. The auto precharge mode requires a tWR of at least one clock plus time, regardless of frequency. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in Figure

18. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. The precharge can be issued coincident with the first coincident clock edge (T2 in Figure 18) on an A1 Version and with the second clock on an A2 Version (Figure 18.)

In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the

Figure 18

WRITE To PRECHARGE

DON’T CARE

DQM

CLK

T2T1 T4T3T0

COMMAND

ADDRESS

BANK a,

COL n

NOPWRITE

PRECHARGE

NOPNOP

n + 1

ACTIVE

BANK

(a or all)

BANK a,

ROW

DQM

COMMAND

ADDRESS

BANK a,

COL n

NOPWRITE

PRECHARGE

NOPNOP

n + 1

ACTIVE

BANK

(a or all)

NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed length of two.

BANK a,

ROW

NOP

WR @ tCLK ≥ 15ns

WR = tCLK < 15ns

Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be immediately followed by a READ command. Once the READ command is registered, the data inputs will be ignored, and WRITEs will not be executed. An example is shown in Figure 17. Data n + 1 is either the last of a burst of two or the last desired of a longer burst.

Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is

Figure 17

WRITE To READ

CLK

T2T1 T3T0

COMMAND

ADDRESS

NOPWRITE

BANK, COL n

n + 1

OUT

READ NOP NOP

BANK, COL b

NOP

OUT

b + 1

T4 T5

NOTE: The WRITE command may be to any bank, and the READ command

be to any bank. DQM is LOW. CAS latency = 2 for illustration.

Figure 16

Random WRITE Cycles

CLK

T2T1 T3T0

COMMAND

ADDRESS

WRITE

BANK, COL n

WRITE

WRITE WRITE

BANK,

COL a

BANK,

COL x

BANK, COL m

NOTE: Each WRITE command may be to any bank.

DQM is LOW.

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ADVANCE

PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.

Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is

Figure 21

Power-Down

DON’T CARE

RAS

RCD

All banks idle

Input buffers gated off

Exit power-down mode.

()(

)

()(

)

()(

)

CKS

> t

CKS

COMMAND

NOP ACTIVE

Enter power-down mode.

NOP

CLK

CKE

()(

)

()(

)

Figure 20

PRECHARGE Command

Figure 19

Terminating a WRITE Burst

CLK

T2T1T0

COMMAND

ADDRESS

BANK,

COL n

WRITE

BURST

TERMINATE

COMMAND

DIN

(ADDRESS)

(DATA)

NOTE: DQMs are LOW.

shown in Figure 19, where data n is the last desired data element of a longer burst.

PRECHARGE

The PRECHARGE command (see Figure 20) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.

POWER-DOWN

Power-down occurs if CKE is registered low coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode.

The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS). (See Figure 21.)

CS#

WE#

CAS#

RAS#

CKE

CLK

A10

HIGH

All Banks

Bank Selected

A0-A9, A11, A12

BA0, BA1

BANK

ADDRESS

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ADVANCE

COMMAND

ADDRESS

WRITE

BANK, COL n

NOPNOP

CLK

T2T1 T4T3 T5T0

CKE

INTERNAL

CLOCK

NOP

n + 1

n + 2

NOTE: For this example, burst length = 4 or greater, and DM

is LOW.

Figure 22

Clock Suspend During WRITE Burst

DON’T CARE

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and

DQM is LOW.

CKE

INTERNAL

CLOCK

NOP

Figure 23

Clock Suspend During READ Burst

CLOCK SUSPEND

The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic.

For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See examples in Figures 22 and 23.)

Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge.

BURST READ/SINGLE WRITE

The burst read/single write mode is entered by programming the write burst mode bit (M9) in the Mode Register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0).

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ADVANCE

CONCURRENT AUTO PRECHARGE

An access command to (READ or WRITE) another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. Micron SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below.

READ with auto precharge

1. Interrupted by a READ (with or without auto

precharge): A READ to bank m will interrupt a READ

on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 24).

2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).

CLK

DOUT

T2T1 T4T3 T6T5T0

COMMAND

READ - AP

BANK n

NOP NOPNOPNOP

OUT

a + 1

OUT

d + 1

NOP

BANK n

CAS Latency = 3 (BANK m)

BANK m

ADDRESS

Idle

NOP

NOTE: DQM is LOW.

BANK n,

COL a

BANK m,

COL d

READ - AP

BANK m

Internal States

Page Active READ with Burst of 4 Interrupt Burst, Precharge

Page Active READ with Burst of 4

Precharge

RP - BANK n

RP - BANK m

CAS Latency = 3 (BANK n)

Figure 24

READ With Auto Precharge Interrupted by a READ

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

NOPNOPNOPNOP

d + 1

d + 2

d + 3

NOP

BANK n

BANK m

ADDRESS

Idle

NOP

DQM

NOTE: 1. DQM is HIGH at T2 to prevent D

OUT

-a+1 from contending with DIN-d at T4.

BANK n,

COL a

BANK m,

COL d

WRITE - AP

BANK m

Internal States

Page

Active

READ with Burst of 4 Interrupt Burst, Precharge

Page Active WRITE with Burst of 4

Write-Back

RP -

BANK

WR -

BANK

CAS Latency = 3 (BANK n)

READ - AP

BANK n

DON’T CARE

Figure 25

READ With Auto Precharge Interrupted by a WRITE

Page 26

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SDRAM

ADVANCE

CLK

T2T1 T4T3 T6T5T0

COMMAND

WRITE - AP

BANK n

NOPNOPNOPNOP

a + 1

NOP NOP

BANK n

BANK m

ADDRESS

NOTE: 1. DQM is LOW.

BANK n,

COL a

BANK m,

COL d

READ - AP

BANK m

Internal States

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active READ with Burst of 4

RP - BANK m

OUT

d + 1

CAS Latency = 3 (BANK m)

RP - BANK n

WR - BANK n

Figure 26

WRITE With Auto Precharge Interrupted by a READ

DON’T CARE

CLK

T2T1 T4T3 T6T5T0

COMMAND

WRITE - AP

BANK n

NOPNOPNOPNOP

d + 1

a + 1

a + 2

d + 2

d + 3

NOP

BANK n

BANK m

ADDRESS

NOP

NOTE: 1. DQM is LOW.

BANK n,

COL a

BANK m,

COL d

WRITE - AP

BANK m

Internal States

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active WRITE with Burst of 4

Write-Back

WR - BANK n

RP - BANK n

WR - BANK m

Figure 27

WRITE With Auto Precharge Interrupted by a WRITE

WRITE with auto precharge

3. Interrupted by a READ (with or without AUTO PRECHARGE): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 26).

4. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin after

WR is met, where tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m (Figure 27).

Page 27

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ADVANCE

TRUTH TABLE 2 – CKE

(Notes: 1-4)

CKE

n-1

CKE

CURRENT STATE COMMAND

ACTION

NOTES

L L Power-Down X Maintain Power-Down

Self Refresh X Maintain Self Refresh

Clock Suspend X Maintain Clock Suspend

L H Power-Down COMMAND INHIBIT or NOP Exit Power-Down 5

Self Refresh COMMAND INHIBIT or NOP Exit Self Refresh 6

Clock Suspend X Exit Clock Suspend 7

H L All Banks Idle COMMAND INHIBIT or NOP Power-Down Entry

All Banks Idle AUTO REFRESH Self Refresh Entry

Reading or Writing VALID Clock Suspend Entry

H H See Truth Table 3 (page 28)

NOTE: 1. CKEn is the logic state of CKE at clock edge n; CKE

n-1

was the state of CKE at the previous clock edge.

2. Current state is the state of the SDRAM immediately prior to clock edge n.

3. COMMAND

is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.

4. All states and sequences not shown are illegal or reserved.

5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that

CKS is met).

6. Exiting self refresh at clock edge n will put the device in the all banks idle state once

XSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during tXSR period.

7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1.

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ADVANCE

TRUTH TABLE 3 – CURRENT STATE BANK n - COMMAND TO BANK n

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION) NOTES

Any H X X X COMMAND INHIBIT (NOP/Continue previous operation)

L H H H NO OPERATION (NOP/Continue previous operation)

L L H H ACTIVE (Select and activate row)

Idle L L L H AUTO REFRESH 7

LLLLLOAD MODE REGISTER 7

L L H L PRECHARGE 11

L H L H READ (Select column and start READ burst) 10

Row Active L H L L WRITE (Select column and start WRITE burst) 10

L L H L PRECHARGE (Deactivate row in bank or banks) 8

Read L H L H READ (Select column and start new READ burst) 10

(Auto L H L L WRITE (Select column and start WRITE burst) 10

Precharge L L H L PRECHARGE (Truncate READ burst, start PRECHARGE) 8

Disabled) L H H L BURST TERMINATE 9

Write L H L H READ (Select column and start READ burst) 10

(Auto L H L L WRITE (Select column and start new WRITE burst) 10

Precharge L L H L PRECHARGE (Truncate WRITE burst, start PRECHARGE) 8

Disabled) L H H L BURST TERMINATE 9

NOTE: 1. This table applies when CKE

n-1

was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been

met (if the previous state was self refresh).

2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and

RP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been

terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been

terminated.

4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth Table 4.

Precharging: Starts with registration of a PRECHARGE command and ends when

RP is met. Once tRP is met, the

bank will be in the idle state.

Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the

bank will be in the row active state.

Read w/Auto

Precharge

Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has

been met. Once tRP is met, the bank will be in the idle state.

Write w/Auto

Precharge

Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has

been met. Once tRP is met, the bank will be in the idle state.

Page 29

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ADVANCE

NOTE (continued):

5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when

RC is met. Once tRC is met,

the SDRAM will be in the all banks idle state.

Accessing Mode

MRD has been met.

Once tMRD is met, the SDRAM will be in the all banks idle state.

Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met,

all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.

9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.

10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.

11. Does not affect the state of the bank and acts as a NOP to that bank.

Page 30

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ADVANCE

TRUTH TABLE 4 – CURRENT STATE BANK n - COMMAND TO BANK m

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION) NOTES

Any H X X X COMMAND INHIBIT (NOP/Continue previous operation)

L H H H NO OPERATION (NOP/Continue previous operation)

Idle XXXXAny Command Otherwise Allowed to Bank m

Row L L H H ACTIVE (Select and activate row)

Activating, L H L H READ (Select column and start READ burst) 7

Active, or L H L L WRITE (Select column and start WRITE burst) 7

Precharging L L H L PRECHARGE

Read L L H H ACTIVE (Select and activate row)

(Auto L H L H READ (Select column and start new READ burst) 7, 10

Precharge L H L L WRITE (Select column and start WRITE burst) 7, 11

Disabled) L L H L PRECHARGE 9

Write L L H H ACTIVE (Select and activate row)

(Auto L H L H READ (Select column and start READ burst) 7, 12

Precharge L H L L WRITE (Select column and start new WRITE burst) 7, 13

Disabled) L L H L PRECHARGE 9

Read L L H H ACTIVE (Select and activate row)

(With Auto L H L H READ (Select column and start new READ burst) 7, 8, 14

Precharge) L H L L WRITE (Select column and start WRITE burst) 7, 8, 15

L L H L PRECHARGE 9

Write L L H H ACTIVE (Select and activate row)

(With Auto L H L H READ (Select column and start READ burst) 7, 8, 16

Precharge) L H L L WRITE (Select column and start new WRITE burst) 7, 8, 17

L L H L PRECHARGE 9

NOTE: 1. This table applies when CKE

n-1

was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the

previous state was self refresh).

2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and

RP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been

terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been

terminated.

Read w/Auto

Precharge

Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when tRP has

been met. Once tRP is met, the bank will be in the idle state.

Write w/Auto

Precharge

Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when tRP has

been met. Once tRP is met, the bank will be in the idle state.

Page 31

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ADVANCE

NOTE (continued):

4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.

8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted by bank m’s burst.

9. Burst in bank n continues as initiated.

10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later (Figure 7).

11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the WRITE command to prevent bus contention.

12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.

13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.

14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 24).

15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).

16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after

WR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to

bank n will be data-in registered one clock prior to the READ to bank m (Figure 26).

17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after

WR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Figure 27).

Page 32

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ADVANCE

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1, 5, 6; notes appear on page 35) (VDD, VDDQ = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Supply Voltage VDD, VDDQ 3 3.6 V

Input High Voltage: Logic 1; All inputs VIH 2VDD + 0.3 V 22

Input Low Voltage: Logic 0; All inputs VIL -0.3 0.8 V 22

Input Leakage Current: Any input 0V ≤ VIN ≤ VDD II -5 5 µA (All other pins not under test = 0V)

Output Leakage Current: DQs are disabled; IOZ -5 5 µA 0V ≤ VOUT ≤ VDDQ

Output Levels: VOH 2.4 – V26 Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) VOL – 0.4 V 26

ABSOLUTE MAXIMUM RATINGS*

Voltage on VDD, VDDQ Supply

Relative to VSS ....................................... -1V to +4.6V

Voltage on Inputs, NC or I/O Pins

Relative to V

SS ....................................... -1V to +4.6V

Operating Temperature,

(Commercial) ................................... 0°C to +70°C

Storage Temperature (plastic) ............ -55°C to +150°C

Power Dissipation ................................................... 1W

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

MAX

IDD SPECIFICATIONS AND CONDITIONS

(Notes: 1, 5, 6, 11, 13; notes appear on page 35) (VDD, VDDQ = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL -7E -75 UNITS NOTES

Operating Current: Active Mode; IDD1 TBD TBD mA 3, 18, Burst = 1; READ or WRITE; tRC = tRC (MIN) 19, 29

Standby Current: Power-Down Mode; IDD2 TBD TBD mA 29 CKE = LOW; All banks idle

Standby Current: Active Mode; CS# = HIGH; IDD3 TBD TBD mA 3, 12, CKE = HIGH; All banks active after tRCD met; 19, 29 No accesses in progress

Operating Current: Burst Mode; Continuous burst; IDD4 TBD TBD mA 3, 18, READ or WRITE; All banks active 19, 29

Auto Refresh Current:

RFC = tRFC (MIN) IDD5 TBD TBD mA 3, 12,

CS# = HIGH; CKE = HIGH 18, 19,

RFC = 7.81µs IDD6 TBD TBD mA 29,30

Self Refresh Current: CKE ≤ 0.2V Standard IDD7 TBD TBD mA 4

Low power (L) IDD7 TBD TBD mA

Page 33

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SDRAM

ADVANCE

CAPACITANCE

(Note: 2; notes appear on page 35)

PARAMETER SYMBOL MIN MAX UNITS

Input Capacitance: CLK C

1 2.5 3.5 pF

Input Capacitance: All other input-only pins C

2 2.5 3.8 pF

Input/Output Capacitance: DQs C

4.0 6.0 pF

AC CHARACTERISTICS -7E -75 PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

Access time from CLK (pos. edge) CL = 3tAC(3) 5.4 5.4 ns 27

CL = 2tAC(2) 5.4 6 ns

Address hold time

AH 0.8 0.8 ns

Address setup time

AS 1.5 1.5 ns

CLK high-level width

CH 2.5 2.5 ns

CLK low-level width

CL 2.5 2.5 ns

Clock cycle time CL = 3tCK(3) 7 7.5 ns 23

CL = 2tCK(2) 7.5 10 ns 23

CKE hold time

CKH 0.8 0.8 ns

CKE setup time

CKS 1.5 1.5 ns

CS#, RAS#, CAS#, WE#, DQM hold time

CMH 0.8 0.8 ns

CS#, RAS#, CAS#, WE#, DQM setup time

CMS 1.5 1.5 ns

Data-in hold time

DH 0.8 0.8 ns

Data-in setup time

DS 1.5 1.5 ns

Data-out high-impedance time CL = 3tHZ(3) 5.4 5.4 ns 10

CL = 2tHZ(2) 5.4 6 ns 10

Data-out low-impedance time

LZ 1 1 ns

Data-out hold time (load)

OH 2.7 2.7 ns

Data-out hold time (no load)

1.8 1.8 ns 28

ACTIVE to PRECHARGE command

RAS 37 120,000 44 120,000 ns

ACTIVE to ACTIVE command period

RC 60 66 ns

ACTIVE to READ or WRITE delay

RCD 15 20 ns

Refresh period (8,192 rows)

REF 64 64 ms

AUTO REFRESH period

RFC 66 66 ns

PRECHARGE command period

RP 15 20 ns

ACTIVE bank a to ACTIVE bank b command

RRD 14 15 ns

Transition time

T 0.3 1.2 0.3 1.2 ns 7

WRITE recovery time

WR 1 CLK + 1 CLK + – 24

7ns 7.5ns 14

14 15 ns 25

Exit SELF REFRESH to ACTIVE command

XSR 67 75 ns 20

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 5, 6, 8, 9, 11; notes appear on page 35)

Page 34

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ADVANCE

AC FUNCTIONAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 11; notes appear on page 35)

PARAMETER SYMBOL -7E -75 UNITS NOTES

READ/WRITE command to READ/WRITE command

CCD 1 1

CK 17

CKE to clock disable or power-down entry mode

CKED 1 1

CK 14

CKE to clock enable or power-down exit setup mode

PED 1 1

CK 14

DQM to input data delay

DQD 0 0

CK 17

DQM to data mask during WRITEs

DQM 0 0

CK 17

DQM to data high-impedance during READs

DQZ 2 2

CK 17

WRITE command to input data delay

DWD 0 0

CK 17

Data-in to ACTIVE command

DAL 4 5

CK 15, 21

Data-in to PRECHARGE command

DPL 2 2

CK 16, 21

Last data-in to burst STOP command

BDL 1 1

CK 17

Last data-in to new READ/WRITE command

CDL 1 1

CK 17

Last data-in to PRECHARGE command

RDL 2 2

CK 16, 21

LOAD MODE REGISTER command to ACTIVE or REFRESH command

MRD 2 2

CK 26

Data-out to high-impedance from PRECHARGE command CL = 3tROH(3) 3 3

CK 17

CL = 2

ROH(2) 2 2

CK 17

Page 35

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ADVANCE

13. IDD specifications are tested after the device is properly initialized.

14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate.

15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate.

16. Timing actually specified by tWR.

17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.

18. The IDD current will increase or decrease in a proportional amount by the amount the frequency is altered for the test condition.

19. Address transitions average one transition every two clocks.

20. CLK must be toggled a minimum of two times during this period.

21. Based on tCK = 7.5ns for -75 and -7E.

22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 3ns.

23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate.

24. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/7ns after the first clock delay, after the last WRITE is executed.

25. Precharge mode only.

26. JEDEC and PC100, PC133 specify three clocks.

27.tAC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design.

28. Parameter guaranteed by design.

29. For -75, CL = 3, tCK = 7.5ns; For -7E, CL = 2,

CK = 7.5ns

30. CKE is HIGH during refresh command period

RFC(MIN) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value.

NOTES

1. All voltages referenced to VSS.

2. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25°C; pin under test biased at 1.4V.

3. I

DD is dependent on output loading and cycle

rates.Specified values are obtained with minimum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0°C ≤ TA ≤ 70°C) is ensured.

6. An initial pause of 100µs is required after powerup, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded.

7. AC characteristics assume tT = 1ns.

8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.

9. Outputs measured at 1.5V with equivalent load:

50pF

10.tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet

OH before going High-Z.

11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input transition time is longer than 1 ns, then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point.

12. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels.

Page 36

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ADVANCE

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

TIMING PARAMETERS

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

AH 0.8 0.8 ns

AS 1.5 1.5 ns

CH 2.5 2.5 ns

CL 2.5 2.5 ns

CK (3) 7 7.5 ns

CK (2) 7.5 10 ns

CKH 0.8 0.8 ns

INITIALIZE AND LOAD MODE REGISTER

*CAS latency indicated in parentheses.

NOTE: 1. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.

2. If CS is HIGH at clock high time, all commands applied are NOP, with CKE a “Don’t Care.”

3. JEDEC and PC100 specify three clocks.

4. Outputs are guaranteed High-Z after command is issued.

5. A12 should be a LOW at

P + 1.

CKS 1.5 1.5 ns

CMH 0.8 0.8 ns

CMS 1.5 1.5 ns

MRD

22tCK

RFC 66 66 ns

RP 15 20 ns

CKE

COMMAND

BA0, BA1

BANK

RFC

MRD

RFC

AUTO REFRESH

Program Mode Register

1, 3, 4

CMH

CMS

Precharge all banks

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

CKS

Power-up: V

and

CLK stable

T = 100µs

MIN

PRECHARGE NOP

AUTO

REFRESH

NOP

LOAD MODE

ACTIVENOP NOPNOP

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

AUTO

REFRESH

ALL

BANKS

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

High-Z

CKH

()(

)

()(

)

DQM/

DQML, DQMH

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

NOP

()(

)

()(

)

CMH

CMS

CMH

CMS

A0-A9, A11, A12

ROW

CODE

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

A10

ROW

CODE

()(

)

()(

)

()(

)

()(

)

ALL BANKS

SINGLE BANK

()(

)

()(

)

()(

)

()(

)

DON’T CARE

UNDEFINED

T0 T1 Tn + 1 To + 1 Tp + 1 Tp + 2 Tp + 3

Page 37

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

AH 0.8 0.8 ns

AS 1.5 1.5 ns

CH 2.5 2.5 ns

CL 2.5 2.5 ns

CK (3) 7 7.5 ns

NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.

POWER-DOWN MODE

Two clock cycles

CKE

CLK

All banks idle, enter power-down mode

Precharge all

active banks

Input buffers gated off while in

power-down mode

Exit power-down mode

()(

)

()(

)

DON’T CARE

CKS

COMMAND

CMH

CMS

PRECHARGE NOP NOP ACTIVENOP

()(

)

()(

)

All banks idle

BA0, BA1

BANK

BANK(S)

()(

)

()(

)

High-Z

CKH

CKS

DQM/

DQML, DQMH

()(

)

()(

)

()(

)

()(

)

A0-A9, A11, A12

ROW

()(

)

()(

)

ALL BANKS

SINGLE BANK

A10

ROW

()(

)

()(

)

T0 T1 T2 Tn + 1 Tn + 2

*CAS latency indicated in parentheses.

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

CK (2) 7.5 10 ns

CKH 0.8 0.8 ns

CKS 1.5 1.5 ns

CMH 0.8 0.8 ns

CMS 1.5 1.5 ns

Page 38

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

AC (3) 5.4 5.4 ns

AC (2) 5.4 6 ns

AH 0.8 0.8 ns

AS 1.5 1.5 ns

CH 2.5 2.5 ns

CL 2.5 2.5 ns

CK (3) 7 7.5 ns

CK (2) 7.5 10 ns

CKH 0.8 0.8 ns

CLOCK SUSPEND MODE

DQM/

DQML, DQMH

CLK

A0-A9, A11, A12

BA0, BA1

A10

OUT

tAHt

BANK

OUT

m + 1

COMMAND

CMH

CMS

NOPNOP NOP NOPNOPREAD WRITE

DON’T CARE

CKE

CKStCKH

BANK

COLUMN m

OUT

e + 1

NOP

CKH

CKS

CMH

CMS

COLUMN e

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and AUTO PRECHARGE is disabled.

2. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care”

*CAS latency indicated in parentheses.

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

CKS 1.5 1.5 ns

CMH 0.8 0.8 ns

CMS 1.5 1.5 ns

DH 0.8 0.8 ns

DS 1.5 1.5 ns

HZ (3) 5.4 5.4 ns

HZ (2) 5.4 6 ns

LZ 1 1 ns

OH 2.7 2.7 ns

Page 39

512Mb: x4, x8, x16

SDRAM

ADVANCE

AUTO REFRESH MODE

CKE

CLK

RFC RFC

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

COMMAND

CMH

CMS

NOPNOP

()(

)

()(

)

BANK

ACTIVE

AUTO

REFRESH

()(

)

()(

)

NOPNOPPRECHARGE

Precharge all

active banks

AUTO

REFRESH

High-Z

BA0, BA1

BANK(S)

()(

)

()(

)

()(

)

()(

)

CKH

CKS

()(

)

NOP

()(

)

()(

)

()(

)

()(

)

DQM /

DQML, DQMH

A0-A9, A11, A12

ROW

()(

)

()(

)

ALL BANKS

SINGLE BANK

A10

ROW

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

DON’T CARE

T0 T1 T2 Tn + 1 To + 1

*CAS latency indicated in parentheses.

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

CKH 0.8 0.8 ns

CKS 1.5 1.5 ns

CMH 0.8 0.8 ns

CMS 1.5 1.5 ns

RFC 66 66 ns

RP 15 20 ns

TIMING PARAMETERS

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

AH 0.8 0.8 ns

AS 1.5 1.5 ns

CH 2.5 2.5 ns

CL 2.5 2.5 ns

CK (3) 7 7.5 ns

CK (2) 7.5 10 ns

Page 40

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

AH 0.8 0.8 ns

AS 1.5 1.5 ns

CH 2.5 2.5 ns

CL 2.5 2.5 ns

CK (3) 7 7.5 ns

CK (2) 7.5 10 ns

CKH 0.8 0.8 ns

SELF REFRESH MODE

CKE

CLK

Enter self refresh mode

Precharge all

active banks

XSR

CLK stable prior to exiting

self refresh mode

Exit self refresh mode

(Restart refresh time base)

()(

)

()(

)

()(

)

()(

)

()(

)

DON’T CARE

COMMAND

CMH

CMS

AUTO

REFRESH

PRECHARGE NOP NOP

or COMMAND

INHIBIT

()(

)

()(

)

()(

)

()(

)

BA0, BA1

BANK(S)

()(

)

()(

)

High-Z

CKS

AUTO

REFRESH

RAS(MIN)

()(

)

()(

)

()(

)

()(

)

CKH

CKS

DQM/

DQML, DQMH

()(

)

()(

)

()(

)

()(

)

A0-A9, A11,A12

()(

)

()(

)

()(

)

()(

)

ALL BANKS

SINGLE BANK

A10

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

T0 T1 T2 Tn + 1 To + 1 To + 2

()(

)

()(

)

≥

*CAS latency indicated in parentheses.

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

CKS 1.5 1.5 ns

CMH 0.8 0.8 ns

CMS 1.5 1.5 ns

RAS 37 120,000 44 120,000 ns

RP 15 20 ns

XSR 67 75 ns

NOTES: 1. No maximum time limit for Self Refresh. tRAS(MAX) applies to non-Self Refresh mode.

2.tXSR requires minimum of two clocks regardless of frequency or timing.

Page 41

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

AC (3) 5.4 5.4 ns

AC (2) 5.4 6 ns

AH 0.8 0.8 ns

AS 1.5 1.5 ns

CH 2.5 2.5 ns

CL 2.5 2.5 ns

CK (3) 7 7.5 ns

CK (2) 7.5 10 ns

CKH 0.8 0.8 ns

CKS 1.5 1.5 ns

READ – WITHOUT AUTO PRECHARGE

ALL BANKS

RAS

RCD

CAS Latency

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

OUT

CMH

CMS

ROW

BANK BANK BANK

ROW

BANK

OUT

m + 3

OUT

m + 2D

OUT

m + 1

COMMAND

CMH

CMS

PRECHARGENOPNOP NOPACTIVE NOP READ NOP ACTIVE

DISABLE AUTO PRECHARGE

SINGLE BANK

DON’T CARE

UNDEFINED

CKH

CKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual”

PRECHARGE.

2. x16: A11 and A12 = “Don’t Care”

x8: A12 = “Don’t Care”

*CAS latency indicated in parentheses.

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

CMH 0.8 0.8 ns

CMS 1.5 1.5 ns

HZ (3) 5.4 5.4 ns

HZ (2) 5.4 6 ns

LZ 1 1 ns

OH 2.7 2.7 ns

RAS 37 120,000 44 120,000 ns

RC 60 66 ns

RCD 15 20 ns

RP 15 20 ns

Page 42

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

AC (3) 5.4 5.4 ns

AC (2) 5.4 6 ns

AH 0.8 0.8 ns

AS 1.5 1.5 ns

CH 2.5 2.5 ns

CL 2.5 2.5 ns

CK (3) 7 7.5 ns

CK (2) 7.5 10 ns

CKH 0.8 0.8 ns

CKS 1.5 1.5 ns

READ – WITH AUTO PRECHARGE

ENABLE AUTO PRECHARGE

RAS

RCD

CAS Latency

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

OUT

CMH

CMS

ROW

BANK

ROW

BANK

DON’T CARE

UNDEFINED

OUT

m + 3

OUT

m + 2D

OUT

m + 1

COMMAND

CMH

CMS

NOPNOP NOPACTIVE NOP READ NOP ACTIVENOP

CKH

CKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.

2. x16: A11 and A12 = “Don’t Care”

x8: A12 = “Don’t Care”

*CAS latency indicated in parentheses.

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

CMH 0.8 0.8 ns

CMS 1.5 1.5 ns

HZ (3) 5.4 5.4 ns

HZ (2) 5.4 6 ns

LZ 1 1 ns

OH 2.7 2.7 ns

RAS 37 120,000 44 120,000 ns

RC 60 66 ns

RCD 15 20 ns

RP 15 20 ns

Page 43

512Mb: x4, x8, x16

SDRAM

ADVANCE

SINGLE READ – WITHOUT AUTO PRECHARGE

TIMING PARAMETERS

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

AC (3) 5.4 5.4 ns

AC (2) 5.4 6 ns

AH 0.8 0.8 ns

AS 1.5 1.5 ns

CH 2.5 2.5 ns

CL 2.5 2.5 ns

CK (3) 7 7.5 ns

CK (2) 7.5 10 ns

CKH 0.8 0.8 ns

CKS 1.5 1.5 ns

CMH 0.8 0.8 ns

CMS 1.5 1.5 ns

HZ (3) 5.4 5.4 ns

HZ (2) 5.4 6 ns

LZ 1 1 ns

OH 2.7 2.7 ns

RAS 37 120,000 44 120,000 ns

RC 60 66 ns

RCD 15 20 ns

RP 15 20 ns

*CAS latency indicated in parentheses.

ALL BANKS

RAS

RCD

CAS Latency

OUT

CMH

CMS

ROW

BANK

BANK(S)

BANK

ROW

BANK

CMH

CMS

NOPNOPNOP

PRECHARGE

ACTIVE NOP READ ACTIVE NOP

DISABLE AUTO PRECHARGE

SINGLE BANKS

DON’T CARE

UNDEFINED

COLUMN m

CKH

CKS

T0 T1 T2 T3 T4 T5 T6 T7 T8

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

COMMAND

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual”

PRECHARGE.

2. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care”

Page 44

512Mb: x4, x8, x16

SDRAM

ADVANCE

NOTE: 1. For this example, the burst length = 1, and the CAS latency = 2.

2. x16: A11 and A12 = “Don’t Care”

x8: A12 = “Don’t Care”

3. READ command not allowed else tRAS would be violated

*CAS latency indicated in parentheses.

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

CMH 0.8 0.8 ns

CMS 1.5 1.5 ns

HZ (3) 5.4 5.4 ns

HZ (2) 5.4 6 ns

LZ 1 1 ns

OH 2.7 2.7 ns

RAS 37 120,000 44 120,000 ns

RC 60 66 ns

RCD 15 20 ns

RP 15 20 ns

TIMING PARAMETERS

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

AC (3) 5.4 5.4 ns

AC (2) 5.4 6 ns

AH 0.8 0.8 ns

AS 1.5 1.5 ns

CH 2.5 2.5 ns

CL 2.5 2.5 ns

CK (3) 7 7.5 ns

CK (2) 7.5 10 ns

CKH 0.8 0.8 ns

CKS 1.5 1.5 ns

SINGLE READ – WITH AUTO PRECHARGE

ENABLE AUTO PRECHARGE

RAS

RCD

CAS Latency

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11

BA0, BA1

A10

CMH

CMS

ROW

BANK

ROW

BANK

DON’T CARE

UNDEFINED

OUT

COMMAND

CMH

CMS

NOP

READACTIVE NOP NOP

ACTIVENOP

CKH

CKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

NOP

Page 45

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

AC (3) 5.4 5.4 ns

AC (2) 5.4 6 ns

AH 0.8 0.8 ns

AS 1.5 1.5 ns

CH 2.5 2.5 ns

CL 2.5 2.5 ns

CK (3) 7 7.5 ns

CK (2) 7.5 10 ns

CKH 0.8 0.8 ns

CKS 1.5 1.5 ns

ALTERNATING BANK READ ACCESSES

ENABLE AUTO PRECHARGE

DQM/

DQML, DQMH

CLK

A0-A9, A11, A12

BA0, BA1

A10

OUT

CMH

CMS

ROW

DON’T CARE

UNDEFINED

OUT

m + 3

OUT

m + 2D

OUT

m + 1

COMMAND

CMH

CMS

NOP NOPACTIVE NOP READ NOP ACTIVE

OUT

READ

ENABLE AUTO PRECHARGE

ROW

ACTIVE

ROW

BANK 0 BANK 0 BANK 3 BANK 3

BANK 0

CKE

CKH

CKS

COLUMN m

COLUMN b

T0 T1 T2 T4T3 T5 T6 T7 T8

RP - BANK 0

RAS - BANK 0

RCD - BANK 0

CAS Latency - BANK 0

RCD - BANK 1

CAS Latency - BANK 1

RC - BANK 0

RRD

NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.

2. x16: A11 and A12 = “Don’t Care”

x8: A12 = “Don’t Care”

*CAS latency indicated in parentheses.

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

CMH 0.8 0.8 ns

CMS 1.5 1.5 ns

LZ 1 1 ns

OH 2.7 2.7 ns

RAS 37 120,000 44 120,000 ns

RC 60 66 ns

RCD 15 20 ns

RP 15 20 ns

RRD 14 15 ns

Page 46

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

AC (3) 5.4 5.4 ns

AC (2) 5.4 6 ns

AH 0.8 0.8 ns

AS 1.5 1.5 ns

CH 2.5 2.5 ns

CL 2.5 2.5 ns

CK (3) 7 7.5 ns

CK (2) 7.5 10 ns

CKH 0.8 0.8 ns

READ – FULL-PAGE BURST

NOTE: 1. For this example, the CAS latency = 2.

2. x16: A11 and A12 = “Don’t Care”

x8: A12 = “Don’t Care”

3. Page left open; no tRP.

*CAS latency indicated in parentheses.

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

CKS 1.5 1.5 ns

CMH 0.8 0.8 ns

CMS 1.5 1.5 ns

HZ (3) 5.4 5.4 ns

HZ (2) 5.4 6 ns

LZ 1 1 ns

OH 2.7 2.7 ns

RCD 15 20 ns

RCD

CAS Latency

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

OUT

CMH

CMS

OUT

m+1

ROW

OUT

m+1

OUT

m+2

OUT

m-1

Dout m

Full-page burst does not self-terminate.

Can use BURST TERMINATE command.

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

Full page completed

1,024 (x16) locations within same row 2,048 (x8) locations within same row 4,096 (x4) locations within same row

DON’T CARE

UNDEFINED

COMMAND

CMH

CMS

NOPNOP NOPACTIVE NOP READ NOP BURST TERMNOP NOP

()(

)

()(

)

NOP

()(

)

()(

)

BANK

()(

)

()(

)

BANK

CKH

CKS

()(

)

()(

)

()(

)

()(

)

COLUMN m

T0 T1 T2 T4T3 T5 T6 Tn + 1 Tn + 2 Tn + 3 Tn + 4

Page 47

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

AC (3) 5.4 5.4 ns

AC (2) 5.4 6 ns

AH 0.8 0.8 ns

AS 1.5 1.5 ns

CH 2.5 2.5 ns

CL 2.5 2.5 ns

CK (3) 7 7.5 ns

CK (2) 7.5 10 ns

CKH 0.8 0.8 ns

READ – DQM OPERATION

RCD

CAS Latency

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

CMS

ROW

BANK

ROW

BANK

DON’T CARE

UNDEFINED

OUT

m + 3D

OUT

m + 2

CMH

COMMAND

NOPNOP NOPACTIVE NOP READ NOPNOP NOP

CMS

CMH

CKH

CKS

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.

2. x16: A11 and A12 = “Don’t Care”

x8: A12 = “Don’t Care”

*CAS latency indicated in parentheses.

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

CKS 1.5 1.5 ns

CMH 0.8 0.8 ns

CMS 1.5 1.5 ns

HZ (3) 5.4 5.4 ns

HZ (2) 5.4 6 ns

LZ 1 1 ns

OH 2.7 2.7 ns

RCD 15 20 ns

Page 48

512Mb: x4, x8, x16

SDRAM

ADVANCE

WRITE – WITHOUT AUTO PRECHARGE

DISABLE AUTO PRECHARGE

RAS

RCD

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

CMH

CMS

ROW

BANK BANK

ROW

BANK

DON’T CARE

DIN m

DIN m + 1 DIN m + 2 DIN m + 3

COMMAND

CMH

CMS

NOPNOP NOPACTIVE NOP WRITE PRECHARGE

SINGLE BANK

CKH

CKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

ROW

BANK

ROW

ACTIVE

NOP

ALL BANKs

NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.

3. x16: A11 and A12 = “Don’t Care”

x8: A12 = “Don’t Care”

*CAS latency indicated in parentheses.

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

CMS 1.5 1.5 ns

DH 0.8 0.8 ns

DS 1.5 1.5 ns

RAS 37 120,000 44 120,000 ns

RC 60 66 ns

RCD 15 20 ns

RP 15 20 ns

WR 14 15 ns

TIMING PARAMETERS

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

AH 0.8 0.8 ns

AS 1.5 1.5 ns

CH 2.5 2.5 ns

CL 2.5 2.5 ns

CK (3) 7 7.5 ns

CK (2) 7.5 10 ns

CKH 0.8 0.8 ns

CKS 1.5 1.5 ns

CMH 0.8 0.8 ns

Page 49

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

AH 0.8 0.8 ns

AS 1.5 1.5 ns

CH 2.5 2.5 ns

CL 2.5 2.5 ns

CK (3) 7 7.5 ns

CK (2) 7.5 10 ns

CKH 0.8 0.8 ns

CKS 1.5 1.5 ns

CMH 0.8 0.8 ns

WRITE – WITH AUTO PRECHARGE

NOTE: 1. For this example, the burst length = 4.

2. x16: A11 and A12 = “Don’t Care”

x8: A12 = “Don’t Care”

*CAS latency indicated in parentheses.

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

CMS 1.5 1.5 ns

DH 0.8 0.8 ns

DS 1.5 1.5 ns

RAS 37 120,000 44 120,000 ns

RC 60 66 ns

RCD 15 20 ns

RP 15 20 ns

WR 1 CLK + 1 CLK + –

7ns 7.5ns

ENABLE AUTO PRECHARGE

RAS

RCD

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

CMH

CMS

ROW

BANK BANK

ROW

BANK

DON’T CARE

DIN m

DIN m + 1 DIN m + 2 DIN m + 3

COMMAND

CMH

CMS

NOPNOP NOPACTIVE NOP WRITE NOP ACTIVE

CKH

CKS

NOP NOP

COLUMN

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

Page 50

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

AH 0.8 0.8 ns

AS 1.5 1.5 ns

CH 2.5 2.5 ns

CL 2.5 2.5 ns

CK (3) 7 7.5 ns

CK (2) 7.5 10 ns

CKH 0.8 0.8 ns

CKS 1.5 1.5 ns

CMH 0.8 0.8 ns

SINGLE WRITE – WITHOUT AUTO PRECHARGE

CMS 1.5 1.5 ns

DH 0.8 0.8 ns

DS 1.5 1.5 ns

RAS 37 120,000 44 120,000 ns

RC 60 66 ns

RCD 15 20 ns

RP 15 20 ns

WR 14 15 ns

*CAS latency indicated in parentheses.

DISABLE AUTO PRECHARGE

ALL BANKS

RAS

RCD

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

CMH

CMS

ROW

BANK BANK BANK

ROW

BANK

DIN m

COMMAND

CMH

CMS

NOP

PRECHARGEACTIVE NOP WRITE ACTIVENOP NOP

SINGLE BANK

CKH

CKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

DON’T CARE

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.

3. x16: A11 and A12 = “Don’t Care”

x8: A12 = “Don’t Care”

4. PRECHARGE command not allowed else tRAS would be violated

Page 51

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

AH 0.8 0.8 ns

AS 1.5 1.5 ns

CH 2.5 2.5 ns

CL 2.5 2.5 ns

CK (3) 7 7.5 ns

CK (2) 7.5 10 ns

CKH 0.8 0.8 ns

CKS 1.5 1.5 ns

CMH 0.8 0.8 ns

SINGLE WRITE – WITH AUTO PRECHARGE

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.

3. x16: A11 and A12 = “Don’t Care”

x8: A12 = “Don’t Care”

4. WRITE command not allowed else tRAS would be violated

*CAS latency indicated in parentheses.

ENABLE AUTO PRECHARGE

RAS

RCD

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

CMH

CMS

ROW

BANK BANK

ROW

BANK

DIN m

COMMAND

CMH

CMS

NOP

NOPACTIVE NOP

WRITE

NOP

ACTIVE

CKH

CKS

NOP NOP

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

DON’T CARE

CMS 1.5 1.5 ns

DH 0.8 0.8 ns

DS 1.5 1.5 ns

RAS 37 120,000 44 120,000 ns

RC 60 66 ns

RCD 15 20 ns

RP 15 20 ns

WR 1 CLK + 1 CLK + ns

7ns 7ns

Page 52

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

AH 0.8 0.8 ns

AS 1.5 1.5 ns

CH 2.5 2.5 ns

CL 2.5 2.5 ns

CK (3) 7 7.5 ns

CK (2) 7.5 10 ns

CKH 0.8 0.8 ns

CKS 1.5 1.5 ns

CMH 0.8 0.8 ns

ALTERNATING BANK WRITE ACCESSES

CLK

DON’T CARE

DIN m

DIN m + 1 DIN m + 2 DIN m + 3

COMMAND

CMH

CMS

NOP NOPACTIVE NOP WRITE NOP NOP ACTIVE

ACTIVE WRITE

DIN b

DIN b + 1 DIN b + 3

ENABLE AUTO PRECHARGE

DQM/

DQML, DQMH

A0-A9, A11, A12

BA0, BA1

A10

CMH

CMS

tAHt

ROW

ENABLE AUTO PRECHARGE

ROW

BANK 0 BANK 0 BANK 1

BANK 0

BANK 1

CKE

CKH

CKS

DIN b + 2

COLUMN b

COLUMN m

RP - BANK 0

RAS - BANK 0

RCD - BANK 0

WR - BANK 0

WR - BANK 1

RCD - BANK 1

RC - BANK 0

RRD

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

NOTE: 1. For this example, the burst length = 4.

2. Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14ns to 15ns with PRECHARGE.

3. x16: A11 and A12 = “Don’t Care”

x8: A12 = “Don’t Care”

*CAS latency indicated in parentheses.

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

CMS 1.5 1.5 ns

DH 0.8 0.8 ns

DS 1.5 1.5 ns

RAS 37 120,000 44 120,000 ns

RC 60 66 ns

RCD 15 20 ns

RP 15 20 ns

RRD 14 15 ns

WR Note 2 Note 2 ns

Page 53

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

AH 0.8 0.8 ns

AS 1.5 1.5 ns

CH 2.5 2.5 ns

CL 2.5 2.5 ns

CK (3) 7 7.5 ns

CK (2) 7.5 10 ns

CKH 0.8 0.8 ns

WRITE – FULL-PAGE BURST

NOTE: 1. x16: A11 and A12 = “Don’t Care”

x8: A12 = “Don’t Care”

2.tWR must be satisfied prior to PRECHARGE command.

3. Page left open; no tRP.

*CAS latency indicated in parentheses.

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

CKS 1.5 1.5 ns

CMH 0.8 0.8 ns

CMS 1.5 1.5 ns

DH 0.8 0.8 ns

DS 1.5 1.5 ns

RCD 15 20 ns

RCD

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

CMS

ROW

Full-page burst does not self-terminate. Can use BURST TERMINATE command to stop.

2, 3

()(

)

()(

)

()(

)

()(

)

Full page completed

DON’T CARE

COMMAND

CMH

CMS

NOPNOP NOPACTIVE NOP WRITE BURST TERMNOP NOP

()(

)

()(

)

()(

)

()(

)

DIN m

DIN m + 1 DIN m + 2 DIN m + 3

DIN m - 1

BANK

()(

)

()(

)

BANK

CMH

CKH

CKS

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

1,024 (x16) locations within same row

2,048 (x8) locations within same row 4,096 (x4) locations within same row

COLUMN

T0 T1 T2 T3 T4 T5 Tn + 1 Tn + 2 Tn + 3

Page 54

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

AH 0.8 0.8 ns

AS 1.5 1.5 ns

CH 2.5 2.5 ns

CL 2.5 2.5 ns

CK (3) 7 7.5 ns

CK (2) 7.5 10 ns

CKH 0.8 0.8 ns

WRITE – DQM OPERATION

RCD

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

CMS

ROW

BANK

ROW

BANK

ENABLE AUTO PRECHARGE

DIN m + 3

DIN m

DIN m + 2

CMH

COMMAND

NOPNOP NOPACTIVE NOP WRITE NOPNOP

DON’T CARE

CMS

CMH

DISABLE AUTO PRECHARGE

CKH

CKS

COLUMN m

T0 T1 T2 T3 T4 T5 T6 T7

NOTE: 1. For this example, the burst length = 4.

2. x16: A11 and A12 = “Don’t Care”

x8: A12 = “Don’t Care”

*CAS latency indicated in parentheses.

-7E -75

SYMBOL* MIN MAX MIN MAX UNITS

CKS 1.5 1.5 ns

CMH 0.8 0.8 ns

CMS 1.5 1.5 ns

DH 0.8 0.8 ns

DS 1.5 1.5 ns

RCD 15 20 ns

Page 55

512Mb: x4, x8, x16

SDRAM

ADVANCE

54-PIN PLASTIC TSOP (400 mil)

SEE DETAIL A

.80 TYP

0.71

10.16 ±0.08

0.50 ±0.10

PIN #1 ID

DETAIL A

22.22 ±0.08

0.375 ±0.075

1.2 MAX

0.10

0.25

11.76 ±0.10

0.80 TYP

0.15

+0.03

-0.02

0.10

+0.10

-0.05

GAGE PLANE

NOTE: 1. All dimensions in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.

Datasheet MT48LC64M8A2TG-75, MT48LC128M4A2TG-75, MT48LC128M4A2TG-7E, MT48LC64M8A2TG-7E, MT48LC32M16A2TG-7E Datasheet (MICRON)

Specifications and Main Features

Frequently Asked Questions

User Manual