Datasheet MT34013 Datasheet (Aeroflex Circuit Technology)

MT34013

EIGHT CHANNEL ARINC DECODER

• 8/16 bit parallel interface

• 3 channels programmable to HIGH/LOW

speed data

• Single 5V supply with low power

consumption < 50mW

• Full MIL operating range

• Programmable test I/P to all channels

• Built in parity and word length error

detection

VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS

1

MT34013

MAXIMUM RATINGS (Above which the useful life may be impaired)

Storage Temperature - 65ºC to +150ºC
Temperature (Ambient) under Bias - 55ºC to +125ºC
Supply Voltage VDD -0.3V to + 7V
DC Input Voltage -0.3 to VDD +0.3V
Output Current (Single O/P) 10mA
Output Current (Total O/P) 20mA

ELECTRICAL CHARACTERISTICS over operating range

PARAMETER DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS
IOH Output High Current VOH=2.8V VDD= 4.5V 1.0
IOL Output Low Current VOL=0.4V 3.2
VIH Input High Voltage 2.4 VCC
VIL Input Low Voltage -0.3 0.8
IIL Input Load Current VSS 40
IOZ Output Leakage Current
CI Input Capacitance
CI/O I/O Capacitance 7 9
ICC Supply Current

0.4V<VO<VCC Output Disabled

Test Frequency = 1.0 MHZ

VCC = MAX. All inputs
HIGH, All inputs open.

-40 40
2 2.6

10

mA
mA
Volts
Volts
uA
uA
pF
pF
mA

ARINC 429 SERIAL INPUT INTERFACE

Interfaces are provided for 8 independent Arinc 429 serial input channels with sufficient digital storage to guarantee
no data is lost provided all 8 channels can be accessed within 230µS.

Channels 0,1 & 2 can be programmed for either high or low speed operation. Channels 3 to 7 are configured for
interfacing to low speed Arinc buses only.

Digital Filtering is incorporated on each decoder input port to prevent word corruption due to noise spikes. (The
duration of reject noise spikes is a function of the basic clock period).

Arinc have suggested that the number of labels available to the user can be increased by either using SDI bits 9 and 10
as extra label bits or by using port identification. Both of these techniques have been accommodated in the design.

DATA DETECTION AND WORD TESTS

Each channel is provided with a 32 bit shift register to hold one complete word. The three channels which are
selectable for either high or low speed operation are additionally provided with a 32 bit buffer register.

Each channel contains hardware to test the following parameters:-

(1) Word length of 32 bits.

(2) Parity:- odd on good words.

(3) Gap:- the presence of a 33rd bit is checked for and the output processing is achieved during the remaining

gap for a valid word.

(4) Interconnection fault (both I/P’s high).

VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS

2

MT34013

Prioritised error information for each channel is latched into a 3 bit register with the format indicated in Table 1 and
made available at the user output port.

Channel servicing is carried out on a rotating priority basis, where the last channel serviced is given the lowest
priority, in order to allow full access for each channel.

A facility is provided on the decoder chip to enable individual channels to be tested, which consists of a multi-plexer
on the input to each channel to allow test messages (generated external to the chip) to be injected.

TABLE 1

Prioritorised coded error data.

Bit position relative to first output word see fig.2.

15 14 13
1 1 1 ) Unused
1 1 0 )

1 0 1 Interconnection fault (highest priority)

1 0 0 Channel overrun (causes corruption of following word in that channel.

0 1 1 Word length error (number of bits not equal to 32).

0 1 0 Parity error (word received with even parity).

0 0 1 Service overrun (not all words or bytes accessed) - lowest priority.

0 0 0 Good word.

USER INTERFACE

Arinc 429 data is read from the decoder chip via an 8 or 16 bit parallel data bus.

Fig 2 illustrates the formatting of the output data relative to the generalised Arinc 429 word format.

Control of the chip is achieved via a four bit control port which provides the user with the facilities outlined in Table

2. The control word is strobed into the chip using the leading edge of the NOT CSTR input providing the required set
up and hold times are met.
N.B. NOT CSTR must be high before NOT RESET is removed.

DATA READY signifies to the user that a word is available and can be accessed by pulling NOT CHIP ENABLE low
and strobing the NOT OUTPUT SELECT line as illustrated in fig .3.

NOT RESET provides the user with a simple means of asynchronously inhibiting the chip. Activating NOT RESET
disables the output buffers and clears DATA READY asynchronously. The internal counters are cleared by holding
NOT RESET low for 2 clock periods. Default options are selected which can be overwritten using the control input
port. The default options are shown below and are selected by pulsing RESET low or by selecting software reset (see
table 2).

• Channel sequencer set to channel 0 for highest priority.

• All channels are set for low speed operation.

• All channels are set for normal reception with no end around test mode.

VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS

3

MT34013

NOT CSTR and NOT OS must be high during reset but may go low immediately NOT RESET is removed.

NOT CSTR, LOW min = HIGH min = 1.5T for correct operation CO-3, SET UP TIME = 0, HOLD TIME = 2T min
after NOT CSTR goes low.

NOT CSTR is synchronised by ØIN to give a 0.5T interval strobe pulse. This pulse disables the state decoder O/P’s
allowing 0.5T settling time for the new state to be established before re-enabling the O/P’s. This ensures that data
I/P’s cannot be internally shorted together when changing from test on one channel to another.

1

*T =

/

= 1 clock cycle time of ØIN.

f

A single phase clock must be provided by the user with a frequency in the range of 1.25 - 2.0 MHZ. The chip will
accommodate all the selectable channel speed options available with the clock at any frequency between these limits.

A 3 bit binary code is allocated in the first word of output data to signify which channel has received a message and is
being accessed.

The positioning of the code is shown in fig 2 and has the form shown below:-

1st output word bit number

12 11 10

0 0 0 Channel 0

0 0 1 Channel 1

0 1 0 Channel 2

0 1 1 Channel 3

1 0 0 Channel 4

1 0 1 Channel 5

1 1 0 Channel 6

1 1 1 Channel 7

FIG. 1

VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS

4

TABLE 2 CONTROL WORD CODES

Control bit number

C3 C2 C1 C0

0 0 0 0 Channels 0 to 7 low speed

0 0 0 1 Channel 0 high speed, channels 1 to 7 low speed

0 0 1 0 Channel 1 high speed, channels 0 and 2 to 7 low speed

0 0 1 1 Channels 0 and 1 high speed, channels 2 to 7 low speed

0 1 0 0 ( Channels 0,1 & 2 high speed

( Channels 3 to 7 low speed

0 1 0 1 ( Unused
0 1 1 0 (

0 1 1 1 Software reset

1 0 0 0 Test Channel 0

MT34013

1 0 0 1 Test Channel 1

1 0 1 0 Test Channel 2

1 0 1 1 Test Channel 3

1 1 0 0 Test Channel 4

1 1 0 1 Test Channel 5

1 1 1 0 Test Channel 6

1 1 1 1 Test Channel 7

Notes

(1) Software reset causes the same action as pulling the RESET line low but once latched into the control register

the chip is held in a quiescent mode. Exit from this mode is achieved by latching in the required channel
speed option.

(2) Exit from the test mode requires restarting the required speed options (i.e. codes 0 to 4) or loading an unused

control mode.

(3) The action of testing a channel does not alter the speed at which is set, also changing between test (i.e. test 1

to test 2) has no effect on channel speed settings.

VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS

5

MT34013

FIG. 2 MULTICHANNEL ARINC 429 RECEIVER DATA OUTPUT FORMAT

Generalised Arinc 429 word format for BNR data:-

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

PARITY SSM BITS DATA FIELD SDI BITS TAG FIELD

Byte and word output formats:-

WORD 1

BYTE 2 BYTE 1

10 9 1 2 3 4 5 6 7 8

Coded
Error
Data

24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

0 0 0 0 0 0 0 0 32 31 30 29 28 27 26 25

Port
Ident

BYTE 4 BYTE 3

DATA FIELD SDI

SDI
Bits

WORD 2

WORD 3

BYTE 5

TAG field

Bits

PAD Bits Parity SSM

Bits

Notes (1) For formats other than BNR see ARINC specification

(2) For byte output formats only 5 bytes are available but for word formats a 6th byte of all zero

bits is added to complete the 3rd word.

(3) The coded error data relates to the channel indicated by the port identifier field.

VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS

DATA field

6

FIG. 3 MULTICHANNEL ARINC 429 RECEIVER OUTPUT TIMING

MT34013

T Clock Period (500 - 800nS). Min Max

t

ON

NOT CHIP ENABLE low to output active time. 10nS 250nS

tv NOT OUTPUT SELECT low to word valid time. 300nS

t

SH (MIN)

t

SL (MIN)

minimum NOT OUTPUT SELECT high time. 400nS

minimum NOT OUTPUT SELECT low time. 400nS

tc NOT CHIP ENABLE high to DATA READY low time. 100nS 2T + 500nS

t

OFF

t

CE (MIN)

t

CEDRH

NOT CHIP ENABLE high to data bus high impedance time. 20nS 100nS

minimum time NOT CHIP ENABLE high/low. 2.5T

minimum time to select next word (CHIP ENABLE high 4T + 20nS 6T + 300nS
to DATA READY high).

Notes:-

(1) The CHIP ENABLE line going high during the select timing resets DATA READY and terminates the read

action. Not all 3 words (or 5 bytes) need to be accessed and read termination can take place at any time.

(2) The output timing for the 8 bit parallel bus is similar to the above but with 5 byte accesses required.

(3) The NOT CHIP ENABLE line cannot be held permanently low (see (1)).

(4) All timings are theoretical and are based on a load of 100pF and one standard TTL input.

(5) The NOT OUTPUT SELECT line only affects the chip when NOT CHIP ENABLE is low.

(6) In BYTE mode, NOT CHIP ENABLE low to NOT OUTPUT SELECT low, (tsu) must be > 100nS to ensure

correct BYTE output sequence.

VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS

7

ARINC 429
Receiver Subsystem

MT34013

VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS

8