Datasheet MT28F800B3WG-9BET, MT28F800B3WG-9T, MT28F800B3WG-9TET, MT28F800B3SG-9TET, MT28F800B3SG-9T Datasheet (MICRON)

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Page 1

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

FLASH MEMORY

FEATURES

• Eleven erase blocks: 16KB/8K-word boot block (protected) Two 8KB/4K-word parameter blocks Eight main memory blocks

• Smart 3 technology (B3):

3.3V ±0.3V VCC

3.3V ±0.3V VPP application programming 5V ±10% VPP application/production programming

• Compatible with 0.3µm Smart 3 device

• Advanced 0.18µm CMOS floating-gate process

• Address access time: 90ns

• 100,000 ERASE cycles

• Industry-standard pinouts

• Inputs and outputs are fully TTL-compatible

• Automated write and erase algorithm

• Two-cycle WRITE/ERASE sequence

• TSOP, SOP and FBGA packaging options

• Byte- or word-wide READ and WRITE

(MT28F800B3):

1 Meg x 8/512K x 16

MT28F008B3 MT28F800B3

3V Only, Dual Supply (Smart 3)

40-Pin TSOP Type I 48-Pin TSOP Type I

44-Pin SOP

OPTIONS MARKING

• Timing

90ns access -9

• Configurations

1 Meg x 8 MT28F008B3

512K x 16/1 Meg x 8 MT28F800B3

• Boot Block Starting Word Address

Top (7FFFFh) T Bottom (00000h) B

• Operating Temperature Range

Commercial (0ºC to +70ºC) None Extended (-40ºC to +85ºC) ET

• Packages

40-pin TSOP Type I 48-pin TSOP Type I ( 44-pin SOP (

NOTE: 1. This generation of devices does not support 12V VPP

MT28F800B3)

production programming; however, 5V VPP application production programming can be used with no loss of performance.

MT28F800B3WG-9 BET

(MT28F008B3)

MT28F800B3)

Part Number Example:

GENERAL DESCRIPTION

The MT28F008B3 (x8) and MT28F800B3 (x16/x8) are low-voltage, nonvolatile, electrically block-erasable (flash), programmable memory devices containing 8,388,608 bits organized as 524,288 words (16 bits) or 1,048,576 bytes (8 bits). Writing and erasing the device is done with a VPP voltage of either 3.3V or 5V, while all operations are performed with a 3.3V VCC. Due to process technology advances, 5V VPP is optimal for application and production programming. These devices are fabricated with Micron’s advanced 0.18µm CMOS floating-gate process.

The MT28F008B3 and MT28F800B3 are organized into eleven separately erasable blocks. To ensure that critical firmware is protected from accidental erasure or overwrite, the devices feature a hardware-protected boot block. This block may be used to store code implemented in low-level system recovery. The remaining blocks vary in density and are written and erased with no additional security measures.

Refer to Micron’s Web site (www.micron.com/flash) for the latest data sheet.

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

Page 2

A18 A17

A7 A6 A5 A4 A3 A2 A1 A0

CE#

OE#

DQ0 DQ8 DQ1 DQ9 DQ2

DQ10

DQ3

DQ11

RP# WE#

A8 A9 A10 A11 A12 A13 A14 A15 A16

BYTE# V

DQ15/(A - 1) DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23

48-Pin TSOP Type I 44-Pin SOP

A15 A14 A13 A12 A11 A10

WE#

RP#

WP#

A18 A17

A9 A8

NC NC

A7 A6 A5 A4 A3 A2 A1

1 2 3 4 5 6 7 8 9 10 11 12

13 14 15 16 17 18 19 20 21 22 23 24

ORDER NUMBER AND PART MARKING

MT28F800B3WG-9 B MT28F800B3WG-9 T MT28F800B3WG-9 BET MT28F800B3WG-9 TET

SMART 3 BOOT BLOCK FLASH MEMORY

PIN ASSIGNMENT (Top View)

A16

BYTE#

46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

DQ15/(A - 1) DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0

OE#

V CE#

8Mb

ORDER NUMBER AND PART MARKING

MT28F800B3SG-9 B MT28F800B3SG-9 T MT28F800B3SG-9 BET MT28F800B3SG-9 TET

40-Pin TSOP Type I

A16 A15 A14 A13 A12 A11

A9 A8

WE#

RP#

WP#

A18

A7 A6 A5 A4 A3 A2 A1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

ORDER NUMBER AND PART MARKING

MT28F008B3VG-9 B MT28F008B3VG-9 T MT28F008B3VG-9 BET MT28F008B3VG-9 TET

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

A17

A19 A10

DQ7 DQ6 DQ5 DQ4

V V

DQ3 DQ2 DQ1 DQ0

OE#

V CE#

Page 3

8Mb Smart 3 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

BYTE#

I/O

Control

Logic

A0–A18/(A19)

WP#

CE#

OE#

WE#

RP#

Command Execution

Logic

Addr.

Buffer/

Latch

Power

(Current)

Control

FUNCTIONAL BLOCK DIAGRAM

16KB Boot Block

19 (20)

Addr.

Counter

State

Machine

Switch/

Pump

Status

(10)

Identification

X - Decoder/Block Erase Control

Y -

Decoder

8KB Parameter Block 8KB Parameter Block

96KB Main Block

128KB Main Block

Y - Select Gates

Sense Amplifiers

Write/Erase-Bit

Compare and Verify

DQ15

Input Data Latch/Mux

Input

Buffer

Input

Buffer

Input

Buffer

A-1

SMART 3 BOOT BLOCK FLASH MEMORY

Output

Buffer

Output

Buffer

DQ15/(A - 1)

DQ8–DQ14

DQ0–DQ7

NOTE: 1. Does not apply to MT28F800B3SG.

2. Does not apply to MT28F008B3.

MUX

Output

Buffer

8Mb

Page 4

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

PIN DESCRIPTIONS

44-PIN SOP 40-PIN TSOP 48-PIN TSOP

NUMBERS NUMBERS NUMBERS SYMBOL TYPE DESCRIPTION

43 9 11 WE# Input Write Enable: Determines if a given cycle is a WRITE cycle. If

WE# is LOW, the cycle is either a WRITE to the command execution logic (CEL) or to the memory array.

– 12 14 WP# Input Write Protect: Unlocks the boot block when HIGH if VPP =

PPH

1 (3.3V) or V

ERASE. Does not affect WRITE or ERASE operation on other blocks.

12 22 26 CE# Input Chip Enable: Activates the device when LOW. When CE# is

HIGH, the device is disabled and goes into standby power mode.

44 10 12 RP# Input Reset/Power-Down: When LOW, RP# clears the status register,

sets the internal state machine (ISM) to the array read mode and places the device in deep power-down mode. All inputs, including CE#, are “Don’t Care,” and all outputs are High-Z. RP# unlocks the boot block and overrides the condition of WP# when at VHH (12V), and must be held at VIH during all other modes of operation.

14 24 28 OE# Input Output Enable: Enables data output buffers when LOW.

When OE# is HIGH, the output buffers are disabled.

33 – 47 BYTE# Input Byte Enable: If BYTE# = HIGH, the upper byte is active through

DQ8–DQ15. If BYTE# = LOW, DQ8–DQ14 are High-Z, and all data is accessed through DQ0–DQ7. DQ15/(A - 1) becomes the least significant address input.

11, 10, 9, 8,

7, 6, 5, 4, 42,

41, 40, 39, 38, 37, 36,

35, 34, 3, 2

21, 20, 19, 18, 25, 24, 23, A0–A18/ Input Address Inputs: Select a unique 16-bit word or 8-bit byte. The 17, 16, 15, 14, 22, 21, 20, (A19) DQ15/(A - 1) input becomes the lowest order address when

8, 7, 36, 6, 5, 19, 18, 8, 7, BYTE# = LOW (MT28F800B3) to allow for a selection of an 8- 4, 3, 2, 1, 40, 6, 5, 4, 3, 2, bit byte from the 1,048,576 available.

13, 37 1, 48, 17, 16

31 – 45 DQ15/ Input/ Data I/O: MSB of data when BYTE# = HIGH. Address Input: LSB

(A - 1) Output of address input when BYTE# = LOW during READ or WRITE

operation.

15, 17, 19, 21, 24, 26,

28, 30

16, 18, 20, 22, 25, 27,

25, 26, 27, 29, 31, 33, DQ0– Input/ Data I/Os: Data output pins during any READ operation or 28, 32, 33, 35, 38, 40, DQ7 Output data input pins during a WRITE. These pins are used to input

34, 35 42, 44 commands to the CEL.

– 30, 32, 34, DQ8– Input/ Data I/Os: Data output pins during any READ operation or

36, 39, 41, DQ14 Output data input pins during a WRITE when BYTE# = HIGH. These

29 43 pins are High-Z when BYTE# is LOW.

11113V

Supply Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM

until completion of the WRITE or ERASE, VPP must be at V (3.3V) or V operations.

23 30, 31 37 V

13, 32 23, 39 27, 46 V

Supply Power Supply: +3.3V ±0.3V. Supply Ground.

– 29, 38 9, 10, 15 NC – No Connect: These pins may be driven or left unconnected.

PPH

2 (5V). V

PPH

2 (5V) and RP# = V

= “Don’t Care” during all other

during a WRITE or

PPH

Page 5

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

TRUTH TABLE (MT28F800B3)

FUNCTION RP# CE# OE# WE# WP# BYTE# A0 A9 VPP DQ0–DQ7 DQ8–DQ14 DQ15/A - 1

Standby H H X X X X X X X High-Z High-Z High-Z RESET L X X X X X X X X High-Z High-Z High-Z

READ

READ (word mode) H L L H X H X X X Data-Out Data-Out Data-Out READ (byte mode) H L L H X L X X X Data-Out High-Z A-1 Output Disable H L H H X X X X X High-Z High-Z High-Z

WRITE/ERASE (EXCEPT BOOT BLOCK)

ERASE SETUP H L H L X X X X X 20h X X ERASE CONFIRM

HLHLXXXXV

PPH

D0h X X WRITE SETUP H L H L X X X X X 10h/40h X X WRITE (word mode) WRITE (byte mode) READ ARRAY

WRITE/ERASE (BOOT BLOCK)

HLHLXHXXV HLHLXLXXV

PPH

Data-In Data-In Data-In

PPH

Data-In X A-1

HLHLXXXXX FFh X X

2, 7

ERASE SETUP H L H L X X X X X 20h X X ERASE CONFIRM ERASE CONFIRM

3, 6

LHLXXXXV

HLHLHXXXV

PPH

D0h X X

D0h X X WRITE SETUP H L H L X X X X X 10h/40h X X WRITE (word mode) WRITE (word mode) WRITE (byte mode) WRITE (byte mode) READ ARRAY

DEVICE IDENTIFICATION

Manufacturer Compatibility H L L H X H L V (word mode)

Manufacturer Compatibility H L L H X L L V

4, 6

8, 9

LHLXHXXV

HLHLHHXXV

LHLXLXXV

HLHLHLXXV

PPH

Data-In Data-In Data-In

PPH

Data-In Data-In Data-In

PPH

Data-In X A-1

PPH

Data-In X A-1

HLHLXXXXX FFh X X

X 89h 00h –

X 89h High-Z X

(byte mode) Device (word mode, top boot) Device (byte mode, top boot) H L L H X L H V Device (word mode, bottom boot) Device (byte mode, bottom boot) H L L H X L H V

HL LHXHHVIDX 9Ch 88h –

X 9Ch High-Z X

HL LHXHHVIDX 9Dh 88h –

X 9Dh High-Z X

NOTE: 1. L = VIL (LOW), H = VIH (HIGH), X = VIL or VIH (“Don’t Care”).

2. VPPH = VPPH1 = 3.3V or VPPH2 = 5V.

3. Operation must be preceded by ERASE SETUP command.

4. Operation must be preceded by WRITE SETUP command.

5. The READ ARRAY command must be issued before reading the array after writing or erasing.

6. When WP# = VIH, RP# may be at VIH or VHH.

7. VHH = 12V.

8. VID = 12V; may also be read by issuing the IDENTIFY DEVICE command.

9. A1–A8, A10–A18 = VIL.

10. Value reflects DQ8–DQ15.

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8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

TRUTH TABLE (MT28F008B3)

FUNCTION RP# CE# OE# WE# WP# A0 A9 VPP DQ0–DQ7

Standby H H XXXXXXHigh-Z RESET L X XXXXXXHigh-Z

READ

READ H L L H X X X X Data-Out Output Disable H L H H X X X X High-Z

WRITE/ERASE (EXCEPT BOOT BLOCK)

ERASE SETUP H L H L X X X X 20h ERASE CONFIRM

HLHLXXXVPPH D0h

WRITE SETUP H L H L X X X X 10h/40h

WRITE READ ARRAY

WRITE/ERASE (BOOT BLOCK)

HLHLXXXVPPH Data-In HLHLXXXX FFh

2, 7

ERASE SETUP H L H L X X X X 20h ERASE CONFIRM ERASE CONFIRM

3, 6

VHH LHLXXXVPPH D0h

HLHLHXXVPPH D0h

WRITE SETUP H L H L X X X X 10h/40h

WRITE

4, 6

WRITE READ ARRAY

DEVICE IDENTIFICATION

8, 9

VHH LHLXXXVPPH Data-In

HLHLHXXVPPH Data-In HLHLXXXX FFh

Manufacturer Compatibility H L L H X L VID X 89h Device (top boot) H L L H X H VID X 98h Device (bottom boot) H L L H X H VID X 99h

NOTE: 1. L = VIL, H = VIH, X = VIL or VIH.

2. VPPH = VPPH1 = 3.3V or VPPH2 = 5V.

3. Operation must be preceded by ERASE SETUP command.

4. Operation must be preceded by WRITE SETUP command.

5. The READ ARRAY command must be issued before reading the array after writing or erasing.

6. When WP# = VIH, RP# may be at VIH or VHH.

7. VHH = 12V.

8. VID = 12V; may also be read by issuing the IDENTIFY DEVICE command.

9. A1–A8, A10–A19 = VIL.

Page 7

SMART 3 BOOT BLOCK FLASH MEMORY

FUNCTIONAL DESCRIPTION

The MT28F800B3 and MT28F008B3 Flash devices incorporate a number of features ideally suited for system firmware. The memory array is segmented into individual erase blocks. Each block may be erased without affecting data stored in other blocks. These memory blocks are read, written and erased with commands to the command execution logic (CEL). The CEL controls the operation of the internal state machine (ISM), which completely controls all WRITE, BLOCK ERASE and VERIFY operations. The ISM protects each memory location from over-erasure and optimizes each memory location for maximum data retention. In addition, the ISM greatly simplifies the control necessary for writing the device insystem or in an external programmer.

The Functional Description provides detailed information on the operation of the MT28F800B3 and MT28F008B3 and is organized into these sections:

• Overview

• Memory Architecture

• Output (READ) Operations

• Input Operations

• Command Set

• ISM Status Register

• Command Execution

• Error Handling

• WRITE/ERASE Cycle Endurance

• Power Usage

• Power-Up

OVERVIEW

SMART 3 TECHNOLOGY (B3)

Smart 3 operation allows maximum flexibility for insystem READ, WRITE and ERASE operations. WRITE and ERASE operations may be executed with a VPP voltage of

3.3V or 5V. Due to process technology advances, 5V VPP is optimal for application and production programming.

8Mb

HARDWARE-PROTECTED BOOT BLOCK

This block of the memory array can be erased or written only when the RP# pin is taken to VHH or when the WP# pin is brought HIGH. (The WP# pin does not apply to the SOP package.) This provides additional security for the core firmware during in-system firmware updates should an unintentional power fluctuation or system reset occur. The MT28F800B3 and MT28F008B3 are available with the boot block starting at the bottom of the address space (“B” suffix) and the top of the address space (“T” suffix).

SELECTABLE BUS SIZE (MT28F800B3)

The MT28F800B3 allows selection of an 8-bit (1 Meg x 8) or 16-bit (512K x 16) data bus for reading and writing the memory. The BYTE# pin is used to select the bus width. In the x16 configuration, control data is read or written only on the lower eight bits (DQ0–DQ7).

Data written to the memory array utilizes all active data pins for the selected configuration. When the x8 configuration is selected, data is written in byte form; when the x16 configuration is selected, data is written in word form.

INTERNAL STATE MACHINE (ISM)

BLOCK ERASE and BYTE/WORD WRITE timing are simplified with an ISM that controls all erase and write algorithms in the memory array. The ISM ensures protection against overerasure and optimizes write margin to each cell.

During WRITE operations, the ISM automatically increments and monitors WRITE attempts, verifies write margin on each memory cell and updates the ISM status register. When BLOCK ERASE is performed, the ISM automatically overwrites the entire addressed block (eliminates overerasure), increments and monitors ERASE attempts, and sets bits in the ISM status register.

ELEVEN INDEPENDENTLY ERASABLE MEMORY BLOCKS

The MT28F800B3 and MT28F008B3 are organized into eleven independently erasable memory blocks that allow portions of the memory to be erased without affecting the rest of the memory data. A special boot block is hardware-protected against inadvertent erasure or writing by requiring either a super-voltage on the RP# pin or driving the WP# pin HIGH. (The WP# pin does not apply to the SOP package.) One of these two conditions must exist along with the VPP voltage (3.3V or 5V) on the VPP pin before a WRITE or ERASE is performed on the boot block. The remaining blocks require that only the VPP voltage be present on the VPP pin before writing or erasing.

ISM STATUS REGISTER

The ISM status register enables an external processor to monitor the status of the ISM during WRITE and ERASE operations. Two bits of the 8-bit status register are set and cleared entirely by the ISM. These bits indicate whether the ISM is busy with an ERASE or WRITE task and when an ERASE has been suspended. Additional error information is set in three other bits: VPP status, write status and erase status.

COMMAND EXECUTION LOGIC (CEL)

The CEL receives and interprets commands to the device. These commands control the operation of the ISM and the read path (i.e., memory array, ID register or status register). Commands may be issued to the CEL

Page 8

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

while the ISM is active. However, there are restrictions on what commands are allowed in this condition. See the Command Execution section for more detail.

DEEP POWER-DOWN MODE

To allow for maximum power conservation, the MT28F800B3 and MT28F008B3 feature a very low current, deep power-down mode. To enter this mode, the RP# pin is taken to VSS ±0.2V. In this mode, the current draw is a maximum of 8µA at 3.3V VCC. Entering deep power-down also clears the status register and sets the ISM to the read array mode.

MEMORY ARCHITECTURE

The MT28F800B3 and MT28F008B3 memory array architecture is designed to allow sections to be erased without disturbing the rest of the array. The array is divided into eleven addressable blocks that vary in size and are independently erasable. When blocks rather than the entire array are erased, total device endurance is enhanced, as is system flexibility. Only the ERASE func-

Figure 1

Memory Address Maps

tion is block-oriented. All READ and WRITE operations are done on a random-access basis.

The boot block is protected from unintentional ERASE or WRITE with a hardware protection circuit which requires that a super-voltage be applied to RP# or that the WP# pin be driven HIGH before erasure is commenced. The boot block is intended for the core firmware required for basic system functionality. The remaining ten blocks do not require that either of these two conditions be met before WRITE or ERASE operations.

BOOT BLOCK

The hardware-protected boot block provides extra security for the most sensitive portions of the firmware. This 16KB block may only be erased or written when the RP# pin is at the specified boot block unlock voltage (VHH) of 12V or when the WP# pin is HIGH. During a WRITE or ERASE of the boot block, the RP# pin must be held at VHH or the WP# pin held HIGH until the WRITE or ERASE is completed. (The WP# pin does not apply to the SOP package.) The VPP pin must be at VPPH (3.3V or 5V) when the boot block is written to or erased.

WORD ADDRESS

7FFFFh

70000h

6FFFFh

60000h

5FFFFh

50000h

4FFFFh

40000h

3FFFFh

30000h

2FFFFh

20000h

1FFFFh

10000h

0FFFFh

04000h

03FFFh

03000h

02FFFh

02000h

01FFFh

00000h

BYTE ADDRESS

FFFFFh

E0000h DFFFFh

C0000h

BFFFFh

A0000h

9FFFFh

80000h

7FFFFh

60000h

5FFFFh

40000h

3FFFFh

20000h

1FFFFh

08000h

07FFFh

06000h

05FFFh

04000h

03FFFh

00000h

128KB Main Block

96KB Main Block

8KB Parameter Block 8KB Parameter Block

16KB Boot Block

Bottom Boot

MT28F008B3/800B3xx-xxB

WORD ADDRESS

7FFFFh

7E000h 7DFFFh

7D000h

7CFFFh 7C000h 7BFFFh

70000h

6FFFFh

60000h

5FFFFh

50000h

4FFFFh

40000h

3FFFFh

30000h

2FFFFh

20000h

1FFFFh

10000h

0FFFFh

00000h

BYTE ADDRESS

FFFFFh

FC000h

FBFFFh

FA000h

F9FFFh

F8000h

F7FFFh

E0000h DFFFFh

C0000h

BFFFFh

A0000h

9FFFFh

80000h

7FFFFh

60000h

5FFFFh

40000h

3FFFFh

20000h

1FFFFh

00000h

16KB Boot Block

8KB Parameter Block 8KB Parameter Block

96KB Main Block

128KB Main Block

Top Boot

MT28F008B3/800B3xx-xxT

Page 9

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

The MT28F800B3 and MT28F008B3 are available in two configurations and top or bottom boot block. The top boot block version supports processors of the x86 variety. The bottom boot block version is intended for 680X0 and RISC applications. Figure 1 illustrates the memory address maps associated with these two versions.

PARAMETER BLOCKS

The two 8KB parameter blocks store less sensitive and more frequently changing system parameters and also may store configuration or diagnostic coding. These blocks are enabled for erasure when the VPP pin is at VPPH. No super-voltage unlock or WP# control is required.

MAIN MEMORY BLOCKS

The eight remaining blocks are general-purpose memory blocks and do not require a super-voltage on RP# or WP# control to be erased or written. These blocks are intended for code storage, ROM-resident applications or operating systems that require in-system update capability.

OUTPUT (READ) OPERATIONS

The MT28F800B3 and MT28F008B3 feature three different types of READs. Depending on the current mode of the device, a READ operation produces data from the memory array, status register or device identification register. In each of these three cases, the WE#, CE# and OE# inputs are controlled in a similar manner. Moving between modes to perform a specific READ is described in the Command Execution section.

MEMORY ARRAY

To read the memory array, WE# must be HIGH, and OE# and CE# must be LOW. Valid data is output on the DQ pins when these conditions have been met, and a valid address is given. Valid data remains on the DQ pins until the address changes, or until OE# or CE# goes HIGH, whichever occurs first. The DQ pins continue to output new data after each address transition as long as OE# and CE# remain LOW.

The MT28F800B3 features selectable bus widths. When the memory array is accessed as a 512K x 16, BYTE# is HIGH, and data is output on DQ0–DQ15. To access the memory array as a 1 Meg x 8, BYTE# must be LOW, DQ8– DQ14 must be High-Z, and all data must be output on DQ0–DQ7. The DQ15/(A - 1) pin becomes the lowest order address input so that 1,048,576 locations can be read.

After power-up or RESET, the device is automatically in the array read mode. All commands and their operations are covered in the Command Set and Command Execution sections.

STATUS REGISTER

Performing a READ of the status register requires the same input sequencing as a READ of the array except that the address inputs are “Don’t Care.” The status register contents are always output on DQ0– DQ7, regardless of the condition of BYTE# on the MT28F800B3. DQ8–DQ15 are LOW when BYTE# is HIGH, and DQ8–DQ14 are High-Z when BYTE# is LOW. Data from the status register is latched on the falling edge of OE# or CE#, whichever occurs last. If the contents of the status register change during a READ of the status register, either OE# or CE# may be toggled while the other is held LOW to update the output.

Following a WRITE or ERASE, the device automatically enters the status register read mode. In addition, a READ during a WRITE or ERASE produces the status register contents on DQ0–DQ7. When the device is in the erase suspend mode, a READ operation produces the status register contents until another command is issued. In certain other modes, READ STATUS REGISTER may be given to return to the status register read mode. All commands and their operations are described in the Command Set and Command Execution sections.

IDENTIFICATION REGISTER

A READ of the two 8-bit device identification registers requires the same input sequencing as a READ of the array. WE# must be HIGH, and OE# and CE# must be LOW. However, ID register data is output only on DQ0– DQ7, regardless of the condition of BYTE# on the MT28F800B3. A0 is used to decode between the two bytes of the device ID register; all other address inputs are “Don’t Care.” When A0 is LOW, the manufacturer compatibility ID is output, and when A0 is HIGH, the device ID is output. DQ8–DQ15 are High-Z when BYTE# is LOW. When BYTE# is HIGH, DQ8–DQ15 are 00h when the manufacturer compatibility ID is read and 88h when the device ID is read.

To get to the identification register read mode, READ IDENTIFICATION may be issued while the device is in certain other modes. In addition, the identification register read mode can be reached by applying a super-voltage (VID) to the A9 pin. Using this method, the ID register can be read while the device is in any mode. When A9 is returned to VIL or VIH, the device returns to the previous mode.

INPUT OPERATIONS

The DQ pins are used either to input data to the array or to input a command to the CEL. A command input issues an 8-bit command to the CEL to control the mode of operation of the device. A WRITE is used to input data to the memory array. The following section de-

Page 10

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

scribes both types of inputs. More information describing how to use the two types of inputs to write or erase the device is provided in the Command Execution section.

COMMANDS

To perform a command input, OE# must be HIGH, and CE# and WE# must be LOW. Addresses are “Don’t Care” but must be held stable, except during an ERASE CONFIRM (described in a later section). The 8-bit command is input on DQ0–DQ7, while DQ8–DQ15 are “Don’t Care” on the MT28F800B3. The command is latched on the rising edge of CE# (CE#-controlled) or WE# (WE#controlled), whichever occurs first. The condition of BYTE# on the MT28F800B3 has no effect on a command input.

MEMORY ARRAY

A WRITE to the memory array sets the desired bits to logic 0s but cannot change a given bit to a logic 1 from a logic 0. Setting any bits to a logic 1 requires that the entire block be erased. To perform a WRITE, OE# must be HIGH, CE# and WE# must be LOW, and VPP must be set to VPPH1 or VPPH2. Writing to the boot block also requires that the

RP# pin be at VHH or WP# be HIGH. A0–A18 (A19) provide the address to be written, while the data to be written to the array is input on the DQ pins. The data and addresses are latched on the rising edge of CE# (CE#-controlled) or WE# (WE#-controlled), whichever occurs first. A WRITE must be preceded by a WRITE SETUP command. Details on how to input data to the array are described in the Write Sequence section.

Selectable bus sizing applies to WRITEs as it does to READs on the MT28F800B3. When BYTE# is LOW (byte mode), data is input on DQ0–DQ7, DQ8–DQ14 are HighZ, and DQ15 becomes the lowest order address input. When BYTE# is HIGH (word mode), data is input on DQ0– DQ15.

COMMAND SET

To simplify writing of the memory blocks, the MT28F800B3 and MT28F008B3 incorporate an ISM that controls all internal algorithms for writing and erasing the floating gate memory cells. An 8-bit command set is used to control the device. Details on how to sequence commands are provided in the Command Execution section. Table 1 lists the valid commands.

Table 1

Command Set

COMMAND HEX CODE DESCRIPTION

RESERVED 00h This command and all unlisted commands are invalid and should not

be called. These commands are reserved to allow for future feature enhancements.

READ ARRAY FFh Must be issued after any other command cycle before the array can be

read. It is not necessary to issue this command after power-up or RESET.

IDENTIFY DEVICE 90h Allows the device and manufacturer compatibility ID to be read. A0 is

used to decode between the manufacturer compatibility ID (A0 = LOW) and device ID (A0 = HIGH).

READ STATUS REGISTER 70h Allows the status register to be read. Please refer to Table 2 for more

information on the status register bits. CLEAR STATUS REGISTER 50h Clears status register bits 3-5, which cannot be cleared by the ISM. ERASE SETUP 20h The first command given in the two-cycle ERASE sequence. The ERASE is

not completed unless followed by ERASE CONFIRM. ERASE CONFIRM/RESUME D0h The second command given in the two-cycle ERASE sequence. Must follow

an ERASE SETUP command to be valid. Also used during an ERASE

SUSPEND to resume the ERASE. WRITE SETUP 40h or The first command given in the two-cycle WRITE sequence. The write

10h data and address are given in the following cycle to complete the WRITE.

ERASE SUSPEND B0h Requests a halt of the ERASE and puts the device into the erase suspend

mode. When the device is in this mode, only READ STATUS REGISTER,

READ ARRAY and ERASE RESUME commands may be executed.

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SMART 3 BOOT BLOCK FLASH MEMORY

ISM STATUS REGISTER

The 8-bit ISM status register (see Table 2) is polled to check for WRITE or ERASE completion or any related errors. During or following a WRITE, ERASE or ERASE SUSPEND, a READ operation outputs the status register contents on DQ0–DQ7 without prior command. While the status register contents are read, the outputs are not be updated if there is a change in the ISM status unless OE# or CE# is toggled. If the device is not in the write, erase, erase suspend or status register read mode, READ STATUS REGISTER (70h) can be issued to view the status register contents.

Table 2

Status Register Bit Definitions

ISMS ESS ES WS VPPSR

765432–0

8Mb

All of the defined bits are set by the ISM, but only the ISM and erase suspend status bits are reset by the ISM. The erase, write and VPP status bits must be cleared using CLEAR STATUS REGISTER. If the VPP status bit (SR3) is set, the CEL does not allow further WRITE or ERASE operations until the status register is cleared. This enables the user to choose when to poll and clear the status register. For example, the host system may perform multiple BYTE WRITE operations before checking the status register instead of checking after each individual WRITE. Asserting the RP# signal or powering down the device also clears the status register.

STATUS

BIT # STATUS REGISTER BIT DESCRIPTION

SR7 ISM STATUS (ISMS) The ISMS bit displays the active status of the state machine during

1 = Ready WRITE or BLOCK ERASE operations. The controlling logic polls this 0 = Busy bit to determine when the erase and write status bits are valid.

SR6 ERASE SUSPEND STATUS (ESS) Issuing an ERASE SUSPEND places the ISM in the suspend mode

1 = ERASE suspended and sets this and the ISMS bit to “1.” The ESS bit remains “1” 0 = ERASE in progress/completed until an ERASE RESUME is issued.

SR5 ERASE STATUS (ES) ES is set to “1” after the maximum number of ERASE cycles is

1 = BLOCK ERASE error executed by the ISM without a successful verify. ES is only cleared 0 = Successful BLOCK ERASE by a CLEAR STATUS REGISTER command or after a RESET.

SR4 WRITE STATUS (WS) WS is set to “1” after the maximum number of WRITE cycles is

1 = WORD/BYTE WRITE error executed by the ISM without a successful verify. WS is only cleared 0 = Successful WORD/BYTE WRITE by a CLEAR STATUS REGISTER command or after a RESET.

SR3 VPP STATUS (VPPS) VPPS detects the presence of a VPP voltage. It does not monitor VPP

1 = No VPP voltage detected continuously, nor does it indicate a valid VPP voltage. The VPP pin 0 = VPP present is sampled for 3.3V or 5V after WRITE or ERASE CONFIRM is given.

VPPS must be cleared by CLEAR STATUS REGISTER or by a RESET.

SR0-2 RESERVED Reserved for future use.

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SMART 3 BOOT BLOCK FLASH MEMORY

COMMAND EXECUTION

Commands are issued to bring the device into different operational modes. Each mode allows specific operations to be performed. Several modes require a sequence of commands to be written before they are reached. The following section describes the properties of each mode, and Table 3 lists all command sequences required to perform the desired operation.

READ ARRAY

The array read mode is the initial state of the device upon power-up and after a RESET. If the device is in any other mode, READ ARRAY (FFh) must be given to return to the array read mode. Unlike the WRITE SETUP command (40h), READ ARRAY does not need to be given before each individual READ access.

IDENTIFY DEVICE

IDENTIFY DEVICE (90h) may be written to the CEL to enter the identify device mode. While the device is in this mode, any READ produces the device identification when A0 is HIGH and the manufacturer compatibility identification when A0 is LOW. The device remains in this mode until another command is given.

8Mb

WRITE SEQUENCE

Two consecutive cycles are needed to input data to the array. WRITE SETUP (40h or 10h) is given in the first cycle. The next cycle is the WRITE, during which the write address and data are issued and VPP is brought to VPPH. Writing to the boot block also requires that the RP# pin be brought to VHH or the WP# pin be brought HIGH at the same time VPP is brought to VPPH. The ISM now begins to write the word or byte. VPP must be held at VPPH until the WRITE is completed (SR7 = 1).

While the ISM executes the WRITE, the ISM status bit (SR7) is at 0, and the device does not respond to any commands. Any READ operation produces the status register contents on DQ0–DQ7. When the ISM status bit (SR7) is set to a logic 1, the WRITE has been completed, and the device goes into the status register read mode until another command is given.

After the ISM has initiated the WRITE, it cannot be aborted except by a RESET or by powering down the part. Doing either during a WRITE corrupts the data being written. If only the WRITE SETUP command has been given, the WRITE may be nullified by performing a null WRITE. To execute a null WRITE, FFh must be written

Table 3

Command Sequences

BUS FIRST SECOND

CYCLES CYCLE CYCLE

COMMANDS REQ’D OPERATION ADDRESS DATA OPERATIONADDRESS DATA NOTES

READ ARRAY 1 WRITE X FFh 1 IDENTIFY DEVICE 3 WRITE X 90h READ IA ID 2, 3 READ STATUS REGISTER 2 WRITE X 70h READ X SRD 4 CLEAR STATUS REGISTER 1 WRITE X 50h ERASE SETUP/CONFIRM 2 WRITE X 20h WRITE BA D0h 5, 6 ERASE SUSPEND/RESUME 2 WRITE X B0h WRITE X D0h WRITE SETUP/WRITE 2 WRITE X 40h WRITE WA WD 6, 7 ALTERNATE WORD/BYTE 2 WRITE X 10h WRITE WA WD 6, 7

WRITE

NOTE: 1. Must follow WRITE or ERASE CONFIRM commands to the CEL in order to enable Flash array READ cycles.

2. IA = Identify Address: 00h for manufacturer compatibility ID; 01h for device ID.

3. ID = Identify Data.

4. SRD = Status Register Data.

5. BA = Block Address (A12–A19).

6. Addresses are “Don’t Care” in first cycle but must be held stable.

7. WA = Address to be written; WD = Data to be written to WA.

Page 13

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SMART 3 BOOT BLOCK FLASH MEMORY

when BYTE# is LOW, or FFFFh must be written when BYTE# is HIGH. When the ISM status bit (SR7) has been set, the device is in the status register read mode until another command is issued.

ERASE SEQUENCE

Executing an ERASE sequence sets all bits within a block to logic 1. The command sequence necessary to execute an ERASE is similar to that of a WRITE. To provide added security against accidental block erasure, two consecutive command cycles are required to initiate an ERASE of a block. In the first cycle, addresses are “Don’t Care,” and ERASE SETUP (20h) is given. In the second cycle, VPP must be brought to VPPH, an address within the block to be erased must be issued, and ERASE CONFIRM (D0h) must be given. If a command other than ERASE CONFIRM is given, the write and erase status bits (SR4 and SR5) are set, and the device is in the status register read mode.

After the ERASE CONFIRM (D0h) is issued, the ISM starts the ERASE of the addressed block. Any READ operation outputs the status register contents on DQ0– DQ7. VPP must be held at VPPH until the ERASE is completed (SR7 = 1). When the ERASE is completed, the device is in the status register read mode until another command is issued. Erasing the boot block also requires

that either the RP# pin be set to VHH or the WP# pin be held HIGH at the same time VPP is set to VPPH.

ERASE SUSPENSION

The only command that may be issued while an ERASE is in progress is ERASE SUSPEND. This command enables other commands to be executed while pausing the ERASE in progress. When the device has reached the erase suspend mode, the erase suspend status bit (SR6) and ISM status bit (SR7) are set. The device may now be given a READ ARRAY, ERASE RESUME or READ STATUS REGISTER command. After READ ARRAY has been issued, any location not within the block being erased may be read. If ERASE RESUME is issued before SR6 has been set, the device immediately proceeds with the ERASE in progress.

ERROR HANDLING

After the ISM status bit (SR7) has been set, the VPP (SR3), write (SR4) and erase (SR5) status bits may be checked. If one or a combination of these three bits has been set, an error has occurred. The ISM cannot reset these three bits. To clear these bits, CLEAR STATUS REGISTER (50h) must be given. If the VPP status bit (SR3) is set, further WRITE or ERASE operations cannot resume until the status register is cleared. Table 4 lists the combination of errors.

Table 4

Status Register Error Code Description

STATUS BITS

SR5 SR4 SR3 ERROR DESCRIPTION

0 0 0 No errors 001VPP voltage error 0 1 0 WRITE error 0 1 1 WRITE error, VPP voltage not valid at time of WRITE 1 0 0 ERASE error 1 0 1 ERASE error, VPP voltage not valid at time of ERASE CONFIRM 1 1 0 Command sequencing error or WRITE/ERASE error 1 1 1 Command sequencing error, VPP voltage error, with WRITE and ERASE errors

NOTE: 1. SR3-SR5 must be cleared using CLEAR STATUS REGISTER.

Page 14

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SMART 3 BOOT BLOCK FLASH MEMORY

WRITE/ERASE CYCLE ENDURANCE

The MT28F800B3 and MT28F008B3 are designed and fabricated to meet advanced firmware storage requirements. To ensure this level of reliability, VPP must be at

3.3V ±0.3V or 5V ±10% during WRITE or ERASE cycles. Due to process technology advances, 5V VPP is optimal for application and production programming.

POWER USAGE

The MT28F800B3 and MT28F008B3 offer several power-saving features that may be utilized in the array read mode to conserve power. Deep power-down mode is enabled by bringing RP# LOW. Current draw (ICC) in this mode is a maximum of 8µA at 3.3V VCC. When CE# is HIGH, the device enters standby mode. In this mode, maximum ICC current is 100µA at 3.3V VCC. If CE# is brought HIGH during a WRITE or ERASE, the ISM continues to operate, and the device consumes the respective active power until the WRITE or ERASE is completed.

POWER-UP

The likelihood of unwanted WRITE or ERASE operations is minimized because two consecutive cycles are required to execute either operation. However, to reset the ISM and to provide additional protection while VCC is ramping, one of the following conditions must be met:

• RP# must be held LOW until VCC is at valid functional level; or

• CE# or WE# may be held HIGH and RP# must be toggled from VCC-GND-VCC.

After a power-up or RESET, the status register is reset,

and the device enters the array read mode.

Figure 2

Power-Up/Reset Timing Diagram

RP#

Note 1

(3.3V)

Address

VALID

Data

RWH

VALID

UNDEFINED

NOTE: 1. VCC must be within the valid operating range before RP#

goes HIGH.

Page 15

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SMART 3 BOOT BLOCK FLASH MEMORY

SELF-TIMED WRITE SEQUENCE

(WORD OR BYTE WRITE)

Start

WRITE 40h or 10h

VPP = 3.3V or 5V

WRITE Word or Byte

Address/Data

STATUS REGISTER

READ

COMPLETE WRITE STATUS-CHECK

SEQUENCE

Start (WRITE completed)

SR3 = 0?

YES

SR4 = 0?

YES

WRITE Successful

V Error

BYTE/WORD WRITE Error

4, 5

SR7 = 1?

YES

Complete Status

Check (optional)

WRITE Complete

NOTE: 1. Sequence may be repeated for additional BYTE or WORD WRITEs.

2. Complete status check is not required. However, if SR3 = 1, further WRITEs are inhibited until the status register is cleared.

3. Device will be in status register read mode. To return to the array read mode, the FFh command must be issued.

4. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE or ERASE operations are allowed by the CEL.

5. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.

Page 16

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

SELF-TIMED BLOCK ERASE SEQUENCE

Start

WRITE 20h

VPP = 3.3V or 5V

WRITE D0h,

Block Address

STATUS REGISTER

READ

SR7 = 1?

Suspend ERASE?

Busy

ERASE

COMPLETE BLOCK ERASE

STATUS-CHECK SEQUENCE

Start (ERASE completed)

SR3 = 0?

YES

SR4, 5 = 1?

SR5 = 0?

YES

ERASE Successful

YES

V Error

Command Sequence Error

BLOCK ERASE Error

5, 6

YES

Complete Status

Check (optional)

ERASE Complete

NOTE: 1. Sequence may be repeated to erase additional blocks.

2. Complete status check is not required. However, if SR3 = 1, further ERASEs are inhibited until the status register is cleared.

3. To return to the array read mode, the FFh command must be issued.

4. Refer to the ERASE SUSPEND flowchart for more information.

5. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE or ERASE operations are allowed by the CEL.

6. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.

YES

Suspend

Sequence

ERASE Resumed

Page 17

SMART 3 BOOT BLOCK FLASH MEMORY

ERASE SUSPEND/RESUME SEQUENCE

Start (ERASE in progress)

WRITE B0h

(ERASE SUSPEND)

VPP = 3.3V or 5V

STATUS REGISTER

READ

8Mb

SR7 = 1?

YES

SR6 = 1?

YES

WRITE FFh

(READ ARRAY)

Done

Reading?

YES

WRITE D0h

(ERASE RESUME)

Resume ERASE

ERASE Completed

Page 18

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SMART 3 BOOT BLOCK FLASH MEMORY

ABSOLUTE MAXIMUM RATINGS*

Voltage on VCC Supply

Relative to VSS ..................................... -0.5V to +4V**

Input Voltage Relative to VSS .................... -0.5V to +4V**

VPP Voltage Relative to VSS ........................ -0.5V to +5.5V

RP# or A9 Pin Voltage

Relative to VSS ................................ -0.5V to +12.6V

Temperature Under Bias.......................... -10ºC to +80ºC

Storage Temperature (plastic) ............... -55ºC to +125ºC

Power Dissipation ......................................................... 1W

†

††

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **VCC, input and I/O pins may transition to -2V for <20ns and VCC + 2V for <20ns.

†

Voltage may pulse to -2V for <20ns and 7V for <20ns.

††

Voltage may pulse to -2V for <20ns and 14V for <20ns.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC READ OPERATING CONDITIONS

Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

3.3V Supply Voltage VCC 3 3.6 V 1 Input High (Logic 1) Voltage, all inputs VIH 2.4 VCC + 0.5 V 1 Input Low (Logic 0) Voltage, all inputs VIL -0.5 0.8 V 1 Device Identification Voltage, A9 VID 10 12.6 V 1 VPP Supply Voltage VPP -0.5 5.5 V 1

DC OPERATING CHARACTERISTICS

Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

OUTPUT VOLTAGE LEVELS VOH VCC - 0.2 – V Output High Voltage (IOH = -100µA) 1 Output Low Voltage (IOL = 2mA) VOL – 0.45 V

INPUT LEAKAGE CURRENT Any input (0V ≤ VIN ≤ VCC); IL -1 1 µA All other pins not under test = 0V

INPUT LEAKAGE CURRENT: A9 INPUT IID – 500 µA (10V ≤ A9 ≤ 12V = VID)

INPUT LEAKAGE CURRENT: RP# INPUT IHH – 500 µA (10V ≤ RP# ≤ 12V = VHH)

OUTPUT LEAKAGE CURRENT IOZ -10 10 µA (DOUT is disabled; 0V ≤ VOUT ≤ VCC)

NOTE: 1. All voltages referenced to VSS.

Page 19

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SMART 3 BOOT BLOCK FLASH MEMORY

CAPACITANCE

(TA = 25ºC; f = 1 MHz)

PARAMETER/CONDITION SYMBOL MAX UNITS NOTES

Input Capacitance CI 9pF Output Capacitance CO 12 pF

READ AND STANDBY CURRENT DRAIN

Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC)

PARAMETER/CONDITION SYMBOL MAX UNITS NOTES

READ CURRENT: WORD-WIDE (CE# ≤ 0.2V; OE#  VCC - 0.2V; f = 5 MHz; ICC1 15 mA 2, 3 Other inputs ≤ 0.2V or  VCC - 0.2V; RP#  VCC - 0.2V)

READ CURRENT: BYTE-WIDE (CE# ≤ 0.2V; OE#  VCC - 0.2V; f = 5 MHz; ICC2 15 mA 2, 3 Other inputs ≤ 0.2V or  VCC - 0.2V; RP# = VCC - 0.2V)

STANDBY CURRENT: TTL INPUT LEVELS VCC power supply standby current ICC3 2mA (CE# = RP# = VIH; Other inputs = VIL or VIH)

STANDBY CURRENT: CMOS INPUT LEVELS VCC power supply standby current ICC4 100 µA (CE# = RP# = VCC - 0.2V)

DEEP POWER-DOWN CURRENT: VCC SUPPLY ICC6 8µA (RP# = VSS ±0.2V)

STANDBY OR READ CURRENT: VPP SUPPLY IPP1 ±15 µA (VPP ≤ 5.5V)

DEEP POWER-DOWN CURRENT: VPP SUPPLY IPP2 5µA (RP# = VSS ±0.2V)

NOTE: 1. VCC = MAX VCC during ICC tests.

2. ICC is dependent on cycle rates.

3. ICC is dependent on output loading. Specified values are obtained with the outputs open.

Page 20

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SMART 3 BOOT BLOCK FLASH MEMORY

READ TIMING PARAMETERS ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC); VCC = +3.3V ±0.3V

AC CHARACTERISTICS -9/-9 ET PARAMETER SYMBOL MIN MAX UNITS NOTES

READ cycle time Access time from CE# Access time from OE# Access time from address RP# HIGH to output valid delay OE# or CE# HIGH to output in High-Z Output hold time from OE#, CE# or address change RP# LOW pulse width

NOTE: 1. Measurements tested under AC Test Conditions.

2. OE# may be delayed by tACE minus tAOE after CE# falls before tACE is affected.

RC 90 ns

ACE 90 ns 2

AOE 40 ns 2

AA 90 ns

RWH 1,000 ns

OD 25 ns

OH 0 ns

RP 150 ns

AC TEST CONDITIONS

Input pulse levels ...................................................... 0V to 3V

Input rise and fall times ................................................ <10ns

Input timing reference level ........................................... 1.5V

Output timing reference level ........................................ 1.5V

Output load ................................... 1 TTL gate and C

L = 50pF

Page 21

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SMART 3 BOOT BLOCK FLASH MEMORY

A0–A18/(A19)

CE#

OE#

WE#

DQ0–DQ15

RP#

WORD-WIDE READ CYCLE

RWH

ACE

AOE

VALID ADDRESS

VALID DATA

DON’T CARE

TIMING PARAMETERS

Commercial Temperature (0ºC ≤ TA ≤ +70ºC) Extended Temperature (-40ºC ≤ TA ≤ +85ºC)

-9/-9 ET

SYMBOL MIN MAX UNITS

RC 90 ns

ACE 90 ns

AOE 40 ns

AA 90 ns

UNDEFINED

-9/-9 ET

SYMBOL MIN MAX UNITS

RWH 1,000 ns

OD 25 ns

OH 0 ns

NOTE: 1. BYTE# = HIGH (MT28F800B3 only).

Page 22

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SMART 3 BOOT BLOCK FLASH MEMORY

A0–A18/(A19)

CE#

OE#

WE#

DQ0–DQ7

DQ8–DQ14

BYTE-WIDE READ CYCLE

HIGH-Z

RWH

ACE

AOE

VALID ADDRESS

VALID DATA

RP#

TIMING PARAMETERS

Commercial Temperature (0ºC ≤ TA ≤ +70ºC) Extended Temperature (-40ºC ≤ TA ≤ +85ºC)

-9/-9 ET

SYMBOL MIN MAX UNITS

RC 90 ns

ACE 90 ns

AOE 40 ns

AA 90 ns

DON’T CARE

UNDEFINED

-9/-9 ET

SYMBOL MIN MAX UNITS

RWH 1,000 ns

OD 25 ns

OH 0 ns

NOTE: 1. BYTE# = LOW (MT28F800B3 only).

Page 23

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SMART 3 BOOT BLOCK FLASH MEMORY

RECOMMENDED DC WRITE/ERASE CONDITIONS

Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC); VCC = +3.3V ±0.3V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

VPP WRITE/ERASE lockout voltage VPPLK – 1.5 V 2 VPP voltage during WRITE/ERASE operation VPPH1 3.0 3.6 V 3 VPP voltage during WRITE/ERASE operation VPPH2 4.5 5.5 V Boot block unlock voltage VHH 10 12.6 V VCC WRITE/ERASE lockout voltage VLKO 2–V

WRITE/ERASE CURRENT DRAIN

Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC - TA - +85ºC); VCC = +3.3V ±0.3V

3.3V VPP 5V VPP

PARAMETER/CONDITION SYMBOL MAX MAX UNITS NOTES

WORD WRITE CURRENT: VCC SUPPLY ICC7 20 20 mA 5 WORD WRITE CURRENT: VPP SUPPLY IPP3 20 20 mA 5 BYTE WRITE CURRENT: VCC SUPPLY ICC8 20 20 mA 6 BYTE WRITE CURRENT: VPP SUPPLY IPP4 20 20 mA 6 ERASE CURRENT: VCC SUPPLY ICC9 25 25 mA ERASE CURRENT: VPP SUPPLY IPP5 25 30 mA ERASE SUSPEND CURRENT: VCC SUPPLY ICC10 810mA7

(ERASE suspended) ERASE SUSPEND CURRENT: VPP SUPPLY IPP6 200 200 µA

(ERASE suspended)

NOTE: 1. WRITE operations are tested at VPP voltages equal to or less than the previous ERASE.

2. Absolute WRITE/ERASE protection when VPP ≤ VPPLK.

3. When 3.3V VCC and VPP are used, VCC cannot exceed VPP by more than 500mV during WRITE and ERASE operations.

4. All currents are in RMS unless otherwise noted.

5. Applies to MT28F800B3 only.

6. Applies to MT28F008B3 and MT28F800B3 with BYTE# = LOW.

7. Parameter is specified when device is not accessed. Actual current draw will be ICC10 plus read current if a READ is executed while the device is in erase suspend mode.

Page 24

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SMART 3 BOOT BLOCK FLASH MEMORY

SPEED-DEPENDENT WRITE/ERASE AC TIMING CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS: WE# (CE#)-CONTROLLED WRITES

Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC); VCC = +3.3V ±0.3V

AC CHARACTERISTICS -9/-9 ET PARAMETER SYMBOL MIN MAX UNITS NOTES

WRITE cycle time WE# (CE#) HIGH pulse width WE# (CE#) pulse width Address setup time to WE# (CE#) HIGH Address hold time from WE# (CE#) HIGH Data setup time to WE# (CE#) HIGH Data hold time from WE# (CE#) HIGH CE# (WE#) setup time to WE# (CE#) LOW CE# (WE#) hold time from WE# (CE#) HIGH VPP setup time to WE# (CE#) HIGH VPP setup time to WE# (CE#) HIGH RP# HIGH to WE# (CE#) LOW delay RP# at VHH or WP# HIGH setup time to WE# (CE#) HIGH WRITE duration (WORD or BYTE WRITE) Boot BLOCK ERASE duration Parameter BLOCK ERASE duration Main BLOCK ERASE duration WE# (CE#) HIGH to busy status (SR7 = 0) VPP hold time from status data valid RP# at VHH or WP# HIGH hold time from status data valid Boot block relock delay time

WC 90 ns

WPH (tCPH) 20 ns

WP (tCP) 50 ns

AS 50 ns

AH 0 ns

DS 50 ns

DH 0 ns

CS (tWS) 0 ns

CH (tWH) 0 ns

VPS1 200 ns 1

VPS2 100 ns 2

RS 1,000 ns

RHS 100 ns 3

WED1 2 µs 5

WED2 100 ms 5

WED3 100 ms 5

WED4 500 ms 5

WB 200 ns 4

VPH 0 ns 5

RHH 0 ns 3

REL 100 ns 6

WORD/BYTE WRITE AND ERASE DURATION CHARACTERISTICS

3.3V VPP 5V VPP

PARAMETER TYP MAX TYP MAX UNITS NOTES

Boot/parameter BLOCK ERASE time 0.5 7 0.4 7 s 7 Main BLOCK ERASE time 2.8 14 1.5 14 s 7 Main BLOCK WRITE time (byte mode) 1.5 – 1 – s 7, 8, 9 Main BLOCK WRITE time (word mode) 1.5 – 1 – s 7, 8, 9

NOTE: 1. Measured with VPP = VPPH1 = 3.3V.

2. Measured with VPP = VPPH2 = 5V.

3. RP# should be held at VHH or WP# held HIGH until boot block WRITE or ERASE is complete.

4. Polling status register before tWB is met may falsely indicate WRITE or ERASE completion.

5. WRITE/ERASE times are measured to valid status register data (SR7 = 1).

6.tREL is required to relock boot block after WRITE or ERASE to boot block.

7. Typical values measured at TA = +25ºC.

8. Assumes no system overhead.

9. Typical WRITE times use checkerboard data pattern.

Page 25

A0–A18/(A19)

CE#

OE#

WE#

DQ0–DQ7/

DQ0–DQ15

RP#

WP#

VPP

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

WRITE/ERASE CYCLE

WE#-CONTROLLED WRITE/ERASE

PPH2

PPH1

Note 1

CMD

WPH

RHS

VPS1 t

VPS2

AIN

CMD/

Data-in

[Unlock boot block]

[3.3V VPP]

WED1/2/3/4

[5V VPP]

Status

(SR7=0)

Status

(SR7=1)

RHH

VPH

CMD

WRITE SETUP or

ERASE SETUP input

WRITE or ERASE (block)

address asserted, and WRITE data or ERASE

CONFIRM issued

WRITE or ERASE

executed, status register

checked for completion

Command for next

operation issued

DON’T CARE

TIMING PARAMETERS

Commercial Temperature (0ºC ≤ TA ≤ +70ºC) Extended Temperature (-40ºC ≤ TA ≤ +85ºC)

-9/-9 ET

SYMBOL MIN MAX UNITS

WC 90 ns

WPH 20 ns

WP 50 ns

AS 50 ns

AH 0 ns

DS 50 ns

DH 0 ns

CS 0 ns

CH 0 ns

VPS1 200 ns

SYMBOL MIN MAX UNITS

VPS2 100 ns

RS 1,000 ns

RHS 100 ns

WED1 2 µs

WED2 100 ms

WED3 100 ms

WED4 500 ms

WB 200 ns

VPH 0 ns

RHH 0 ns

NOTE: 1. Address inputs are “Don’t Care” but must be held stable.

2. If BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit.

3. Either RP# at VHH or WP# HIGH unlocks the boot block.

-9/-9 ET

Page 26

A0–A18/(A19)

WE#

OE#

CE#

DQ0–DQ7/

DQ0–DQ15

RP#

WP#

VPP

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

WRITE/ERASE CYCLE

CE#-CONTROLLED WRITE/ERASE

PPH2

PPH1

Note 1

CMD

CPH

RHS

VPS1 t

VPS2

AIN

CMD/

Data-in

[Unlock boot block]

[3.3V VPP]

WED1/2/3/4

[5V VPP]

Status

(SR7=0)

Status

(SR7=1)

RHH

VPH

CMD

WRITE or ERASE (block)

WRITE SETUP or

ERASE SETUP input

address asserted, and

WRITE data or ERASE

CONFIRM issued

TIMING PARAMETERS

Commercial Temperature (0ºC ≤ TA ≤ +70ºC) Extended Temperature (-40ºC ≤ TA ≤ +85ºC)

-9/-9 ET

SYMBOL MIN MAX UNITS

WC 90 ns

CPH 20 ns

CP 50 ns

AS 50 ns

AH 0 ns

DS 50 ns

DH 0 ns

WS 0 ns

WH 0 ns

VPS1 200 ns

NOTE: 1. Address inputs are “Don’t Care” but must be held stable.

2. If BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit.

3. Either RP# at VHH or WP# HIGH unlocks the boot block.

WRITE or ERASE

executed, status register

checked for completion

Command for next

operation issued

DON’T CARE

-9/-9 ET

SYMBOL MIN MAX UNITS

VPS2 100 ns

RS 1,000 ns

RHS 100 ns

WED1 2 µs

WED2 100 ms

WED3 100 ms

WED4 500 ms

WB 200 ns

VPH 0 ns

RHH 0 ns

Page 27

.0197 (0.50)

TYP

PIN #1 INDEX

.010 (0.25) .006 (0.15)

SMART 3 BOOT BLOCK FLASH MEMORY

40-PIN PLASTIC TSOP I

(10mm x 20mm)

.795 (20.20) .780 (19.80) .727 (18.47) .721 (18.31)

20 21

8Mb

.010 (0.25)

.397 (10.08)

.391 (9.93)

.010 (0.25)

.007 (0.18) .005 (0.13)

SEE DETAIL A

.047 (1.20)

MAX

.004 (0.10)

.008 (0.20) .002 (0.05)

DETAIL A

.0315 (0.80)

PLANE

.024 (0.60) .016 (0.40)

GAGE

NOTE: 1. All dimensions in inches (millimeters)

MAX

or typical where noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side.

Page 28

.0197 (0.50)

TYP

PIN #1 INDEX

.010 (0.25) .006 (0.15)

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

48-PIN PLASTIC TSOP I

(12mm x 20mm)

.795 (20.20) .780 (19.80) .727 (18.47) .721 (18.31)

.010 (0.25)

.475 (12.07) .469 (11.91)

.007 (0.18) .005 (0.12)

SEE DETAIL A

.047 (1.20) MAX

.004 (0.10)

.008 (0.20) .002 (0.05)

DETAIL A

.010 (0.25)

.0315 (0.80)

GAGE

PLANE

.024 (0.60) .016 (0.40)

NOTE: 1. All dimensions in inches (millimeters)

MAX

or typical where noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side.

Page 29

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

.050 (1.27)

PIN #1 INDEX

TYP

1.113 (28.27)

1.107 (28.12)

44-PIN PLASTIC SOP

(600 mil)

.020 (0.50) .015 (0.38)

.499 (12.68) .493 (12.52)

.030 (0.76)

.007 (0.18) .005 (0.13)

.643 (16.34) .620 (15.74)

SEE DETAIL A

.004 (0.10)

NOTE: 1. Not recommended for new designs.

2. All dimensions in inches (millimeters)

3. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side.

.106 (2.70) MAX

MAX

or typical where noted.

MIN

GAGE PLANE

.010 (0.25)

.0315 (0.80)

.016 (0.40) .010 (0.25)

DETAIL A

(ROTATED 90 CW)

.066 (1.72)

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

The Micron logo and the M logo are trademarks of Micron Technology, Inc.

Page 30

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

REVISION HISTORY

Rev. 3, Pub. 10/01 ................................................................................................................................................... 10/01

• Updated input capacitance spec

• Changed access time to 90ns

Rev. 2 ......................................................................................................................................................................................... 3/01

• Changed to 0.18µm process

• 12V VPP no longer supported

• 10V ≤ VHH ≤ 12V

•VOH ≤ VCC - 0.2V

•tRWH changed to 1µs from 800ns

•tAH changed to 10ns from 0ns

• AC test output load CL changed to 50pF

• Typical main BLOCK ERASE time changed to 1.5s from 1s

• Typical main BLOCK WRITE time (byte mode) changed to 1s from 0.5s

• Typical main BLOCK WRITE time (word mode) changed to 1s from 0.5s

• MT28F800B3 only available in WG and SG packages

• MT28F008B3 only available in VG package

• Added 80ns access time for commercial and extended temperature ranges

Datasheet MT28F800B3WG-9BET, MT28F800B3WG-9T, MT28F800B3WG-9TET, MT28F800B3SG-9TET, MT28F800B3SG-9T Datasheet (MICRON)

Specifications and Main Features

Frequently Asked Questions

User Manual

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PIN DESCRIPTIONS

TRUTH TABLE (MT28F800B3)

TRUTH TABLE (MT28F008B3)

FUNCTIONAL DESCRIPTION

OVERVIEW

SMART 3 TECHNOLOGY (B3)

HARDWARE-PROTECTED BOOT BLOCK

SELECTABLE BUS SIZE (MT28F800B3)

INTERNAL STATE MACHINE (ISM)

ELEVEN INDEPENDENTLY ERASABLE MEMORY BLOCKS

ISM STATUS REGISTER

COMMAND EXECUTION LOGIC (CEL)

DEEP POWER-DOWN MODE

MEMORY ARCHITECTURE

BOOT BLOCK

PARAMETER BLOCKS

MAIN MEMORY BLOCKS

OUTPUT (READ) OPERATIONS

MEMORY ARRAY

STATUS REGISTER

IDENTIFICATION REGISTER

INPUT OPERATIONS

COMMANDS

MEMORY ARRAY

COMMAND SET

ISM STATUS REGISTER

Status Register Bit Definitions

COMMAND EXECUTION

READ ARRAY

IDENTIFY DEVICE

WRITE SEQUENCE

ERASE SEQUENCE

ERASE SUSPENSION

ERROR HANDLING

WRITE/ERASE CYCLE ENDURANCE

POWER USAGE

POWER-UP

SELF-TIMED BLOCK ERASE SEQUENCE

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC READ OPERATING CONDITIONS

CAPACITANCE

READ AND STANDBY CURRENT DRAIN

AC TEST CONDITIONS

WORD-WIDE READ CYCLE

BYTE-WIDE READ CYCLE

RECOMMENDED DC WRITE/ERASE CONDITIONS

WRITE/ERASE CURRENT DRAIN

SPEED-DEPENDENT WRITE/ERASE AC TIMING CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS: WE# (CE#)-CONTROLLED WRITES

WORD/BYTE WRITE AND ERASE DURATION CHARACTERISTICS

40-PIN PLASTIC TSOP I

48-PIN PLASTIC TSOP I

44-PIN PLASTIC SOP