Datasheet MT28F640J3RG-15ET, MT28F640J3RG-12, MT28F640J3RG-12ET, MT28F640J3RG-15, MT28F640J3FS-15ET Datasheet (MICRON)

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Q-FLASHTM MEMORY

FEATURES

• x8/x16 organization

• One hundred twenty-eight 128KB erase blocks (128Mb) Sixty-four 128KB erase blocks (64Mb) Thirty-two 128KB erase blocks (32Mb)

•VCC, VCCQ, and VPEN voltages:

2.7V to 3.6V VCC operation

2.7V to 3.6V or 4.5V to 5.5V* VCCQ operation

2.7V to 3.6V, or 5V VPEN application programming

• Interface Asynchronous Page Mode Reads:

150ns/25ns read access time (128Mb) 120ns/25ns read access time (64Mb) 110ns/25ns read access time (32Mb)

• Enhanced data protection feature with VPEN = VSS

Flexible sector locking Sector erase/program lockout during power

transition

• Security OTP block feature

Permanent block locking (Contact factory for

availability)

• Industry-standard pinout

• Inputs and outputs are fully TTL-compatible

• Common Flash Interface (CFI) and Scalable Command Set

• Automatic write and erase algorithm

• 4.7µs-per-byte effective programming time using write buffer

• 128-bit protection register

64-bit unique device identifier 64-bit user-programmable OTP cells

• 100,000 ERASE cycles per block

• Automatic suspend options:

Block Erase Suspend-to-Read Block Erase Suspend-to-Program Program Suspend-to-Read

NOTE: MT28F128J3, and MT28F320J3 are preliminary status.

MT28F640J3 is production status.

OPTIONS MARKING

• Timing 150ns (128Mb) -15 120ns (64Mb) -12 110ns (32Mb) -11

• Operating Temperature Range Commercial Temperature (0ºC to +85ºC) None Extended Temperature (-40ºC to +85ºC) ET

‡

MT28F128J3‡, MT28F640J3, MT28F320J3

56-Pin TSOP Type I

•VCCQ Option*

2.7V–3.6V None

4.5V–5.5V F

• Packages 56-pin TSOP Type I RG 64-ball FBGA (1.0mm pitch) FS

MT28F640J3RG-12 ET

*Contact factory for availability of the MT28F320J3 and MT28F640J3.

‡

64-Ball FBGA

Part Number Example:

‡

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S

PRODUCTION DATA SHEET SPECIFICATIONS.

1

GENERAL DESCRIPTION

The MT28F128J3 is a nonvolatile, electrically blockerasable (Flash), programmable memory containing 134,217,728 bits organized as 16,777,218 bytes (8 bits) or 8,388,608 words (16 bits). This 128Mb device is organized as one hundred twenty-eight 128KB erase blocks.

The MT28F640J3 contains 67,108,864 bits organized as 8,388,608 bytes (8 bits) or 4,194,304 words (16 bits). This 64Mb device is organized as sixty-four 128KB erase blocks.

Similarly, the MT28F320J3 contains 33,554,432 bits organized as 4,194,304 bytes (8 bits) or 2,097,152 words (16 bits). This 32Mb device is organized as thirty-two 128KB erase blocks.

These three devices feature in-system block locking. They also have common flash interface (CFI) that permits software algorithms to be used for entire families of devices. The software is device-independent, JEDEC ID-independent with forward and backward compatibility.

Additionally, the scalable command set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant Flash memory devices. The SCS provides the fastest system/device data transfer rates and minimizes the device and system-level implementation costs.

To optimize the processor-memory interface, the device accommodates VPEN, which is switchable during block erase, program, or lock bit configuration, or hardwired to VCC, depending on the application. VPEN is treated as an input pin to enable erasing, programming, and block locking. When VPEN is lower than the VCC lockout voltage (VLKO), all program functions are disabled. Block erase suspend mode enables the user to stop block erase to read data from or program data to any other blocks. Similarly, program suspend mode enables the user to suspend programming to read data or execute code from any unsuspended blocks.

VPEN serves as an input with 2.7V, 3.3V, or 5V for application programming. VPEN in this Q-Flash family

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

can provide data protection when connected to ground. This pin also enables program or erase lockout during power transition.

Micron’s even-sectored Q-Flash devices offer individual block locking that can lock and unlock a block using the sector lock bits command sequence.

Status (STS) is a logic signal output that gives an additional indicator of the internal state machine (ISM) activity by providing a hardware signal of both status and status masking. This status indicator minimizes central processing unit (CPU) overhead and system power consumption. In the default mode, STS acts as an RY/BY# pin. When LOW, STS indicates that the ISM is performing a block erase, program, or lock bit configuration. When HIGH, STS indicates that the ISM is ready for a new command.

Three chip enable (CE) pins are used for enabling and disabling the device by activating the device’s control logic, input buffer, decoders, and sense amplifiers.

BYTE# enables selecting x8 or x16 READs/WRITEs to the device. BYTE# at logic LOW selects an 8-bit mode with address A0 selecting between the low byte and the high byte. BYTE# at logic HIGH enables 16-bit operation.

RP# is used to reset the device. When the device is disabled and RP# is at VCC, the standby mode is enabled. A reset time (tRWH) is required after RP# switches HIGH until outputs are valid. Likewise, the device has a wake time (tRS) from RP# HIGH until WRITEs to the command user interface (CUI) are recognized. When RP# is at GND, it provides write protection, resets the ISM, and clears the status register.

A variant of the MT28F320J3 also supports the new security block lock feature for additional code security. This feature provides an OTP function for locking the top two blocks, the bottom two blocks, or the entire device. (Contact factory for availability.)

2

DEVICE MARKING

Due to the size of the package, Micron’s standard part number is not printed on the top of each device. Instead, an abbreviated device mark comprised of a

Cross Reference for Abbreviated Device Marks

PRODUCT ENGINEERING QUALIFIED

PART NUMBER MARKING SAMPLE SAMPLE

MT28F320J3FS-11 FW201 FX201 FQ201 MT28F320J3FS-11 ET FW207 FX207 FQ207 MT28F640J3FS-12 FW202 FX202 FQ202 MT28F640J3FS-12 ET FW209 FX209 FQ209 MT28F128J3FS-15 FW203 FX203 FQ203 MT28F128J3FS-15 ET FW501 FX501 FQ501

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

five-digit alphanumeric code is used. The abbreviated device marks are cross referenced to Micron part numbers in Table 1.

Table 1

A22

CE1

A21

A20 A19 A18 A17 A16

V

A15 A14 A13 A12

CE0

V

PEN

RP#

A11 A10

A9 A8

V

A7 A6 A5 A4 A3 A2 A1

PIN /BALL ASSIGNMENT (Top View)

56-Pin TSOP Type I

56

1 2 3 4 5 6 7 8 9

CC

10 11 12 13 14 15 16 17 18 19 20 21

SS

22 23 24 25 26 27 28

NC

55

WE#

54

OE#

53

STS

52

DQ15

51

DQ7

50

DQ14

49

DQ6

48

V

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

SS

DQ13

DQ5

DQ12

DQ4

V

CC

Q

V

SS

DQ11

DQ3

DQ10

DQ2

V

CC

DQ9

DQ1

DQ8

DQ0

A0

BYTE#

A23

CE2

A

B

C

D

E

F

G

H

64-Ball FBGA

1 2 3 4 5 6 7 8

A1

A2

A3

A4

DQ8

BYTE#

A23

CE2

DQ1

DQ0

DNU

A6

A8

V

A9

SS

A10

A7

A11

A5

DQ9

DQ10

DQ2

A0

V

CC

A13

V

PEN

A14

CE0

A15

A12

DNU

RP#

DQ4

DQ3

DQ12

DQ11

DQ5

V

CC

Q

DQ13

V

SS

Top View

(Ball Down)

V

DNU

DQ6

V

CC

A18

A19

A20

A16

DQ15

DNU

DQ14

DQ7

SS

A22

CE1

A21

A17

STS

OE#

WE#

NC

NOTE: 1. A22 only exists on the 64Mb and 128Mb devices. On the 32Mb, this pin/ball is a no connect (NC).

2. A23 only exists on the 128Mb device. On the 32Mb and 64Mb, this pin/ball is a no connect (NC).

3. The # symbol indicates signal is active LOW.

3

A0–A23

I/O

Control

Logic

FUNCTIONAL BLOCK DIAGRAM

(128Mb)

Addr.

Buffer/

Latch

128KB Memory Block (0) 128KB Memory Block (1)

X - Decoder/Block Erase Control

128KB Memory Block (2)

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Input

Buffer

CE0 CE1 CE2

OE#

WE#

RP#

V

STS

V

Power

(Current)

Control

Addr.

Counter

Write Buffer

DQ0–DQ15

CE Logic

CC

PEN

Command

Execution

Logic

State

Machine

Switch/

Pump

PP

V

Status

Register

Identification

Register

Decoder

128KB Memory Block (125) 128KB Memory Block (126) 128KB Memory Block (127)

Y -

Query

Y - Select Gates

Sense Amplifiers

Write/Erase-Bit

Compare and Verify

Output

Buffer

FUNCTIONAL BLOCK DIAGRAM

(64Mb)

Input

Buffer

I/O

Control

Logic

128KB Memory Block (0) 128KB Memory Block (1)

X - Decoder/Block Erase Control

128KB Memory Block (2)

A0–A22

Addr.

Buffer/

Latch

Power

(Current)

Control

Addr.

Counter

Write Buffer

DQ0–DQ15 CE0 CE1

CE2

OE#

WE#

RP# V

CC

STS

V

PEN

CE Logic

Command

Execution

Logic

State

Machine

Switch/

Pump

PP

V

Status

Register

Identification

4

Decoder

Register

Y -

Query

128KB Memory Block (61) 128KB Memory Block (62) 128KB Memory Block (63)

Y - Select Gates

Sense Amplifiers

Write/Erase-Bit

Compare and Verify

Output

Buffer

A0–A21

I/O

Control

Logic

FUNCTIONAL BLOCK DIAGRAM

(32Mb)

Addr.

Buffer/

Latch

128KB Memory Block (0) 128KB Memory Block (1)

X - Decoder/Block Erase Control

128KB Memory Block (2)

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Input

Buffer

CE0 CE1 CE2

OE#

WE#

RP#

V

STS

V

Power

(Current)

Control

Addr.

Counter

Write Buffer

DQ0–DQ15

Y -

Query

128KB Memory Block (29) 128KB Memory Block (30)

128KB Memory Block (31)

Y - Select Gates

Sense Amplifiers

Write/Erase-Bit

Compare and Verify

Output

Buffer

CE Logic

CC

PEN

Command

Execution

Logic

State

Machine

Switch/

Pump

PP

V

Status

Register

Identification

Register

Decoder

5

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

PIN/BALL DESCRIPTIONS

56-PIN TSOP 64-BALL FBGA

NUMBERS NUMBERS SYMBOL TYPE DESCRIPTION

55 G8 WE# Input Write Enable: Determines if a given cycle is a WRITE

cycle. If WE# is LOW, the cycle is either a WRITE to the command execution logic (CEL) or to the memory array. Addresses and data are latched on the rising edge of the WE# pulse.

14, 2, 29 B4, B8, H1 CE0, CE1, Input Chip Enable: Three CE pins enable the use of multiple

CE2 Flash devices in the system without requiring additional

logic. The device can be configured to use a single CE signal by tying CE1 and CE2 to ground and then using CE0 as CE. Device selection occurs with the first edge of CE0, CE1, or CE2 (CEx) that enables the device. Device deselection occurs with the first edge of CEx that disables the device (see Table 2).

16 D4 RP# Input Reset/Power-Down: When LOW, RP# clears the status

register, sets the ISM to the array read mode, and places the device in deep power-down mode. All inputs, including CEx, are “Don’t Care,” and all outputs are High-Z. RP# must be held at VIH during all other modes of operation.

54 F8 OE# Input Output Enables: Enables data ouput buffers when LOW.

When OE# is HIGH, the output buffers are disabled.

32, 28, 27, G2, A1, B1, C1, A0–A21/ Input Address inputs during READ and WRITE operations. A0 is 26, 25, 24, 23, D1, D2, A2, C2, (A22) only used in x8 mode. A22 (pin 1, ball A8) is only 22, 20, 19, 18, A3, B3, C3, D3, (A23) available on the 64Mb and 128Mb devices. A23 (pin 30, 17, 13, 12, 11, C4, A5, B5, C5, ball G1) is only available on the 128Mb device.

10, 8, 7, 6, 5, 4, D7, D8, A7, B7,

3, 1, 30 C7, C8, A8, G1

31 F1 BYTE# Input BYTE# LOW places the device in the x8 mode. BYTE#

HIGH places the device in the x16 mode and turns off the A0 input buffer. Address A1 becomes the lowest order address in x16 mode.

15 A4 V

33, 35, 38, 40, F2, E2, G3, E4, DQ0– Input/ Data I/O: Data output pins during any READ operation 44, 46, 49, 51, E5, G5, G6, H7, DQ15 Output or data input pins during a WRITE. DQ8–DQ15 are not 34, 36, 39, 41, E1, E3, F3, F4, used in byte mode.

45, 47, 50, 52 F5, H5, G7, E7

53 E8 STS Output Status: Indicates the status of the ISM. When configured

PEN

Input Necessary voltage for erasing blocks, programming data,

or configuring lock bits. Typically, V VCC. When V

PEN

≤ V

PENLK

, this pin enables hardware write

PEN

is connected to

protect.

in level mode, default mode it acts as an RY/BY# pin. When configured in its pulse mode, it can pulse to indicate program and/or erase completion. Tie STS to VCCQ through a pull-up resistor.

(continued on next page)

6

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

PIN/BALL DESCRIPTIONS (continued)

56-PIN TSOP 64-BALL FBGA

NUMBERS NUMBERS SYMBOL TYPE DESCRIPTION

43 G4 VCCQ Supply VCCQ controls the output voltages. To obtain output

voltage compatible with system data bus voltages, connect VCCQ to the system supply voltage.

9, 37 H3, A6 VCC Supply Power Supply: 2.7V to 3.6V.

21, 42, 48 B2, H4, H6 VSS Supply Ground.

56 H8 NC – No Connect: These may be driven or left unconnected.

Pin 1 and ball A8 are NCs on the 32Mb device. Pin 30 and ball G1 are NCs on the 32Mb and 64Mb devices.

– B6, C6, D5, D6, DNU – Do Not Use: Must float to minimize noise.

E6, F6, F7, H2

7

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

MEMORY ARCHITECTURE

The MT28F128J3, MT28F640J3, and MT28F320J3 memory array architecture is divided into one hundred twenty-eight, sixty-four, or thirty-two 128KB blocks, respectively (see Figure 1). The internal architecture allows greater flexibility when updating data because individual code portions can be updated independently of the rest of the code.

Figure 1

Memory Map

FFFFFFh FE0000h

7FFFFFh 7E0000h

3FFFFFh 3E0000h

03FFFFh 020000h 01FFFFh 000000h

128KB Block 127

128KB Block 63

128KB Block 31

128KB Block 1

128KB Block 0

A0–A23: 128Mb A0–A22: 64Mb A0–A21: 32Mb

Byte-Wide (x8) Mode Word-Wide (x16) Mode

7FFFFFh 7F0000h

3FFFFFh 3F0000h

1FFFFFh 1F0000h

01FFFFh 010000h 00FFFFh 000000h

64K-Word Block 127

64K-Word Block 63

64K-Word Block 31

64K-Word Block 1

64K-Word Block 0

A1–A23: 128Mb A1–A22: 64Mb A1–A21: 32Mb

64Mb

b

32M

128Mb

Table 2

Chip Enable Truth Table

CE2 CE1 CE0 DEVICE

VIL VIL VIL Enabled

VIL VIL VIH Disabled

VIL VIH VIL Disabled

VIL VIH VIH Disabled

VIH VIL VIL Enabled

VIH VIL VIH Enabled

VIH VIH VIL Enabled

VIH VIH VIH Disabled

NOTE: For single-chip applications, CE2 and CE1 can be

connected to GND.

high-speed page buffer. A0–A2 select data in the page buffer. Asynchronous page mode, with a page size of four words or eight bytes, is supported with no additional commands required.

OUTPUT DISABLE

The device outputs are disabled with OE# at a logic HIGH level (VIH). Output pins DQ0–DQ15 are placed in High-Z.

BUS OPERATION

All bus cycles to and from the Flash memory must conform to the standard microprocessor bus cycles. The local CPU reads and writes Flash memory insystem.

READ

Information can be read from any block, query, identifier codes, or status register, regardless of the VPEN voltage. The device automatically resets to read array mode upon initial device power-up or after exit from reset/power-down mode. To access other read mode commands (READ ARRAY, READ QUERY, READ IDENTIFIER CODES, or READ STATUS REGISTER), these commands should be issued to the CUI. Six control pins dictate the data flow in and out of the device: CE0, CE1, CE2, OE#, WE#, and RP#. In system designs using multiple Q-Flash devices, CE0, CE1, and CE2 (CEx) select the memory device (see Table 2). To drive data out of the device and onto the I/O bus, OE# must be active and WE# must be inactive (VIH).

When reading information in read array mode, the device defaults to asynchronous page mode, thus providing a high data transfer rate for memory subsystems. In this state, data is internally read and stored in a

STANDBY

CE0, CE1, and CE2 can disable the device (see Table 2) and place it in standby mode, which substantially reduces device power consumption. DQ0–DQ15 outputs are placed in High-Z, independent of OE#. If deselected during block erase, program, or lock bit configuration, the ISM continues functioning and consuming active power until the operation completes.

RESET/POWER-DOWN

RP# puts the device into the reset/power-down mode when set to VIL.

During read, RP# LOW deselects the memory, places output drivers in High-Z, and turns off internal circuitry. RP# must be held LOW for a minimum of tPLPH.

t

RWH is required after return from reset mode until initial memory access outputs are valid. After this wakeup interval, normal operation is restored. The command execution logic (CEL) is reset to the read array mode and the status register is set to 80h.

During block erase, program, or lock bit configuration, RP# LOW aborts the operation. In default mode, STS transitions LOW and remains LOW for a maximum time of tPLPH + tPHRH, until the RESET operation is complete. Any memory content changes are no longer

8

128Mb, 64Mb, 32Mb

Reserved for Future Implementation

Manufacturer Code

Device Code

010000h 00FFFFh

000004h

000003h

000002h

000001h

000000h

Reserved for Future Implementation

Block 63

Block 0

3FFFFFh

3F0003h 3F0002h

3F0000h 3EFFFFh

1EFFFFh

1F0003h 1F0002h

1F0000h

01FFFFh

010003h 010002h

32Mb

64Mb

128Mb

Block 63 Lock Configuration

Block 0 Lock Configuration

Reserved for Future Implementation

(Blocks 32 through 62)

Reserved for Future Implementation

7FFFFFh

7F0003h 7F0002h

7F0000h 7EFFFFh

Block 127 Lock Configuration

Reserved for Future Implementation

Block 31

Reserved for Future Implementation

(Blocks 2 through 30)

Block 1

Reserved for Future Implementation

Block 1 Lock Configuration

Block 127

Block 31 Lock Configuration

(Blocks 64 through 126)

Q-FLASH MEMORY

valid; the data may be partially corrupted after a program or partially changed after an erase or lock bit configuration. After RP# goes to logic HIGH (VIH), and

Device Identifier Code Memory Map

Figure 2

after tRS, another command can be written.

It is important to assert RP# during system reset. After coming out of reset, the system expects to read from the Flash memory. During block erase, program, or lock bit configuration mode, automated Flash memories provide status information when accessed. When a CPU reset occurs with no Flash memory reset, proper initialization may not occur because the Flash memory may be providing status information instead of array data. Micron Flash memories allow proper initialization following a system reset through the use of the RP# input. RP# should be controlled by the same RESET# signal that resets the system CPU.

READ QUERY

The READ QUERY operation produces block status information, CFI ID string, system interface information, device geometry information, and extended query information.

READ IDENTIFIER CODES

The READ IDENTIFIER CODES operation produces the manufacturer code, device code, and the block lock configuration codes for each block (see Figure 2). The block lock configuration codes identify locked and unlocked blocks.

WRITE

Writing commands to the CEL allows reading of device data, query, identifier codes, and reading and clearing of the status register. In addition, when VPEN = VPENH, block erasure, program, and lock bit configuration can also be performed.

The BLOCK ERASE command requires suitable command data and an address within the block. The BYTE/ WORD PROGRAM command requires the command and address of the location to be written to. The CLEAR BLOCK LOCK BITS command requires the command and any address within the device. SET BLOCK LOCK BITS command requires the command and the block to be locked. The CEL does not occupy an addressable memory location. It is written to when the device is enabled and WE# is LOW. The address and data needed to execute a command are latched on the rising edge of WE# or the first edge of CEx that disables the device (see Table 2). Standard microprocessor write timings are used.

NOTE: When obtaining these identifier codes, A0 is not used

in either x8 or x16 modes. Data is always given on the LOW byte in x16 mode (upper byte contains 00h).

9

Table 3

Bus Operations

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

CE0, CE1, STS DEFAULT

MODE RP# CE2

1

OE#2WE#2ADDRESS VPEN DQ

Read Array VIH Enabled VIL VIH XXDOUT High-Z

3

MODE NOTES

4

5, 6, 7

Output Disable VIH Enabled VIH VIH X X High-Z X

Standby VIH Disabled X X X X High-Z X

Reset/Power-Down VIL X X X X X High-Z High-Z

4

Mode

Read Identifier Codes VIH Enabled VIL VIH See X Note 8 High-Z

4

Figure 2

Read Query VIH Enabled VIL VIH See X Note 9 High-Z

4

Table 7

Read Status (ISM off) VIH Enabled VIL VIH XXDOUT

Read Status (ISM on) VIH Enabled VIL VIH XX

DQ7 DOUT

DQ15–DQ8 High-Z

DQ6–DQ0 High-Z

Write VIH Enabled VIH VIL XVPENH DIN X 7, 10, 11

NOTE: 1. See Table 2 for valid CE configurations.

2. OE# and WE# should never be enabled simultaneously.

3. DQ refers to DQ0–DQ7 if BYTE# is LOW and DQ0–DQ15 if BYTE# is HIGH.

4. High-Z is VOH with an external pull-up resistor.

5. Refer to DC Characteristics. When VPEN ≤ VPENLK, memory contents can be read, but not altered.

6. X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN. See DC Characteristics for VPENLK and VPENH voltages.

7. In default mode, STS is VOL when the ISM is executing internal block erase, program, or lock bit configuration algorithms. It is VOH when the ISM is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or reset/power-down mode.

8. See Read Identifier Codes section for read identifier code data.

9. See Read Query Mode Command section for read query data.

10. Command writes involving block erase, program, or lock bit configuration are reliably executed when VPEN = VPENH and VCC is within specification.

11. Refer to Table 4 for valid DIN during a WRITE operation.

10

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

COMMAND DEFINITIONS

When the VPEN voltage is less than VPPLK, only READ operations from the status register, query, identifier codes, or blocks are enabled. Placing VPENH on VPEN enables BLOCK ERASE, PROGRAM, and LOCK BIT CON-

Table 4

Micron Q-Flash Memory Command Set Definitions

COMMAND SCALABLE BUS

OR BASIC CYCLES FIRST BUS CYCLE SECOND BUS CYCLE

COMMAND REQ’D

READ ARRAY SCS/BCS 1 WRITE X FFh

READ IDENTIFIER SCS/BCS  2 WRITE X 90h READ IA ID 7 CODES

READ QUERY SCS  2 WRITE X 98h READ QA QD

READ STATUS SCS/BCS 2 WRITE X 70h READ X SRD 8 REGISTER

CLEAR STATUS SCS/BCS 1 WRITE X 50h REGISTER

WRITE TO BUFFER SCS/BCS > 2 WRITE BA E8h WRITE BA N 9, 10, 11

WORD/BYTE SCS/BCS 2 WRITE X 40h WRITE PA PD 12, 13 PROGRAM or

BLOCK ERASE SCS/BCS 2 WRITE BA 20h WRITE BA D0h 11, 12

BLOCK ERASE, SCS/BCS 1 WRITE X B0h 12, 14 PROGRAM SUSPEND

BLOCK ERASE, SCS/BCS 1 WRITE X D0h 12 PROGRAM RESUME

CONFIGURATION SCS 2 WRITE X B8h WRITE X C C

SET BLOCK LOCK BITS S CS 2 WRITE X 60h WRITE BA 01h

CLEAR BLOCK SCS 2 WRITE X 60h WRITE X D0h 15 LOCK BITS

PROTECTION 2 WRITE X C0h WRITE PA PD PROGRAM

SET

2

OPER3ADDR4DATA

FIGURATION operations. Device operations are selected by writing specific commands into the CEL, as seen in Table 4.

1

10h

5, 6

OPER3ADDR4DATA

5, 6

NOTES*

*Notes appear on the next page.

11

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

NOTE: 1. Commands other than those shown in Table 4 are reserved for future device implementations and should not be used.

2. The SCS is also referred to as the extended command set.

3. Bus operations are defined in Table 3.

4. X = Any valid address within the device BA = Address within the block

IA = Identifier code address; see Figure 2 and Table 15

QA = Query data base address

PA = Address of memory location to be programmed

5. ID = Data read from identifier codes

QD = Data read from query data base

SRD = Data read from status register; see Table 16 for a description of the status register bits

PD = Data to be programmed at location PA; data is latched on the rising edge of WE#

CC = Configuration code

6. The upper byte of the data bus (DQ8–DQ15) during command WRITEs is a “Don’t Care” in x16 operation.

7. Following the READ IDENTIFIER CODES command, READ operations access manufacturer, device, and block lock codes.

See Block Status Register section for read identifier code data.

8. If the ISM is running, only DQ7 is valid; DQ15–DQ8 and DQ6–DQ0 float, which places them in High-Z.

9. After the WRITE-to-BUFFER command is issued, check the XSR to make sure a buffer is available for writing.

10. The number of bytes/words to be written to the write buffer = n + 1, where n = byte/word count argument. Count ranges on this device for byte mode are n = 00h to n = 1Fh and for word mode, n = 0000h to n = 000Fh. The third and consecutive bus cycles, as determined by n, are for writing data into the write buffer. The CONFIRM command (D0h) is expected after exactly n + 1 WRITE cycles; any other command at that point in the sequence aborts the WRITE-toBUFFER operation. Please see Figure 4, WRITE-to-BUFFER Flowchart, for additional information.

11. The WRITE-to-BUFFER or ERASE operation does not begin until a CONFIRM command (D0h) is issued.

12. Attempts to issue a block erase or program to a locked block while RP# = VIH will fail.

13. Either 40h or 10h is recognized by the ISM as the byte/word program setup.

14. Program suspend can be issued after either the WRITE-to-BUFFER or WORD/BYTE PROGRAM operation is initiated.

15. The CLEAR BLOCK LOCK BITS operation simultaneously clears all block lock bits.

12

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Q-FLASH MEMORY

READ ARRAY COMMAND

The device defaults to read array mode upon initial device power-up and after exiting reset/power-down mode. The read configuration register defaults to asynchronous read page mode. Until another command is written, the READ ARRAY command also causes the device to enter read array mode. When the ISM has started a block erase, program, or lock bit configuration, the device does not recognize the READ ARRAY command until the ISM completes its operation, unless the ISM is suspended via an ERASE or PROGRAM SUSPEND command. The READ ARRAY command functions independently of the VPEN voltage.

READ QUERY MODE COMMAND

This section is related to the definition of the data structure or “data base” returned by the CFI QUERY command. System software should retain this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. When this information has been obtained, the software knows which command sets to use to enable Flash writes or block erases, and otherwise control the Flash component.

QUERY STRUCTURE OUTPUT

The query “data base” enables system software to obtain information about controlling the Flash component. The device’s CFI-compliant interface allows the host system to access query data. Query data are always located on the lowest-order data outputs (DQ0– DQ7) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the query table device starting address is a 10h, which is a word address for x16 devices.

For a x16 organization, the first two bytes of the query structure, “Q” and “R” in ASCII, appear on the low byte at word addresses 10h and 11h. This CFIcompliant device outputs 00h data on upper bytes, thus making the device output ASCII “Q” on the LOW byte (DQ7–DQ0) and 00h on the HIGH byte (DQ15– DQ8). At query addresses containing two or more bytes of information, the least significant data byte is located at the lower address, and the most significant data byte is located at the higher address. This is summarized in Table 5. A more detailed example is provided in Table 6.

Table 5

Summary of Query Structure Output as a Function of Device and Mode

QUERY DATA WITH

MAXIMUM DEVICE BUS QUERY DATA WITH BYTE

DEVICE QUERY START LOCATION IN WIDTH ADDRESSING ADDRESSING

TYPE/ MAXIMUM DEVICE BUS HEX HEX ASCII HEX HEX ASCII MODE WIDTH ADDRESSES OFFSET CODE VALUE OFFSET CODE VALUE

x16 device 10h 10 0051 Q 20 51 Q x16 mode 11 0052 R 21 00 Null

12 0059 Y 22 52 R

x16 device 20 51 Q x8 mode N/A

NOTE: 1. The system must drive the lowest-order addresses to access all the device’s array data when the device is configured in

x8 mode. Therefore, word addressing where these lower addresses are not toggled by the system is “Not Applicable” for x8-configured devices.

1

N/A

1

21 51 Q 22 52 R

13

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Q-FLASH MEMORY

QUERY STRUCTURE OVERVIEW

The QUERY command makes the Flash component display the CFI query structure or data base. The structure subsections and address locations are outlined in Table 7.

Table 6

Example of Query Structure Output of a x16- and x8-Capable Device

WORD ADDRESSING BYTE ADDRESSING

OFFSET HEX CODE VALUE OFFSET HEX CODE VALUE

A16–A1 DQ15–DQ0 A7–A0 DQ7–DQ0

0010h 0051 Q 20h 51 Q

0011h 0052 R 21h 51 Q

0012h 0059 Y 22h 52 R

0013h P_ID LO PrVendor 23h 52 R

0014h P_ID HI ID # 24h 59 Y

0015h P LO PrVendor 25h 59 Y

0016h P HI TblAdr 26h P_ID LO PrVendor

0017h A_ID LO AltVendor 27h P_ID LO PrVendor

0018h A_ID HI ID # 28h P_ID HI ID #

... ... ... ... ... ...

Table 7

Query Structure

OFFSET SUBSECTION NAME DESCRIPTION

00h Manufacturer compatibility code

01h Device code

(BA+2)h

04–0Fh Reserved Reserved for vendor-specific information

10h CFI Query Identification String Reserved for vendor-specific information

1Bh System Interface Information Command set ID and vendor data offset

27h Device Geometry Definition Flash device layout

3

P

NOTE: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function

2

of device bus width and mode.

2. BA = Block address beginning location (i.e., 020000h is block two’s beginning location when the block size is 64K-word).

3. Offset 15 defines “P,” which points to the Primary Extended Query Table.

Block Status Register Block-specific information

Primary Extended Query Table Vendor-defined additional information specific to the

primary vendor algorithm

14

1

CFI QUERY IDENTIFICATION STRING

The CFI query identification string verifies whether the component supports the CFI specification. Addi-

Table 8

Block Status Register

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

tionally, it indicates the specification version and supported vendor-specified command set(s).

OFFSET LENGTH DESCRIPTION ADDRESS

(BA+2)h

NOTE: 1. BA = The beginning location of a block address (i.e., 010000h is block one’s (64K-word) beginning location in word

1

mode).

1 Block Lock Status Register (BA+2)h 00 or 01

BSR0 Block Lock Status 0 = Unlocked (BA+2)h (bit 0) 0 or 1 1 = Locked

BSR1–7 Reserved for Future Use (BA+2)h (bit 2–7) 0

1

VALUE

Table 9

CFI Identification

OFFSET LENGTH DESCRIPTION ADDRESS HEX VALUE

CODE

10h 3 Query-unique ASCII string “QRY” 10h 51 Q

11h 52 R 12h 59 Y

13h 2 Primary vendor command set and control interface ID 13h 01

code. 16-bit ID code for vendor-specified algorithms 14h 00

15h 2 Extended query table primary algorithm address 15h 31

16h 00

17h 2 Alternate vendor command set and control interface ID 17h 00

code; 0000h means no second vendor-specified 18h 00 algorithm exists

19h 2 Secondary algorithm extended query table address; 19h 00

0000h means none exists 1Ah 00

15

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Q-FLASH MEMORY

SYSTEM INTERFACE INFORMATION

Table 10 provides useful information about optimizing system interface software.

Table 10

System Interface Information

OFFSET LENGTH DESCRIPTION ADDRESS HEX VALUE

CODE

1Bh 1 V

1Ch 1 VCC logic supply maximum program/erase voltage

1Dh 1 VPP [programming] supply minimum program/erase

1Eh 1 VPP [programming] supply maximum program/erase

1Fh 1 “n” such that typical single word program 1Fh 07 128µs

20h 1 “n” such that typical max. buffer write timeout = 2n µs 20h 07 128µs

21h 1 “n” such that typical block erase timeout = 2n ms 21h 0A 1s

22h 1 “n” such that typical full chip erase timeout = 2n ms 22h 00 N/A

23h 1 “n” such that maximum word program timeout = 2

24h 1 “n” such that maximum buffer write timeout = 2

25h 1 “n” such that maximum block erase timeout = 2

26h 1 “n” such that maximum chip erase timeout = 2

CC logic supply minimum program/erase voltage

Bits 0–3 BCD 100mV 1Bh 27 2.7V Bits 4–7 BCD volts

Bits 0–3 BCD 100mV 1Ch 36 3.6V Bits 4–7 BCD volts

voltage Bits 0–3 BCD 100mV 1Dh 00 0.0V Bits 4–7 Hex volts

voltage Bits 0–3 BCD 100mV 1Eh 00 0.0V Bits 4–7 Hex volts

timeout = 2n µs

n

23h 04 2ms

times typical

n

24h 04 2ms

times typical

n

25h 04 16s

times typical

n

26h 00 N/A

times typical

16

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Q-FLASH MEMORY

DEVICE GEOMETRY DEFINITION

Tables 11a and 11b provide important details about the device geometry.

Table 11a

Device Geometry Definitions

OFFSET LENGTH DESCRIPTION CODE

(see table below)

27h 1 “n” such that device size = 2

28h 2 Flash device interface: x8 async, x16 async, x8/x16 async; 28h 02 x8/x16

28:00 29:00, 28:01 29:00, 28:02 29:00 29h 00

2Ah 2 “n” such that maximum number of bytes in write 2Ah 05 32

buffer = 2

2Ch 1 Number of erase block regions within device: 2Ch 01 1

1. x = 0 means no erase blocking; the device erases in “bulk”

2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks

3. Symmetrically blocked partitions have one blocking region

4. Partition size = (total blocks) x (individual block size)

2Dh 4 Erase Block Region 1 Information 2Dh

Bits 0–15 = y; y + 1 = number of identical-size erase blocks 2Eh Bits 16–31 = z; region erase block(s) size are z x 256 bytes 2Fh

n

in number of bytes 27h

2Bh 00

30h

Table 11b

Device Geometry Definition Codes

ADDRESS 32Mb 64Mb 128Mb

27h 16 17 18 28h 02 02 02

29h 00 00 00 2Ah 05 05 05 2Bh 00 00 00 2Ch 01 01 01 2Dh 1F 3F 7F

2Eh 00 00 00

2Fh 00 00 00

30h 02 02 02

17

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

PRIMARY VENDOR-SPECIFIC EXTENDED QUERY TABLE

Table 12 includes information about optional Flash features and commands and other similar information.

Table 12

Primary Vendor-Specific Extended Query

OFFSET1DESCRIPTION ADDRESS HEX VALUE

P = 31h (OPTIONAL FLASH FEATURES AND COMMANDS) CODE

(P+0)h Primary extended query table 31h 50 P (P+1)h Unique ASCII string, PRI 32h 52 R (P+2)h 33h 49 I

(P+3)h Major version number, ASCII 34h 31 1

(P+4)h Minor version number, ASCII 35h 31 1

(P+5)h Optional feature and command support (1 = yes, 0 = no) bits 9–31 36h 0A (P+6)h are reserved; undefined bits are “0.” If bit 31 is “1,” then another 37h 00 (P+7)h 31-bit field of optional features follows at the end of the bit 30 38h 00 (P+8)h field. 39h 0

Bit 0 Chip erase supported = no = 0 Bit 1 Suspend erase supported = yes = 1 Bit 2 Suspend program supported = yes = 1 Bit 3 Legacy lock/unlock supported = yes = 1 Bit 4 Queued erase supported = no = 0 Bit 5 Instant Individual block locking supported = no = 0 Bit 6 Protection bits supported = yes = 1 Bit 7 Page mode read supported = yes = 1 Bit 8 Synchronous read supported = no = 0

(P+9)h Supported functions after suspend: read array, status, query 3Ah 01

Other supported operations: Bits 1–7 Reserved; undefined bits are “0” Bit 0 Program supported after erase suspend = yes = 1

(P+A)h Block status register mask 3Bh 01 (P+B)h Bits 2–15 Reserved; undefined bits are “0” 3Ch 00

Bit 0 Block lock bit status register active = yes = 1 Bit 1 Block lock down bit status active = no = 0

(P+C)h VCC logic supply highest-performance program/erase voltage

Bits 0–3 BCD value in 100mV 3Dh 33 3.3V Bits 4–7 BCD value in volts

(P+D)h VPP optimum program/erase supply voltage

Bits 0–3 BCD value in 100mV 3Eh 00 0.0V Bits 4–7 Hex value in volts

1

NOTE: 1. Future devices may not support the described “Legacy Lock/Unlock” function. On these devices, bit 3 would have a

value of “0.”

18

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Table 13

Protection Register Information

OFFSET1DESCRIPTION ADDRESS HEX VALUE

P = 31h (OPTIONAL FLASH FEATURES AND COMMANDS) CODE

(P+E)h Number of protection register fields in JEDEC ID space. “00h” 3Fh 01 01

indicates that 256 protection bytes are available.

(P+F)h Protection Field 1: Protection Description 40h 00 00h (P+10)h This field describes user-available, one-time programmable (OTP) (P+11)h protection register bytes. Some are preprogrammed with device(P+12)h unique serial numbers; others are user-programmable. Bits 0–15

point to the protection register lock byte, the section’s first byte. The following bytes are factory-preprogrammed and userprogrammable. Bits 0–7 Lock/bytes JEDEC-plane physical low address Bits 8–15 Lock/bytes JEDEC-plane physical high address Bits 16–23 “n” such that 2 Bits 24–31 “n” such that 2

n

= factory preprogrammed bytes

n

= user-programmable bytes

Table 14

Burst Read Information

OFFSET1DESCRIPTION ADDRESS HEX VALUE

P = 31h (OPTIONAL FLASH FEATURES AND COMMANDS) CODE

(P+13)h Page Mode Read Capability 44h 03 8 byte

Bits 0–7 = “n” such that 2 read page bytes. See offset 28h for device word width to determine page mode data output width. 00h indicates no read page buffer.

(P+14)h Number of synchronous mode read configuration fields 45h 00

that follow. 00h indicates no burst capability.

(P+15)h Reserved for future use. 46h

NOTE: 1. The variable “P” is a pointer which is defined at CFI offset 15h.

n

Hex value represents the number of

19

READ IDENTIFIER CODES COMMAND

Writing the READ IDENTIFIER CODES command initiates the IDENTIFIER CODE operation. Following the writing of the command, READ cycles from addresses shown in Figure 2 retrieve the manufacturer, device, and block lock configuration codes (see Table 15 for identifier code values). Page mode READs are not supported in this read mode. To terminate the operation, write another valid command. The READ IDENTIFIER CODES command functions independently of the V

PEN voltage. This command is valid only

when the ISM is off or the device is suspended. See Table 15 for read identifier codes.

READ STATUS REGISTER COMMAND

The status register may be read at any time by writing the READ STATUS REGISTER command to determine the successful completion of programming, block

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

erasure, or lock bit configuration. After writing this command, all subsequent READ operations output data from the status register until another valid command is written. Page mode READs are not supported in this read mode. The status register contents are latched on the falling edge of OE# or the first edge of CEx that enables the device (see Table 2). To update the status register latch, OE# must toggle to VIH or the device must be disabled before further READs. The READ STATUS REGISTER command functions independently of the VPEN voltage. During a program, block erase, set block lock bits, or clear block lock bits command sequence, only SR7 is valid until the ISM completes or suspends the operation. Device I/O pins DQ0–DQ6 and DQ8– DQ15 are placed in High-Z. When the operation completes or suspends (check status register bit 7), all contents of the status register are valid during a READ.

Table 15

Identifier Codes

CODE ADDRESS

Manufacturer Compatibility Code 00000h (00) 89

Device Code

• 32Mb 00001h (00) 16

• 64Mb 00001h (00) 17

• 128Mb 00001h (00) 18

Block Lock Configuration X0002h

• Block is Unlocked DQ0 = 0

• Block is Locked DQ0 = 1

• Reserved for Future Use DQ1–DQ7

NOTE: 1. A0 is not used in either x8 or x16 modes when obtaining the identifier

codes. The lowest-order address line is A1. Data is always presented on the low byte in x16 mode (upper byte contains 00h).

2. X selects the specific block’s lock configuration code. See Figure 2 for the device identifier code memory map.

1

2

DATA

20

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Table 16

Status Register Definitions

ISMS ESS ECLBS PSLBS VPENS PSS DPS R

76543210

HIGH-Z WHEN STATUS REGISTER BITS NOTES BUSY?

No SR7 = WRITE STATE MACHINE STATUS (ISMS) Check STS or SR7 to determine block

1 = Ready erase, program, or lock bit 0 = Busy configuration completion. SR6–SR0 are

not driven while SR7 = 0.

Yes SR6 = ERASE SUSPEND STATUS (ESS)

1 = Block Erase Suspended 0 = Block Erase in Progress/Completed

Yes SR5 = ERASE AND CLEAR LOCK BITS STATUS (ECLBS) If both SR5 and SR4 are “1s” after a

1 = Error in Block Erasure or Clear Lock Bits block erase or lock bit configuration 0 = Successful Block Erase or Clear Lock Bits attempt, an improper command

sequence was entered.

Yes SR4 = PROGRAM AND SET LOCK BIT STATUS (PSLBS)

1 = Error in Programming or Setting Block Lock Bits 0 = Successful Program or Set Block Lock Bits

Yes SR3 = PROGRAMMING VOLTAGE STATUS (VPENS) SR3 does not provide a continuous

1 = Low Programming Voltage Detected, programming voltage level indication.

Operation Aborted The ISM interrogates and indicates the

0 = Programming Voltage OK programming voltage level only after

block erase, program, set block lock bits, or clear block lock bits command sequences.

Yes SR2 = PROGRAM SUSPEND STATUS (PSS)

1 = Program Suspended 0 = Program in Progress/Completed

Yes SR1 = DEVICE PROTECT STATUS (DPS) SR1 does not provide a continuous

1 = Block Lock Bit Detected, Operation Aborted indication of block lock bit values. The 0 = Unlock ISM interrogates the block lock bits

only after block erase, program, or lock bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock bit is set. Read the block lock configuration codes using the READ IDENTIFIER CODES command to determine block lock bit status. SR0 is reserved for future use and should be masked when polling the status register.

Yes SR0 = RESERVED FOR FUTURE ENHANCEMENTS

21

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Table 17

Extended Status Register Definitions (XSR)

WBS RESERVED

7 6–0

HIGH-Z WHEN STATUS REGISTER BITS NOTES BUSY?

No XSR7 = WRITE BUFFER STATUS (WBS) After a BUFFER WRITE command,

1 = Write Buffer Available XSR7 = 1 indicates that a write buffer is 0 = Write Buffer Not Available available.

Yes XSR6–XSR0 = RESERVED FOR FUTURE SR6–SR0 are reserved for future use

ENHANCEMENTS and should be masked when polling

the status register.

CLEAR STATUS REGISTER COMMAND

The ISM sets the status register bits SR5, SR4, SR3, and SR1 to “1s.” These bits, which indicate various failure conditions, can only be reset by the CLEAR STATUS REGISTER command. Allowing system software to reset these bits can perform several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence). To determine if an error occurred during the sequence, the status register may be polled. To clear the status register, the CLEAR STATUS REGISTER command (50h) is written. The CLEAR STATUS REGISTER command functions independently of the applied VPEN voltage and is only valid when the ISM is off or the device is suspended.

BLOCK ERASE COMMAND

The BLOCK ERASE command is a two-cycle command that erases one block. First, a block erase setup is written, followed by a block erase confirm. This command sequence requires an appropriate address within the block to be erased. The ISM handles all block preconditioning, erase, and verify. Time tWB after the twocycle block erase sequence is written, the device automatically outputs status register data when read. The CPU can detect block erase completion by analyzing the output of the STS pin or status register bit SR7. Toggle OE# or CEx to update the status register. Upon block erase completion, status register bit SR5 should be checked to detect any block erase error. When an error is detected, the status register should be cleared before system software attempts corrective actions. The CEL remains in read status register mode until a new command is issued. This two-step setup command sequence ensures that block contents are not accidentally erased. An invalid block erase command sequence

results in status register bits SR4 and SR5 being set to “1.” Also, reliable block erasure can only occur when VCC is valid and VPEN = VPENH. Note that SR3 and SR5 are set to “1” if block erase is attempted while VPEN ≤ VPENLK. Successful block erase requires that the corresponding block lock bit be cleared. Similarly, SR1 and SR5 are set to “1” if block erase is attempted when the corresponding block lock bit is set.

BLOCK ERASE SUSPEND COMMAND

The BLOCK ERASE SUSPEND command allows block erase interruption in order to read or program data in another block of memory. Writing the BLOCK ERASE SUSPEND command immediately after starting the block erase process requests that the ISM suspend the block erase sequence at an appropriate point in the algorithm. When reading after the BLOCK ERASE SUSPEND command is written, the device outputs status register data. Polling status register bit SR7, followed by SR6, shows when the BLOCK ERASE operation has been suspended. In the default mode, STS also transitions to VOH. tLES defines the block erase suspend latency. At this point, a READ ARRAY command can be written to read data from blocks other than that which is suspended. During erase suspend to program data in other blocks, a program command sequence can also be issued. During a PROGRAM operation with block erase suspended, status register bit SR7 returns to “0” and STS output (in default mode) transitions to VOL. However, SR6 remains “1” to indicate block erase suspend status. Using the PROGRAM SUSPEND command, a PROGRAM operation can also be suspended. Resuming a suspended programming operation by issuing the PROGRAM RESUME command

22

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

enables the suspended programming operation to continue. To resume the suspended erase, the user must wait for the programming operation to complete before issuing the BLOCK ERASE RESUME command. While block erase is suspended, the only other valid commands are READ QUERY, READ STATUS REGISTER, CLEAR STATUS REGISTER, CONFIGURE, and BLOCK ERASE RESUME. After a BLOCK ERASE RESUME command to the Flash memory is completed, the ISM continues the block erase process. Status register bits SR6 and SR7 automatically clear and STS (in default mode) returns to VOL. After the ERASE RESUME command is completed, the device automatically outputs status register data when read. VPEN must remain at

PENH (the same VPEN level used for block erase) during

V block erase suspension. Block erase cannot resume during block erase suspend until PROGRAM operations are complete.

WRITE-TO-BUFFER COMMAND

The write-to-buffer command sequence is initiated to program the Flash device via the write buffer. A buffer can be loaded with a variable number of bytes, up to the buffer size, before writing to the Flash device. First, the WRITE-to-BUFFER SETUP command is issued, along with the block address (see Figure 4). Then, the extended status register (XSR; see Table 17) information is loaded and XSR7 indicates “buffer available” status. If XSR7 = 0, the write buffer is not available. To retry, issue the WRITE-to-BUFFER SETUP command with the block address and continue monitoring XSR7 until XSR7 = 1. When XSR7 transitions to “1,” the buffer is ready for loading new data. Then the part is given a word/byte count with the block address. On the next write, a device start address is given, along with the write buffer data. Depending on the count, subsequent writes provide additional device addresses and data. All subsequent addresses must lie within the start address plus the count.

The device internally programs many Flash cells in parallel. Due to this parallel programming, maximum programming performance and lower power are obtained by aligning the start address at the beginning of a write buffer boundary (i.e., A0–A4 of the start address = 0).

When the final buffer data is given, a WRITE CONFIRM command is issued, thus programming the ISM to begin copying the buffer data to the Flash array. If the device receives a command other than WRITE CONFIRM, an invalid command/sequence error is generated and status register bits SR5 and SR4 are set to “1.” For additional BUFFER WRITEs, issue another WRITEto-BUFFER SETUP command and check XSR7.

If an error occurs during a WRITE, the device stops writing, and status register bit SR4 is set to a “1” to indicate a program failure. The ISM only detects errors for “1s” that do not successfully program to “0s.” When a program error is detected, the status register should be cleared. Note that the device does not accept any more WRITE-to-BUFFER commands any time SR4 and/ or SR5 is set. In addition, if the user attempts to program past an erase block boundary with a WRITE-toBUFFER command, the device aborts the WRITE-toBUFFER operation and generates an invalid command/ sequence error, and status register bits SR5 and SR4 are set to “1.”

Reliable BUFFERED WRITEs can only occur when

PEN = VPENH. If a BUFFERED WRITE is attempted while

V V

PEN ≤ VPENLK, status register bits SR4 and SR3 are set to

“1.” Buffered write attempts with invalid VCC and VPEN voltages produce spurious results and should not be attempted. Finally, the corresponding block lock bit should be reset for successful programming. When a BUFFERED WRITE is attempted while the corresponding block lock bit is set, SR1 and SR4 are set to “1.”

BYTE/WORD PROGRAM COMMANDS

A two-cycle command sequence executes a byte/ word program setup. This program setup (standard 40h or alternate 10h) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). Next, the ISM takes over to internally control the programming and program verify algorithms. When the program sequence is written, the device automatically outputs status register data when read (see Figure 5). The CPU can detect the completion of the program event by analyzing the STS pin or status register bit SR7.

Upon program completion, status register bit SR4 should be checked. The status register should be cleared if a program error is detected. The ISM only detects errors for “1s” that do not successfully program to “0s.” The CEL remains in read status register mode until it receives another command.

Reliable byte/word programs can only occur when VCC and VPEN are valid. Status register bits SR4 and SR3 are set to “1” if a byte/word program is attempted while VPEN ≤ VPENLK. The corresponding block lock bit should be cleared for successful byte/word programs. If BYTE/ WORD is attempted while the corresponding block lock bit is set, SR1 and SR4 are set to “1.”

PROGRAM SUSPEND COMMAND

The PROGRAM SUSPEND command enables program interruption to read data in other Flash memory locations. After starting the programming process, writ-

23

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

ing the PROGRAM SUSPEND command requests that the ISM suspend the program sequence at a predetermined point in the algorithm. When the PROGRAM SUSPEND command is written, the device continues to output status register data when read. Polling status register bit SR7 can determine when the programming operation has been suspended. When SR7 = 1, SR2 is also set to “1” to indicate that the device is in the program suspend mode. STS in RY/BY# level mode also transitions to VOH. Note that tLPS defines the program suspend latency.

Hence, a READ ARRAY command can be written to read data from unsuspended locations. While programming is suspended, the only other valid commands are READ QUERY, READ STATUS REGISTER, CLEAR STATUS REGISTER, CONFIGURE, and PROGRAM RESUME. When the PROGRAM RESUME command is written, the ISM continues the programming process. Status register bits SR2 and SR7 automatically clear and STS in RY/BY# mode returns to VOL. After the PROGRAM RESUME command is written, the device automatically outputs status register data when read. VPEN must remain at VPENH and VCC must remain at valid VCC levels (the same VPEN and VCC levels used for programming) while in program suspend mode. Refer to Figure 6 (PROGRAM SUSPEND/RESUME Flowchart).

SET READ CONFIGURATION COMMAND

Q-Flash memory does not support the SET READ CONFIGURATION command. The devices default to the asynchronous page mode. If this command is given, the operation of the device will not be affected.

READ CONFIGURATION

Micron’s Q-Flash devices support both asynchronous page mode and standard word/byte READs without configuration requirement. Status register and identifier only support standard word/byte single READ operations.

STS CONFIGURATION COMMAND

Using the CONFIGURATION command, the STS pin can be configured to different states. Once configured, the STS pin remains in that configuration until another configuration command is issued, RP# is asserted LOW, or the device is powered down. Initially, the STS pin defaults to RY/BY# operation where RY/BY# goes LOW to indicate that the state machine is busy. When HIGH, RY/BY# indicates that either the state machine is ready for a new operation or it is suspended. Table 18, Configuration Coding Definitions, shows the possible STS configurations. To change the STS pin to other modes, the CONFIGURATION command is given, followed by the desired configuration code. The three alternate configurations are all pulse modes and may be used as a system interrupt. With these configurations, bit 0 controls erase complete interrupt pulse, and bit 1 controls program complete interrupt pulse. Providing the 00h configuration code with the CONFIGURATION command resets the STS pin to the default RY/BY# level mode. Table 18 describes possible configurations and usage. The CONFIGURATION command can only be given when the device is not busy or suspended. When configured in one of the pulse modes, the STS pin pulses LOW with a typical pulse width of 250ns. Check SR7 for device status. An invalid configuration code results in status register bits SR4 and SR5 being set to “1.”

24

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Table 18

Configuration Coding Definitions

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

RESERVED PULSE ON PULSE ON

DQ1–DQ0 = STS Configuration Codes NOTES

00 = Default, RY/BY# level mode Used to control HOLD to a memory controller to prevent accessing

(device ready) indication a Flash memory subsystem while any Flash device’s ISM is busy.

01 = Pulse on Erase Complete Used to generate a system interrupt pulse when any Flash device in

an array has completed a BLOCK ERASE or sequence of queued BLOCK ERASEs; helpful for reformatting blocks after file system free space reclamation or “cleanup.”

10 = Pulse on Program Complete Used to generate a system interrupt pulse when any Flash device in

an array has completed a PROGRAM operation. Provides highest performance for enabling continuous BUFFER WRITE operations.

11 = Pulse on Erase or Program Used to generate system interrupts to trigger enabling of Flash

Complete arrays when either ERASE or PROGRAM operations are completed

and a common interrupt service routine is desired.

1

PROGRAM ERASE

COMPLETE2COMPLETE

2

NOTE: 1. An invalid configuration code will result in both SR4 and SR5 being set.

2. When the device is configured in one of the pulse modes, the STS pin pulses LOW with a typical pulse width of 250ns.

SET BLOCK LOCK BITS COMMAND

A flexible block locking and unlocking scheme is enabled via a combination of block lock bits. The block lock bits gate PROGRAM and ERASE operations. Using the SET BLOCK LOCK BITS command, individual block lock bits can be set. This command is invalid when the ISM is running or when the device is suspended. SET BLOCK LOCK BITS commands are executed by a twocycle sequence. The set block lock bits setup, along with appropriate block address, is followed by the set block lock bits confirm and an address within the block to be locked. The ISM then controls the set lock bit algorithm. When the sequence is written, the device automatically outputs status register data when read (see Figure 9). The CPU can detect the completion of the set block lock bit event by analyzing the STS pin output or status register bit SR7. Upon completion of set block lock bits operation, status register bit SR4 should be checked for error. If an error is detected, the status register should be cleared. The CEL remains in read status register mode until a new command is issued. This two-step sequence of setup followed by execution ensures that lock bits are not accidentally set. An invalid SET BLOCK LOCK BITS command results in status register bits SR4 and SR5 being set to “1.” Also, reliable operation occurs only when VCC and VPEN are

valid. When VPEN ≤ VPENLK, lock bit contents are protected against any data change.

CLEAR BLOCK LOCK BITS COMMAND

The CLEAR BLOCK LOCK BITS command can clear all set block lock bits in parallel. This command is invalid when the ISM is running or the device is suspended. The CLEAR BLOCK LOCK BITS command is executed by a two-cycle sequence. First, a clear block lock bits setup is written, followed by a CLEAR BLOCK LOCK BITS CONFIRM command. Then the device automatically outputs status register data when read (see Figure 9). The CPU can detect completion of the clear block lock bits event by analyzing the STS pin output or the status register bit SR7. When the operation is completed, status register bit SR5 should be checked. If a clear block lock bits error is detected, the status register should be cleared. The CEL remains in read status register mode until another command is issued.

This two-step setup sequence ensures that block lock bits are not accidentally cleared. An invalid clear block lock bits command sequence results in status register bits SR4 and SR5 being set to “1.” Also, a reliable CLEAR BLOCK LOCK BITS operation can only occur when VCC and VPEN are valid. If a CLEAR BLOCK

25

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

LOCK BITS operation is attempted when VPEN ≤ VPENLK, SR3 and SR5 are set to “1.” If a CLEAR BLOCK LOCK BITS operation is aborted due to VPEN or VCC transitioning out of valid range, block lock bit values are left in an undetermined state. To initialize block lock bit contents to known values, a repeat of CLEAR BLOCK LOCK BITS is required.

PROTECTION REGISTER PROGRAM COMMAND

The 3V Q-Flash memory includes a 128-bit protection register to increase the security of a system design. For example, the number contained in the protection register can be used for the Flash component to communicate with other system components, such as the CPU or ASIC, to prevent device substitution. The 128 bits of the protection register are divided into two 64bit segments. One of the segments is programmed at the Micron factory with a unique and unchangeable 64-bit number. The other segment is left blank for customers to program as needed. After the customer segment is programmed, it can be locked to prevent reprogramming.

READING THE PROTECTION REGISTER

The protection register is read in the identification read mode. The device is switched to identification read mode by writing the READ IDENTIFIER command (90h). When in this mode, READ cycles from addresses shown in Table 19 or Table 20 retrieve the specified information. To return to read array mode, the READ ARRAY command (FFh) must be written.

PROGRAMMING THE PROTECTION REGISTER

The protection register bits are programmed with two-cycle PROTECTION PROGRAM commands.

The 64-bit number is programmed 16 bits at a time for word-wide parts and eight bits at a time for bytewide parts. First, the PROTECTION PROGRAM SETUP command, C0h, is written. The next write to the device latches in addresses and data, and programs the specified location. The allowable addresses are shown in Table 19 and Table 20. Any attempt to address PROTECTION PROGRAM commands outside the defined

protection register address space results in a status register error (program error bit SR4 is set to “1”). Attempting to program a locked protection register segment results in a status register error (program error bit SR4 and lock error bit SR1 are set to “1”).

LOCKING THE PROTECTION REGISTER

By programming bit 1 of the PR-LOCK location to “0,” the user-programmable segment of the protection register is lockable. To protect the unique device number, bit 0 of this location is programmed to “0” at the Micron factory. Bit 1 is set using the PROTECTION PROGRAM command to program “FFFDh” to the PR-LOCK location. When these bits have been programmed, no further changes can be made to the values stored in the protection register. PROTECTION PROGRAM commands to a locked section will result in a status register error (program error bit SR4 and lock error bit SR1 are set to “1”). Note that the protection register lockout state is not reversible.

Figure 3

Protection Register Memory Map

Word

Address

88h

4 Words

User-Programmed

85h 84h

4 Words

Factory-Programmed

81h 80h 0

NOTE: A0 is not used in x16 mode when accessing the

protection register map (see Table 19 for x16 addressing). A0 is used for x8 mode (see Table 20 for x8 addressing).

1 Word Lock

26

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Table 19

Word-Wide Protection Register Addressing

WORD USE A8 A7 A6 A5 A4 A3 A2 A1

LOCK Both 1 0 0 00000

0 Factory 1 0 0 00001 1 Factory 1 0 0 00010 2 Factory 1 0 0 00011 3 Factory 1 0 0 00100 4 User 1 0 0 00101 5 User 1 0 0 00110 6 User 1 0 0 00111 7 User 1 0 0 01000

Table 20

Byte-Wide Protection Register Addressing

BYTE USE A 8 A7 A6 A5 A4 A 3 A2 A1 A 0

LOCK Both 100000000

0 Factory 100000010 1 Factory 100000011 2 Factory 100000100 3 Factory 100000101 4 Factory 100000110 5 Factory 100000111 6 Factory 100001000 7 Factory 100001001 8 User 100001010

9 User 100001011 A User 100001100 B User 100001101 C User 100001110 D User 100001111

E User 100010000

F User 100010001

NOTE: 1. All address lines not specified in the above tables must be “0” when accessing the

protection register (i.e., A22–A9 = 0).

27

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Figure 4

WRITE-to-BUFFER Flowchart

Start

Set Timeout

WRITE-to-BUFFER

Write Buffer Data,

WRITE-to-BUFFER

Yes

Write Next Buffer

Data, Device Address

Program Buffer to

Flash Confirm D0h

Yes

WRITE-to-BUFFER

Read Status Register

Issue

Command E8h,

Block Address

Read Extended Status Register

XSR7 =

1

Write Word or

Byte Count N, Block Address

Start Address

X = 0

Yes

Check X = N?

No

Abort

Command?

No

X = X + 1

Another

?

No

1

SR7 =

0

Yes

0

No

WRITE-to-

BUFFER Timeout?

Write to Another

Block Address

Write to Buffer

Aborted

READ STATUS

Yes

Issue

Command

BUS OPERATION COMMAND COMMENTS

WRITE WRITE-to- Data = E8h

BUFFER Block Address

READ XS R7 = Valid

Addr = Block Address

STANDBY Check XSR7

1 = Write Buffer Available 0 = Write Buffer Not Available

1, 2

WRITE

Data = N = Word/Byte Count N = 0 Corresponds to Count = 1 Addr = Block Address

3, 4

WRITE

Data = Write Buffer Data Addr = Device Start Address

5, 6

WRITE

Data = Write Buffer Data Addr = Device Address

WRITE Program Data = D0h

Buffer to Addr = Block Address Flash Confirm

7

READ

Status register data with the device enabled, OE# LOW updates SR Addr = Block Address

STANDBY Check SR7

1 = ISM Ready 0 = ISM Busy

Full status check can be done after all erase and write sequences complete. Write FFh after the last operation to reset the device to read array mode.

1

Full Status

Check if Desired

Programming

Complete

NOTE: 1. Byte or word count values on DQ0–DQ7 are loaded into the count register. Count ranges on this device for byte mode

are n = 00h to 1Fh and for word mode are n = 0000h to 000Fh.

2. The device now outputs the status register when read (XSR is no longer available).

3. Write buffer contents will be programmed at the device start address or destination Flash address.

4. Align the start address on a write buffer boundary for maximum programming performance (i.e., A4–A0 of the start address = 0).

5. The device aborts the WRITE-to-BUFFER command if the current address is outside of the original block address.

6. The status register indicates an “improper command sequence” if the WRITE-to-BUFFER command is aborted. Follow this with a CLEAR STATUS REGISTER command.

7. Toggling OE# (LOW to HIGH to LOW) updates the status register. This can be done in place of issuing the READ STATUS REGISTER command.

28

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Figure 5

Byte/Word Program Flowchart

Start

Write 40h,

Address

Write Data and

Address

Read Status

Register

SR7 =

1

Full Status

Check if Desired

Byte/Word

Program Complete

0

BUS OPERATION COMMAND COMMENTS

WRITE SETUP BYTE/ Data = 40h

WORD Addr = Location to be PROGRAM Programmed

WRITE BYTE/ Data = Data to be

WORD Programmed PROGRAM Addr = Location to be

Programmed

READ Status Register Data

STANDBY Check SR7

1 = ISM Ready 0 = ISM Busy

Toggling OE# (LOW to HIGH to LOW) updates the status register. This can be done in place of issuing the READ STATUS REGISTER command. Repeat for subsequent programming operations.

After each program operation or after a sequence of programming operations, an SR full status check can be done.

Write FFh after the last program operation to place the device in read array mode.

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (see above)

1

SR3 =

0

SR1 =

0

SR4 =

0

Byte/Word

Program Successful

Voltage Range Error

1

Device Protect Error

1

Programming Error

BUS OPERATION COMMAND COMMENTS

STANDBY Check SR3

1 = Programming to

Voltage Error Detect

STANDBY Check SR1

1 = Device Protect Detect RP# = VIH, Block Lock Bit is

Set Only required for systems implemeting lock bit configuration

STANDBY Check SR4

1 = Programming Error

Toggling OE# (LOW to HIGH to LOW) updates the status register. This can be done in place of issuing the READ STATUS REGISTER command. Repeat for subsequent programming operations.

SR4, SR3, and SR1 are only cleared by the CLEAR STATUS REGISTER command in cases where multiple locations are programmed before full status is checked.

If an error is detected, clear the status register before attempting retry or other error recovery.

29

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Figure 6

PROGRAM SUSPEND/RESUME Flowchart

Start

Write B0h

Read Status

Register

SR7 =

1

SR2 =

1

Write FFh

Read Data Array

1

0

Programming

Completed

BUS OPERATION COMMAND COMMENTS

WRITE PROGRAM Data = B0h

SUSPEND Addr = X

READ Status Register Data

Addr = X

STANDBY Check SR7

1 = ISM Ready 0 = ISM Busy

STANDBY Check SR6

1 = Programming

Suspended

0 = Programming

Completed

WRITE READ Data = FFh

ARRAY Addr = X

READ Read array locations other

than that being programmed

WRITE PROGRAM Data = D0h

RESUME Addr = X

Done Reading

Yes

Write D0h

Programming

Resumed

No

Write FFh

Read Data Array

30

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

BLOCK ERASE Flowchart

Start

Issue Single BLOCK

ERASE Command 20h,

Block Address

Write Confirm D0h

Block Address

Read Status

Register

SR7 = Suspend Erase

1

Full Status

Check if Desired

Erase Flash

Block(s) Complete

Figure 7

No

Yes

Suspend Erase Loop

BUS OPERATION COMMAND COMMENTS

WRITE ERASE Data = 20h

BLOCK Addr = Block Address

WRITE ERASE Data = D0h

CONFIRMED Addr = Block Address

READ Status register data with

the device enabled; OE# LOW updates SR Addr = X

STANDBY Check SR7

1 = ISM Ready 0 = ISM Busy

The erase confirm byte must follow erase setup. This device does not support erase queuing.

Full status check can be done after all erase and write sequences complete. Write FFh after the last operation to reset the device to read array mode.

31

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Figure 8

BLOCK ERASE SUSPEND/RESUME

Flowchart

Start

Write B0h

Read Status

Register

SR7 =

SR6 =

Read Program

Read Array

Data

Read or

Program?

Done?

0

1

0

1

No

Program

BLOCK ERASE

Completed

Loop

BUS OPERATION COMMAND COMMENTS

WRITE ERASE Data = B0h

SUSPEND Addr = X

READ Status Register Data

Addr = X

STANDBY Check SR7

1 = ISM Ready 0 = ISM Busy

STANDBY Check SR6

1 = Block Erase Suspended 0 = Block Erase Completed

WRITE ERASE Data = D0h

RESUME Addr = X

Yes

Write D0h

BLOCK ERASE

Resumed

Write FFh

Read Data Array

32

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Figure 9

SET BLOCK LOCK BITS Flowchart

Start

Write 60h,

Block Address

Write 01h,

Block Address

Read Status

Register

SR7 =

1

Full Status

Check if Desired

SET BLOCK LOCK BITs

Complete

0

BUS OPERATION COMMAND COMMENTS

WRITE SET BLOCK Data = 60h

LOCK BITS Addr = Block Address SETUP

WRITE SET BLOCK Data = 01h

LOCK BITS Addr = Block Address CONFIRM

READ Status Register Data

STANDBY Check SR7

1 = ISM Ready 0 = ISM Busy

Repeat for subsequent lock bit operations.

Full status check can be done after each lock bit set operation or after a sequence of lock bit set operations

Write FFh after the last lock bit set operation to place device in read array mode.

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (see above)

1

SR3 =

0

SR4,5 =

0

SR4 =

0

SET BLOCK LOCK BITS

Successful

Voltage Range Error

1

Command Sequence

1

SET BLOCK LOCK BITS

Error

BUS OPERATION COMMAND COMMENTS

STANDBY Check SR3

1 = Programming Voltage

Error Detect

STANDBY Check SR4, SR5

Both 1 = Command

Sequence Error

STANDBY Check SR4

1 = Set Block Lock Bits

Error

SR5, SR4, and SR3 are only cleared by the CLEAR STATUS REGISTER command in cases where multiple lock bits are set before full status is checked.

If an error is detected, clear the status register before attempting retry or other error recovery.

33

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Figure 10

CLEAR BLOCK LOCK BITS Flowchart

Start

Write 60h

Write D0h

Read Status

Register

SR7 =

1

Full Status

Check if Desired

CLEAR BLOCK LOCK

BITS Complete

0

BUS OPERATION COMMAND COMMENTS

WRITE CLEAR Data = 60h

BLOCK LOCK

Addr = X

BITS SETUP

WRITE

CLEAR BLOCK

Data = D0h

LOCK BITS Addr = X or CONFIRM

READ Status Register Data

STANDBY Check SR7

1 = ISM Ready 0 = ISM Busy

Write FFh after the CLEAR BLOCK LOCK BITS operation to place device in read array mode.

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (see above)

1

SR3 =

0

SR4,5 =

0

SR5 =

0

CLEAR BLOCK LOCK

BITS Successful

Voltage Range Error

1

Command Sequence

1

CLEAR BLOCK LOCK

Error

BITS Error

BUS OPERATION COMMAND COMMENTS

STANDBY Check SR3

1 = Programming Voltage

Error Detect

STANDBY Check SR4, 5

Both 1 = Command

Sequence Error

STANDBY Check SR5

1 = Clear Block Lock Bits

Error

SR5, SR4, and SR3 are only cleared by the CLEAR STATUS REGISTER command.

If an error is detected, clear the status register before attempting retry or other error recovery.

34

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Figure 11

PROTECTION REGISTER PROGRAMMING

Flowchart

Start

Write C0h

(Protection Register

Program Setup)

Write Protect Register

Address/Data

Read Status

Register

SR7 = 1

Yes

Full Status

Check if Desired

PROGRAM

Complete

No

BUS OPERATION COMMAND COMMENTS

WRITE

PROTECTION

Data = C0h

PROGRAM SETUP

WRITE

PROTECTION

Data = Data to Program

PROGRAM Addr = Location to

Program

READ Status Register Data

Toggle CE# or OE# to update status register data

STANDBY Check SR7

1 = ISM Ready 0 = ISM Busy

PROTECTION PROGRAM operations can only be addressed within the protection register address space. Addresses outside the defined space will return an error.

Repeat for subsequent programming operations.

SR full status check can be done after each program or after a sequence of program operations.

Write FFh after the last program operation to reset device to read array mode.

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (see above)

SR3, SR4 =

SR1, SR4 =

PROGRAM

Successful

1, 1

0, 1

PROTECTION REGISTER

PROGRAMMING Error

Attempted Program to

1, 1

VPEN Range Error

Locked Register –

Aborted

BUS COMMENTS OPERATION COMMAND SR1 SR3 SR4

STANDBY 0 1 1 VPEN LOW

STANDBY 0 0 1 Protection

Register Program Error

STANDBY 1 0 1 Register

Locked: Aborted

SR3, if set during a program attempt, MUST be cleared before further attempts are allowed by the ISM.

SR1, SR3, and SR4 are only cleared by the CLEAR STAUS REGISTER command, in cases of multiple protection register program operations, before full status is checked.

If an error is detected, clear the status register before attempting retry or other error recovery.

35

DESIGN CONSIDERATIONS

FIVE-LINE OUTPUT CONTROL

Micron provides five control inputs (CE0, CE1, CE2, OE#, and RP#) to accommodate multiple memory connections in large memory arrays. This control provides the lowest possible memory power dissipation and ensures that data bus contention does not occur.

To efficiently use these control inputs, an address decoder should enable the device (see Table 2) while OE# is connected to all memory devices and the system’s READ# control line. This ensures that only selected memory devices have active outputs while deselected memory devices are in standby mode. During system power transitions, RP# should be connected to the system POWERGOOD signal to prevent unintended writes. POWERGOOD should also toggle during system reset.

STS AND BLOCK ERASE, PROGRAM, AND LOCK BIT CONFIGURATION

POLLING

As an open drain output, STS should be connected to VCCQ by a pull-up resistor to provide a hardware method of detecting block erase, program, and lock bit configuration completion. It is recommended that a

2.5KΩ resistor be used between STS# and VCCQ. In default mode, it transitions LOW after block erase, program, or lock bit configuration commands and returns to High-Z when the ISM has finished executing the internal algorithm. See the CONFIGURATION com-

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

mand for alternate configurations of the STS pin. STS can be connected to an interrupt input of the system CPU or controller. STS is active at all times. In default mode, it is also High-Z when the device is in block erase suspend (with programming inactive), program suspend, or reset/power-down mode.

POWER SUPPLY DECOUPLING

Device decoupling is required for Flash memory power switching characteristics. There are three supply current issues to consider: standby current levels, active current levels, and transient peaks produced by falling and rising edges of CEx and OE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection suppresses transient voltage peaks. Because Micron Q-Flash memory devices draw their power from three V devices do not include a VPP pin), it is recommended that systems without separate power and ground planes attach a 0.1µF ceramic capacitor between each of the device’s three VCC pins (this includes VCCQ) and GND. These high-frequency, low-inductance capacitors should be placed as close as possible to package leads on each Micron Q-Flash memory device. Additionally, for every eight devices, a 4.7µF electrolytic capacitor should be placed between VCC and GND at the array’s power supply connection.

CC pins (these

36

REDUCING OVERSHOOTS AND UNDERSHOOTS WHEN USING BUFFERS OR TRANSCEIVERS

Overshoots and undershoots can sometimes cause input signals to exceed Flash memory specifications as faster, high-drive devices such as transceivers or buffers drive input signals to Flash memory devices. Many buffer/transceiver vendors now carry bus-interface devices with internal output-damping resistors or reduced-drive outputs. Internal output-damping resistors diminish the nominal output drive currents, while still leaving sufficient drive capability for most applications. These internal output-damping resistors help reduce unnecessary overshoots and undershoots by diminishing output-drive currents. When considering a buffer/transceiver interface design to Flash, devices with internal output-damping resistors or reduced-drive outputs should be used to minimize overshoots and undershoots.

VCC, VPEN, RP# TRANSITIONS

If VPEN or VCC falls outside of the specified operating ranges, or RP# is not set to VIH, block erase, program, and lock bit configuration are not guaranteed. If RP# transitions to VIL during block erase, program, or lock bit configuration, STS (in default mode) will remain LOW for a maximum time of tPLPH + tPHRH, until the RESET operation is complete and the device enters reset/power-down mode. The aborted operation may leave data partially corrupted after programming, or partially altered after an erase or lock bit configuration. Therefore, BLOCK ERASE and LOCK BIT CONFIGURATION commands must be repeated after normal operation is restored. Device power-off or RP# = VIL clears the status register. The CEL latches commands issued by system software and is not altered by VPEN or CEx transitions, or ISM actions. Its state is read array mode

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

upon power-up, upon exiting reset/power-down mode, or after VCC transitions below VLKO. VCC must be kept at or above VPEN during VCC transitions.

After block erase, program, or lock bit configuration, and after V placed in read array mode via the READ ARRAY command if subsequent access to the memory array is desired. During VPEN transitions, VPEN must be kept at or below V

POWER-UP/DOWN PROTECTION

During power transition, the device itself provides protection against accidental block erasure, programming, or lock bit configuration. Internal circuitry resets the CEL to read array mode at power-up. A system designer must watch out for spurious writes for VCC voltages above VLKO when VPEN is active. Because WE# must be LOW and the device enabled (see Table 2) for a command write, driving WE# to VIH or disabling the device inhibits WRITEs. The CEL’s two-step command sequence architecture provides added protection against data alteration. In-system block lock and unlock capability protects the device against inadvertent programming. The device is disabled when RP# = VIL regardless of its control inputs. Keeping VPEN below VPENLK prevents inadvertent data change.

POWER DISSIPATION

Designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory’s nonvolatility increases usable battery life because data is retained when system power is removed.

PEN transitions to VPENLK, the CEL must be

CC.

37

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

ABSOLUTE MAXIMUM RATINGS*

Temperature Under

Bias Expanded ................................... –40ºC to +85ºC

Storage Temperature ........................... –65ºC to +125ºC

CCQ = +2.7V to +3.6V

For V

Voltage On Any Pin ........................ –2.0V to +5.0V**

For V

CCQ = +4.5V to +5.5V

All Pins Except VCC .......................... –2.0V to +7.0V**

VCC ..................................................... –2.0V to +5.5V**

Output Short Circuit Current.............................100mA

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **All specified voltages are with respect to GND. Minimum DC voltage is –0.5V on input/output pins and

-0.2V on VCC and VPEN pins. During transitions, this level may undershoot to –2.0V for periods <20ns. Maximum

†

DC voltage on input/output pins, VCC, and VPEN is VCC +0.5V which, during transitions, may overshoot to VCC +2.0V for periods <20ns. †Output shorted for no more than one second. No more than one output shorted at a time.

38

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

TEMPERATURE AND RECOMMENDED DC OPERATING CONDITIONS

Commercial Temperature (0ºC ≤ TA ≤ +85ºC), Extended Temperature (-40ºC ≤ TA ≤ +85ºC)

PARAMETER SYMBOL MIN MAX UNITS NOTES

VCC Supply Voltage (2.7V–3.6V) VCC1 2.7 3.6 V

VCCQ Supply Voltage (2.7V–3.6V) VCCQ1 2.7 3.6 V

VCCQ Supply Voltage (4.5V–5.5V) VCCQ2 4.5 5.5 V

INPUT AND VPEN LOAD CURRENT VCC = VCC (MAX); VCCQ = VCCQ (MAX) ILI ±1 µA 1 VIN = VCCQ or GND

OUTPUT LEAKAGE CURRENT VCC = VCC (MAX); VCCQ = VCCQ (MAX) ILO ±10 µA 1 VIN = VCCQ or GND

INPUT LOW VOLTAGE VIL -0.5 0.8 V 2

INPUT HIGH VOLTAGE VIH 2VCCQ + 0.5 V 2

OUTPUT LOW VOLTAGE (2.7V–3.6V) VCCQ = VCCQ1 (MIN) VOL 0.4 V 2, 3 IOL = 2mA

VCCQ = VCCQ1 (MIN) 0.2 V IOL = 100µA

OUTPUT LOW VOLTAGE (4.5V–5.5V) VCCQ = VCCQ2 (MIN) VOL 0.45 V 4 IOL = 2mA

OUTPUT LOW VOLTAGE (4.5V–5.5V) VCCQ = VCCQ2 (MIN) 0.25 V 4 IOL = 100µA

OUTPUT HIGH VOLTAGE (2.7V–3.6V) VCCQ = VCCQ (MIN) VOH IOH = -2.5mA

VCCQ = VCCQ (MIN) VCCQ IOH = -100µA

OUTPUT HIGH VOLTAGE (4.5V–5.5V) VCCQ = VCCQ2 (MIN) VOH IOH = -2.5mA

VCCQ = VCCQ2 (MIN) VCCQ IOH = -100µA

0.85 × VCCQ

0.2 V

2.4

0.2 V

V2

V4

NOTE: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds).

2. Sampled, not 100% tested.

3. Includes STS.

4. MT28F320J3RG-11 F and MT28F640J3RG-12 F only.

39

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

CAPACITANCE

(TA = +25ºC; f = 1 MHz)

PARAMETER/CONDITION SYMBOL TYP MAX UNITS

Input Capacitance C 5 8 p F

Output Capacitance BYTE# COUT 10 12 p F

All other Pins COUT 512pF

RECOMMENDED DC ELECTRICAL CHARACTERISTICS

Commercial Temperature (0ºC ≤ TA ≤ +85ºC), Extended Temperature (-40ºC ≤ TA ≤ +85ºC)

DESCRIPTION CONDITIONS SYMBOL TYP MAX UNITS NOTES

VCC Standby CMOS Inputs; VCC = VCC (MAX); ICC1 50 120 µA 1, 2, 3 Current Device is enabled;

RP# = VCCQ ±0.2V

TTL inputs; VCC = VCC (MAX); 0.71 2 mA Device is enabled; RP# = VIH

VCC Power-Down RP# = GND ±0.2V; ICC2 50 120 µA Current IOUT (STS) = 0mA

VCC Page Mode CMOS inputs; VCC = VCC (MAX); ICC3 11 20 mA 1, 3 Read Current VCCQ = VCCQ (MAX) using standard

4-word page mode READs;

Device is enabled;

f = 5 MHz; IOUT = 0mA

CMOS inputs; VCC = VCC (MAX); 15 29 mA

VCCQ = VCCQ (MAX) using standard

4-word page mode READs;

Device is enabled;

f = 33 MHz; IOUT = 0mA

VCC Asynchronous Mode CMOS inputs; VCC = VCC (MAX); ICC4 12.5 50 mA 1, 3 Read Current VCCQ = VCCQ (MAX) using

standard word/byte single READs;

Device is enabled;

f = 5 MHz; IOUT = 0mA

NOTE: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds).

2. Includes STS.

3. CMOS inputs are either VCC ±0.2V or VSS ±0.2V. TTL inputs are either VIL or VIH.

4. Sampled, not 100% tested.

5. ICCWS and ICCES are specified with the device deselected. If the device is read or written while in erase suspend mode, the device’s current draw is ICCR or ICCW.

6. Block erase, programming, and lock bit configurations are inhibited when VPEN ≤ VPENLK, and they are not guaranteed in the range between VPENLK (MAX) and VPENH (MIN), or above VPENH (MAX).

7. Typically, VPEN is connected to VCC.

8. Block erase, programming, and lock bit configurations are inhibited when VCC < VLKO, and they are not guaranteed in the range between VLKO (MIN) and VCC (MIN), or above VCC (MAX).

(continued on next page)

40

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

RECOMMENDED DC ELECTRICAL CHARACTERISTICS (continued)

Commercial Temperature (0ºC ≤ TA ≤ +85ºC), Extended Temperature (-40ºC ≤ TA ≤ +85ºC)

DESCRIPTION CONDITIONS SYMBOL TYP MAX UNITS NOTES

VCC Program or Set CMOS inputs, VPEN = VCC ICC5 22 60 mA 1, 4 Lock Bits Current

VCC Block Erase or Clear CMOS inputs, VPEN = VCC ICC6 20 70 mA 1, 4 Block Lock Bits Current

VCC Program Suspend or Device is disabled ICC7 10 m A 1 Block Erase Suspend

Current

V

PEN Lockout during VPENLK 1 V 5, 6, 7

Program, Erase, and Lock Bit Operations

VPEN during Block Erase, VPENH 2.7 3.6 V 6, 7 Program, or Lock Bit Operations

VCC Lockout Voltage VLKO 2.2 V 8

TTL inputs, VPEN = VCC 24 70 mA

TTL inputs, VPEN = VCC 22 80 mA

NOTE: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds).

2. Includes STS.

3. CMOS inputs are either VCC ±0.2V or VSS ±0.2V. TTL inputs are either VIL or VIH.

4. Sampled, not 100% tested.

5. ICCWS and ICCES are specified with the device deselected. If the device is read or written while in erase suspend mode, the device’s current draw is ICCR or ICCW.

6. Block erase, programming, and lock bit configurations are inhibited when VPEN ≤ VPENLK, and they are not guaranteed in the range between VPENLK (MAX) and VPENH (MIN), or above VPENH (MAX).

7. Typically, VPEN is connected to VCC.

8. Block erase, programming, and lock bit configurations are inhibited when VCC < VLKO, and they are not guaranteed in the range between VLKO (MIN) and VCC (MIN), or above VCC (MAX).

41

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Figure 12

Transient Input/Output Reference Waveform for

VCCQ = 2.7V–3.6V, or VCCQ = 4.5V–5.5V

VCCQ

Test PointsInput VCCQ/2 VCCQ/2 Output

0.0

NOTE: AC test inputs are driven at VCCQ for a logic 1 and 0.0V for a logic 0. Input timing begins, and output timing ends, at VCCQ/

2V (50% of V

CCQ). Input rise and fall times (10% to 90%) < 5ns.

Figure 13

Transient Equivalent Testing Load Circuit

1.3V

1N914

R

= 3.3K

Ω

L

Device

Under Test

NOTE: CL includes jig capacitance

C

L

Out

Test Configuration Capacitance Loading Value

Test Configuration C

CCQ = VCC

V

CCQ =

= 2.7V to 3.6V 30

4.5V to 5.5V 30

L

(pF)

30

42

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

AC CHARACTERISTICS – READ-ONLY OPERATIONS

(Notes: 1, 2, 4); Commercial Temperature (0ºC ≤ TA ≤ +85ºC), Extended Temperature (-40ºC ≤ TA ≤ +85ºC)

VCC = 2.7V–3.6V

CCQ = 2.7V–3.6V

V

or 4.5V–5.5V

PARAMETER SYMBOL DENSITY MIN MAX UNITS NOTES

READ/WRITE Cycle Time

Address to Output Delay

CEx to Output Delay

OE# to Non-Array Output Delay OE# to Array Output Delay RP# HIGH to Output Delay

CEx to Output in Low-Z OE# to Output in Low-Z CEx HIGH to Output in High-Z OE# HIGH to Output in High-Z Output Hold from Address, CEx, or OE#

Change, Whichever Occurs First

CEx LOW to BYTE# HIGH or LOW BYTE# to Output Delay BYTE# to Output in High-Z CEx HIGH to CEx LOW Page Address Access Time

t

RC 32Mb 110 ns

64Mb 120 ns

128Mb 150 ns

t

AA 32Mb 110 ns

64Mb 120 ns

128Mb 150 ns

t

ACE 32Mb 110 ns

64Mb 120 ns

128Mb 150 ns

t

AOE ALL 50 ns 3, 5

t

AOA ALL 25 ns 5

t

RWH 32Mb 150 ns

64Mb 180 ns

128Mb 210 ns

t

OEC ALL 0 ns 6

t

OEO ALL 0 ns 6

t

ODC ALL 35 ns 6

t

ODO ALL 15 ns 6

t

OH ALL 0 ns 6

t

CB ALL 10 ns 6

t

ABY ALL 1,000 ns

t

ODB ALL 1,000 ns 6

t

CWH ALL 0 ns 6

t

APA ALL 25 ns 6

NOTE: 1. CEx LOW is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEx HIGH is defined at the first edge

of CE0, CE1, or CE2 that disables the device (see Table 2).

2. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.

3. OE# may be delayed up to tACE - tAOE after the first edge of CEx that enables the device (see Table 2) without impact on tACE .

4. See Figures 12 and 13, Transient Input/Output Reference Waveform for VCCQ = 2.7V–3.6V or VCCQ = 4.5V–5.5V, and Transient Equivalent Testing Load Circuit for testing characteristics.

5. When reading the Flash array, a faster tAOE applies. Nonarray READs refer to status register READs, QUERY READs, or DEVICE IDENTIFIER READs.

6. Sampled, not 100% tested.

43

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

PAGE MODE AND STANDARD WORD/BYTE READ OPERATIONS

V

CEx

VCC

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

t

ACE

V

IH

V

IL

V

OH

V

OL

V

IH

V

IL

t

RWH

t

OEC

VALID

ADDRESS

t

AA

t

OEO

t

RC

t

AOE/

t

AOA

VALID

OUTPUT

VALID

ADDRESS

VALID

OUTPUT

VALID

ADDRESS

t

APA

VALID

OUTPUT

VALID

ADDRESS

VALID

OUTPUT

ADDRESSES

(A22–A3)

ADDRESSES

(A2–A0)

Disabled

Enabled

OE#

WE#

DQ0–DQ15

t

ODC

t

ODO

t

OH

t

CWH

High-ZHigh-Z

V

IH

RP#

V

BYTE

IL

V

IH

V

IL

t

CB

TIMING PARAMETERS

VCC = 2.7V–3.6V

V

CCQ = 2.7V–3.6V

or 4.5V–5.5V

SYMBOL MIN MAX UNITS

t

RC (32Mb) 110 ns

t

RC (64Mb) 120 ns

t

RC (128Mb) 150 ns

t

AA (32Mb) 110 ns

t

AA (64Mb) 120 ns

t

AA (128Mb) 150 ns

t

ACE (32Mb) 110 ns

t

ACE (64Mb) 120 ns

t

ACE (128Mb) 150 ns

t

AOE 50 ns

t

AOA 25 ns

t

RWH (32Mb) 150 ns

t

ABY

t

ODB

UNDEFINED

V

CC = 2.7V–3.6V

V

CCQ = 2.7V–3.6V

or 4.5V–5.5V

SYMBOL MIN MAX UNITS

t

RWH (64Mb) 180 ns

t

RWH (128Mb) 210 ns

t

OEC 0 ns

t

OEO 0 n s

t

ODC 35 ns

t

ODO 15 ns

t

OH 0 ns

t

CB 10 ns

t

ABY 1,000 ns

t

ODB 1,000 n s

t

CWH 0 ns

t

APA 25 ns

NOTE: CEx LOW is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEx HIGH is defined as the first edge of

CE0, CE1, or CE2 that disables the device.

44

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

AC CHARACTERISTICS – WRITE OPERATIONS

(Notes: 1, 2, 3); Commercial Temperature (0ºC ≤ TA ≤ +85ºC), Extended Temperature (-40ºC ≤ TA ≤ +85ºC)

AC CHARACTERISTICS -11/-12/-15 PARAMETER SYMBOL MIN MAX UNITS NOTES

RP# High Recovery to WE# (CEx) Going LOW CEx (WE#) LOW to WE# (CEx) Going LOW Write Pulse Width Data Setup to WE# (CEx) Going HIGH Address Setup to WE# (CEx) Going HIGH CEx (WE#) Hold from WE# (CEx) HIGH Data Hold from WE# (CEx) HIGH Address Hold from WE# (CEx) HIGH Write Pulse Width HIGH VPEN Setup to WE# (CEx) Going HIGH Write Recovery Before Read WE# (CEx) HIGH to STS Going LOW VPEN Hold from Valid SRD, STS Going HIGH WE# (CEx) HIGH to Status Register Busy

NOTE: 1. CEx LOW is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEx HIGH is defined as the first edge

of CE0, CE1, or CE2 that disables the device.

2. Read timing characteristics during BLOCK ERASE, PROGRAM, and LOCK BIT CONFIGURATION operations are the same as during READ-only operations. Refer to AC Characteristics – Read-Only Operations.

3. A WRITE operation can be initiated and terminated with either CEX or WE#.

4. Sampled, not 100% tested.

5. Write pulse width (tWP) is defined from CEx or WE# going LOW (whichever goes LOW last) to CEx or WE# going HIGH (whichever goes HIGH first).

6. Refer to Table 4 for valid AIN and DIN for block erase, program, or lock bit configuration.

7. Write pulse width HIGH (t WPH) is defined from CEx or WE# going HIGH (whichever goes HIGH first) to CEx or WE# going LOW (whichever goes LOW first).

8. For array access, tAA is required in addition to tWR for any accesses after a WRITE.

9. STS timings are based on STS configured in its RY/BY# default mode.

10. VPEN should be held at VPENH until determination of block erase, program, or lock bit configuration success (SR1/3/4/5 =

0).

t

RS 1 µs 4

t

CS (tWS) 0 ns 5

t

WP (tCP) 70 ns 5

t

DS 50 ns 6

t

AS 55 ns 6

t

CH (tWH) 0 ns

t

DH 0 n s

t

AH 0 n s

t

WPH (tCPH) 30 ns 7

t

VPS 0 ns 4

t

WR 35 ns 8

t

STS 200 ns 9

t

VPH 0 ns 4, 9, 10

t

WB 200 ns 4

45

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

BLOCK ERASE, PROGRAM, AND LOCK BIT CONFIGURATION PERFORMANCE

(Notes: 1, 2, 3); Commercial Temperature (0ºC ≤ TA ≤ +85ºC), Extended Temperature (-40ºC ≤ TA ≤ +85ºC)

CHARACTERISTICS -11/-12/-15 PARAMETER SYMBOL TYP MAX

t

Write Buffer Byte Program Time

WED1 150 654 µs 4, 5, 6, 7

8

UNITS NOTES

(Time to Program 32 bytes/16 words)

Byte/Word Program Time (Using WORD/BYTE PROGRAM Command) Block Program Time (Using WRITE-to-BUFFER Command) Block Erase Time Set Lock Bits Time Clear Block Lock Bits Time Program Suspend Latency Time to Read Erase Suspend Latency Time to Read

t

WED2 14 630 µs 4

t

WED3 0.6 1.7 sec 4

t

WED4 0.75 5 sec 4

t

WED5 64 75 µs 4

t

WED6 0.5 0.7 sec 5

t

LP S 25 30 µs

t

LE S 26 35 µs

NOTE: 1. Typical values measured at TA = +25ºC and nominal voltages. Assumes corresponding lock bits are not set. Subject to

change based on device characterization.

2. These performance numbers are valid for all speed versions.

3. Sampled, but not 100% tested.

4. Excludes system-level overhead.

5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary.

6. Effective per-byte program time is 4.7µs/byte (typical).

7. Effective per-word program time is 9.4µs/word (typical).

8. MAX values are measured at worst-case temperature and VCC corner after 100,000 cycles.

46

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Addresses

Disabled

CEx (WE#)

Enabled

OE#

Disabled

WE# (CEx)

Enabled

DQ0–DQ15

STS

RP#

V

PEN

V

PENLK

V

OH

V

PENH

V

WRITE OPERATIONS

1

Note 3Note 2 Note 4 Note 5 Note 6 Note 7

IH

IL

IH

IL

t

RS

IH

IL

IH

IL

IH

IL

OL

IH

IL

A

IN

t

AS

t

CS

t

DS

D

IN

t

WPH

t

WP

A

IN

t

AH

t

CH

t

DH

t

VPS

WR

t

WB

D

IN

VALID

BUSY SRD

t

STS

VALID

READY SRD

t

VPH

D

IN

UNDEFINED

TIMING PARAMETERS

-11/-12/-15

SYMBOL MIN MAX UNITS

t

RS 1 µs

t

CS 0 ns

t

WP 70 ns

t

DS 50 ns

t

AS 55 ns

t

CH 0 ns

t

DH 0 ns

SYMBOL MIN MAX UNITS

t

AH 0 ns

t

WPH 30 ns

t

VPS 0 ns

t

WR 35 ns

t

STS 200 ns

t

VPH 0 ns

t

WB 200 ns

NOTE: 1. CEx LOW is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEx HIGH is defined at the first edge

of CE0, CE1, or CE2 that disables the device (see Table 2). STS is shown in its default mode (RY/BY#).

2. VCC power-up and standby.

3. Write block erase, write buffer, or program setup.

4. Write block erase or write buffer confirm, or valid address and data.

5. Automated erase delay.

6. Read status register or query data.

7. WRITE READ ARRAY command.

47

-11/-12/-15

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

Addresses

Disabled

CEx (WE#)

Enabled

OE#

Disabled

WE# (CEx)

Enabled

DQ0–DQ15

STS

RP#

VPEN

V

OH

V

PENH

PENLK

V

RESUME OPERATIONS

Note 2 Note 3

IH

IL

IH

IL

IH

IL

IH

IL

IH

IL

OL

IH

IL

t

CS

t

DS

AIN

t

Command

t

STS

AS

t

WP

t

CH

t

DH

t

WEH

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

1

AIN

t

AH

Command

Note 4

t

STS

UNDEFINED

TIMING PARAMETERS

-11/-12/-15

SYMBOL MIN MAX UNITS

t

CS 0 ns

t

WP 70 ns

t

DS 50 ns

t

AS 55 ns

t

CH 0 ns

SYMBOL MIN MAX UNITS

t

DH 0 ns

t

AH 0 ns

t

STS 200 ns

t

WE H 200 n s

NOTE: 1. CEx LOW is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEx HIGH is defined at the first edge

of CE0, CE1, or CE2 that disables the device (see Table 2). STS is shown in its default mode (RY/BY#).

2. Erase resume, or program resume.

3. Read status, erase suspend or program suspend.

4. STS value will be: VIH after ERASE SUSPEND and PROGRAM SUSPEND commands VIL after READ STATUS command

48

-11/-12/-15

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

RESET SPECIFICATIONS

(Note: 1); Commercial Temperature (0ºC ≤ TA ≤ +85ºC), Extended Temperature (-40ºC ≤ TA ≤ +85ºC)

CHARACTERISTICS -11/-12/-15 PARAMETER SYMBOL MIN MAX UNITS NOTES

RP# Pulse Low Time (If RP# is tied to V

CC, this specification is not applicable)

RP# HIGH to Reset during Block Erase, Program, or Lock Bit Configuration

t

PLPH 35 µs 2

t

PHRH 100 ns 3

STS

RP#

RESET OPERATION

V

IH

V

IL

V

IH

V

IL

t

PLPH

t

PHRH

4

NOTE: 1. STS is shown in its default mode (RY/BY#).

2. These specifications are valid for all product versions (packages and speeds).

3. If RP# is asserted while a BLOCK ERASE, PROGRAM, or LOCK BIT CONFIGURATION operation is not executing, then the minimum required RP# pulse LOW time is 100ns.

4. A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going HIGH until outputs are valid.

49

PIN #1 INDEX

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

56-PIN TSOP TYPE I

20.00 ±0.10

PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC

18.40 ±0.08 LEAD FINISH: TIN/LEAD PLATE

PACKAGE WIDTH AND LENGTH DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE

0.50 TYP

14.00 ±0.08

0.15

+0.03

-0.02

SEE DETAIL A

1.20 MAX

0.10

0.25

0.10

0.25

GAGE

PLANE

+0.10

-0.05

0.5 ±0.10

0.80 TYP

DETAIL A

NOTE: 1. All dimensions in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.

50

SEATING PLANE

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

64-BALL FBGA

0.850 ±0.075

0.08 C

64X ∅0.45

SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PREREFLOW DIAMETER IS Ø 0.40

7.00 ±0.05

BALL A8

3.50 ±0.05

C

1.00 TYP

3.50 ±0.05 5.50 ±0.05

10.00 ±0.10

7.00

C L

BALL A1 ID

BALL A1

1.00 TYP

C L

6.50 ±0.05

13.00 ±0.10

1.20 MAX

BALL A1 ID

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or 62% Sn, 36% Pb, 2%Ag SOLDER BALL PAD: Ø .33mm

NOTE: 1. All dimensions in millimeters.

DATA SHEET DESIGNATIONS

Preliminary: This data sheet contains initial characterization limits that are subject to change upon full

characterization of production devices. This designation applies to the MT28F320J3 and MT28F128J3 devices.

No Marking: This data sheet contains minimum and maximum limits specified over the complete power supply

and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. This designation applies to the MT28F640J3 device.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the Micron and M logos and Q-Flash are trademarks and/or servicemarks of Micron Technology, Inc.

51

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

REVISION HISTORY

Rev. 6 ......................................................................................................................................................................................... 8/02

• Added commercial temperature range

• Updated Configuration Coding Definitions table

• Removed 3.0V–3.6V VCCQ voltage range option

• Updated VLKO, VPENLK, tAOA, tODC, tAPA, tCH (tWH), tSTS, and tWB

• Added Resume Operations timing diagram

Rev. 5 ......................................................................................................................................................................................... 5/02

• Updated MT28F320J3 information

Rev. 4 ......................................................................................................................................................................................... 2/02

• Added VCCQ = 4.5V–5.5V parameter for 32Mb and 64Mb devices

• Updated erase and program timing parameters

• Removed Block Erase Status bit

Rev. 3 ......................................................................................................................................................................................... 6/01

• Updated package drawing and corresponding notes

Rev. 2 ......................................................................................................................................................................................... 5/01

• Added 128Mb device information

• Added 64-ball FBGA (1.0mm pitch) package

Original document, Rev. 1 .................................................................................................................................................. 12/00

52

Datasheet MT28F640J3RG-15ET, MT28F640J3RG-12, MT28F640J3RG-12ET, MT28F640J3RG-15, MT28F640J3FS-15ET Datasheet (MICRON)

Specifications and Main Features

Frequently Asked Questions

User Manual

GENERAL DESCRIPTION

DEVICE MARKING

PIN /BALL ASSIGNMENT (Top View)

56-Pin TSOP Type I

64-Ball FBGA

PIN/BALL DESCRIPTIONS

PIN/BALL DESCRIPTIONS (continued)

MEMORY ARCHITECTURE

OUTPUT DISABLE

BUS OPERATION

READ

STANDBY

RESET/POWER-DOWN

READ QUERY

READ IDENTIFIER CODES

WRITE

COMMAND DEFINITIONS

READ ARRAY COMMAND

READ QUERY MODE COMMAND

QUERY STRUCTURE OUTPUT

QUERY STRUCTURE OVERVIEW

CFI QUERY IDENTIFICATION STRING

SYSTEM INTERFACE INFORMATION

DEVICE GEOMETRY DEFINITION

PRIMARY VENDOR-SPECIFIC EXTENDED QUERY TABLE

READ IDENTIFIER CODES COMMAND

READ STATUS REGISTER COMMAND

CLEAR STATUS REGISTER COMMAND

BLOCK ERASE COMMAND

BLOCK ERASE SUSPEND COMMAND

WRITE-TO-BUFFER COMMAND

BYTE/WORD PROGRAM COMMANDS

PROGRAM SUSPEND COMMAND

SET READ CONFIGURATION COMMAND

READ CONFIGURATION

STS CONFIGURATION COMMAND

SET BLOCK LOCK BITS COMMAND

CLEAR BLOCK LOCK BITS COMMAND

PROTECTION REGISTER PROGRAM COMMAND

READING THE PROTECTION REGISTER

LOCKING THE PROTECTION REGISTER

DESIGN CONSIDERATIONS

FIVE-LINE OUTPUT CONTROL

STS AND BLOCK ERASE, PROGRAM, AND LOCK BIT CONFIGURATION

POLLING

POWER SUPPLY DECOUPLING

VCC, VPEN, RP# TRANSITIONS

POWER-UP/DOWN PROTECTION

POWER DISSIPATION

TEMPERATURE AND RECOMMENDED DC OPERATING CONDITIONS

CAPACITANCE

RECOMMENDED DC ELECTRICAL CHARACTERISTICS

RECOMMENDED DC ELECTRICAL CHARACTERISTICS (continued)

PAGE MODE AND STANDARD WORD/BYTE READ OPERATIONS

WRITE OPERATIONS

RESUME OPERATIONS

RESET SPECIFICATIONS

RESET OPERATION

56-PIN TSOP TYPE I

64-BALL FBGA