Datasheet MT28C3212P2FL-11BET, MT28C3212P2FL-11T, MT28C3212P2FL-10T, MT28C3212P2FL-10B, MT28C3212P2NFL-11TET Datasheet (MICRON)
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1
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory ©2002, Micron Technology, Inc.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
FLASH AND SRAM
COMBO MEMORY
MT28C3212P2FL
MT28C3212P2NFL
Low Voltage, Extended Temperature
FEATURES
• Flexible dual-bank architecture
• Support for true concurrent operations with no
latency:
Read bank b during program bank a and vice versa
Read bank b during erase bank a and vice versa
• Organization: 2,048K x 16 (Flash)
128K x 16 (SRAM)
• Basic configuration:
Flash
Bank a (4Mb Flash for data storage)
– Eight 4K-word parameter blocks
– Seven 32K-word blocks
Bank b (28Mb Flash for program storage)
– Fifty-six 32K-word main blocks
SRAM
2Mb SRAM for data storage
– 128K-words
• F_VCC, VCCQ, F_VPP, S_VCC voltages
1
1.65V (MIN)/1.95V (MAX) F_VCC read voltage or
1.80V (MIN)/2.20V (MAX) F_VCC read voltage
1.65V (MIN)/1.95V (MAX) S_VCC read voltage or
1.80V (MIN)/2.20V (MAX) S_VCC read voltage
1.65V (MIN)/1.95V (MAX) VCCQ or
1.80V (MIN)/2.20V (MAX) VCCQ
1.80V (TYP) F_VPP (in-system PROGRAM/ERASE)
0.0V (MIN)/2.20V (MAX) F_VPP (in-system
PROGRAM/ERASE)
2
12V ±5% (HV) F_VPP (production programming
compatibility)
• Asynchronous access time
1
Flash access time: 100ns or 110ns @ 1.65V F_VCC
SRAM access time: 100ns @ 1.65V S_VCC
• Page Mode read access
1
Interpage read access: 100ns/110ns @ 1.65V F_VCC
Intrapage read access: 35ns/45ns @ 1.65V F_VCC
• Low power consumption
• Enhanced suspend options
ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank
• Read/Write SRAM during program/erase of Flash
• Dual 64-bit chip protection registers for security
purposes
• PROGRAM/ERASE cycles
100,000 WRITE/ERASE cycles per block
• Cross-compatible command set support
Extended command set
Common Flash interface (CFI) compliant
NOTE: 1. These specifications are guaranteed for operation
within either one of two voltage ranges, 1.65V–1.95V
or 1.80V–2.20V. Use only one of the two voltage
ranges for PROGRAM and ERASE operations.
2. MT28C3212P2NFL only.
OPTIONS MARKING
• Timing
100ns -10
110ns -11
• Boot Block
Top T
Bottom B
•VPP1 Range
0.9V–2.2V None
0.0V–2.2V N
• Operating Temperature Range
Commercial Temperature (0oC to +70oC) None
Extended Temperature (-40oC to +85oC) ET
• Package
66-ball FBGA (8 x 8 grid) FL
Part Number Example:
MT28C3212P2FL-10 TET
BALL ASSIGNMENT
66-Ball FBGA (Top View)
A
B
C
D
E
F
G
H
1 2 3 4 5 6 7 8 9 10 11 12
Top View
(Ball Down)
NC
NC
A14
A9
DQ11
A6
A0
A15
A10
A19
S_OE#
A7
A4
A20
A16
F_WE#
S_V
SS
F_WP#
S_LB#
A18
F_V
CC
A12
S_WE#
DQ6
S_CE2
DQ10
DQ8
A2
F_V
SS
F_VSS
DQ14
DQ4
S_V
CC
DQ2
DQ0
A1
F_OE#
V
ccQ
DQ7
DQ5
F_V
CC
DQ3
DQ1
S_CE1#
NCNCNCNCNC
A13
DQ15
DQ13
DQ12
DQ9
A3
F_CE#
NC
NC
A11
A8
NC
F_RP#
F_V
PP
S_UB#
A17
A5
Page 2
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2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
Table 2
Cross Reference for Abbreviated Device Marks
PRODUCT SAMPLE MECHANICAL
PART NUMBER MARKING MARKING SAMPLE MARKING
MT28C3212P2FL-10 BET FW443 FX443 FY443
MT28C3212P2FL-10 TET FW442 FX442 FY442
MT28C3212P2FL-11 BET FW444 FX444 FY444
MT28C3212P2FL-11 TET FW433 FX433 FY433
MT28C3212P2NFL-11 TET FW445 FX445 FY445
GENERAL DESCRIPTION
The MT28C3212P2FL and MT28C3212P2NFL combination Flash and SRAM memory devices provide a
compact, low-power solution for systems where PCB
real estate is at a premium. The dual-bank Flash is a
high-performance, high-density, nonvolatile memory
device with a revolutionary architecture that can significantly improve system performance.
This new architecture features:
• A two-memory-bank configuration supporting
dual-bank burst operation;
• A high-performance bus interface providing a fast
page data transfer; and
• A conventional asynchronous bus interface.
The device also provides soft protection for blocks
by configuring soft protection registers with dedicated
command sequences. For security purposes, dual 64bit chip protection registers are provided.
The embedded WORD WRITE and BLOCK ERASE
functions are fully automated by an on-chip write state
machine (WSM). The WSM simplifies these operations
and relieves the system processor of secondary tasks.
An on-chip status register, one for each bank, can be
used to monitor the WSM status to determine the
progress of a PROGRAM/ERASE command.
The erase/program suspend functionality allows
compatibility with existing EEPROM emulation software packages.
The device takes advantage of a dedicated power
source for the Flash device (F_VCC) and a dedicated
power source for the SRAM device (S_VCC), both at
1.65V–1.95V or 1.80V–2.20V for optimized power consumption and improved noise immunity. The
MT28C3212P2FL and MT28C3212P2NFL devices sup-
port two VPP voltage ranges, VPP1 and VPP2. VPP1 is an incircuit voltage of 0.9V–2.2V (MT28C3212P2FL) or 0.0V–
2.2V (MT28C3212P2NFL). VPP2 is the production compatibility voltage of 12V ±5%. The 12V ±5% VPP2 is supported for a maximum of 100 cycles and 10 cumulative
hours. See Table 1.
The MT28C3212P2FL and MT28C3212P2NFL devices contain an asynchronous 2Mb SRAM organized
as 128K-words by 16 bits. These devices are fabricated
using an advanced CMOS process and high-speed/
ultra-low-power circuit technology.
The MT28C3212P2FL and MT28C3212P2NFL devices are packaged in a 66-ball FBGA package with
0.80mm pitch.
DEVICE MARKING
Due to the size of the package, Micron’s standard
part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to Micron part numbers in Table 2.
Table 1
VPP Voltage Ranges
VOLTAGE RANGE
DEVICE VPP1 VPP2
MT28C3212P2FL 0.9V–2.2V 11.4V–12.6V
MT28C3212P2NFL 0.0V–2.2V 11.4V–12.6V
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2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
PART NUMBERING INFORMATION
Micron’s low-power devices are available with sev-
eral different combinations of features (see Figure 1).
Table 3
Valid Part Number Combinations
BOOT BLOCK OPERATING
V
PP1 ACCESS STARTING TEMPERATURE
PART NUMBER RANGE TIME (ns) ADDRESS RANGE
MT28C3212P2FL-10 BET 0.9V–2.2V 100 Bottom -40oC to +85oC
MT28C3212P2FL-10 TET 0.9V–2.2V 100 Top -40oC to +85oC
MT28C3212P2FL-11 BET 0.9V–2.2V 110 Bottom -40oC to +85oC
MT28C3212P2FL-11 TET 0.9V–2.2V 110 Top -40oC to +85oC
MT28C3212P2NFL-11 TET 0.0V–2.2V 110 Top -40
o
C to +85oC
MT 28C 321 2 P 2 N FL-11 T ET
Micron Technology
Flash Family
28C = Dual-Supply Flash/SRAM Combo
Density/Organization/Banks
321 = 32Mb (2,048K x 16)
bank a = 1/8; bank b = 7/8
SRAM Density
2 = 2Mb SRAM (128K x 16)
Access Time
-10 = 100ns
-11 = 110ns
Read Mode Operation
P = Asynchronous/Page Read
Package Code
FL = 66-ball FBGA (8 x 8 grid)
Operating Temperature Range
None = Commercial (0ºC to +70ºC)
ET = Extended (-40ºC to +85ºC)
V
PP1
Range
None = 0.9V–2.2V
N = 0.0V–2.2V
Boot Block Starting Address
B = Bottom boot
T = Top boot
Operating Voltage Range
2 = 1.65V–1.95V or 1.80V–2.20V
Figure 1
Part Number Chart
Valid combinations of features and their corresponding part numbers are listed in Table 3.
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2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
BLOCK DIAGRAM
F_V
PP
S_OE#
S_CE2
S_CE1#
S_WE#
DQ0
–
DQ15
A17
–
A20
A0
–
A16
F_RP#
F_CE#
F_OE#
F_WE#
F_V
CC
F_WP#
F_V
SS
FLASH
SRAM
S_V
SS
S_UB#
S_LB#
2,048K x 16
128K x 16
Bank a
Bank b
S_V
CC
VCCQ
FLASH FUNCTIONAL BLOCK DIAGRAM
Address
Input
Buffer
X DEC
Y/Z DEC
Data Input
Buffer
Output
Multiplexer
Address
CNT/WSM
Output
Buffer
Status
Reg.
WSM
Program/
Erase
Pump Voltage
Generators
Address Latch
DQ0-DQ15
DQ0–DQ15
CSM
F_RST#
F_CE#
X DEC
Y/Z DEC
F_WE#
F_OE#
I/O Logic
A0–A20
Address
Multiplexer
Bank 2 Blocks
Y/Z Gating/Sensing
Data
Register
Bank 1 Blocks
Y/Z Gating/Sensing
ID Reg.
RCR
Block Lock
Device ID
Manufacturer’s ID
OTP
Query
PR Lock
Query/OTP
PR Lock
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2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
BALL DESCRIPTIONS
66-BALL FBGA
NUMBERS SYMBOL TYPE DESCRIPTION
A3, A4, A5, A6, A0–A20 Input Address Inputs: Inputs for the addresses during READ and WRITE
A7, A8, B3, B4, operations. Addresses are internally latched during READ and WRITE
B5, B6, E5, G3, cycles. Flash: A0–A20; SRAM: A0–A16.
G4, G5, G6, G7,
G8, G9, H4, H5,
H6
H7 F_CE# Input Flash Chip Enable: Activates the device when LOW. When CE# is HIGH,
the device is disabled and goes into standby power mode.
H9 F_OE# Input Flash Output Enable: Enables Flash output buffers when LOW. When
F_OE# is HIGH, the output buffers are disabled.
C3 F_WE# Input Flash Write Enable: Determines if a given cycle is a Flash WRITE cycle.
F_WE# is active LOW.
D4 F_RP# Input Reset. When F_RP# is a logic LOW, the device is in reset, which drives
the outputs to High-Z and resets the WSM. When F_RP# is a logic HIGH,
the device is in standard operation. When F_RP# transitions from logic
LOW to logic HIGH, the device resets all blocks to locked and defaults to
the read array mode.
E3 F_WP# Input Flash Write Protect. Controls the lock down function of the flexible
locking feature.
G10 S_CE1# Input SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level
deselects the SRAM and reduces the power consumption to standby
levels.
D8 S_CE2 Input SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level
deselects the SRAM and reduces the power consumption to standby
levels.
F5 S_OE# Input SRAM Output Enable: Enables SRAM output buffers when LOW. When
S_OE# is HIGH, the output buffers are disabled.
B8 S_WE# Input SRAM Write Enable: Determines if a given cycle is an SRAM WRITE cycle.
S_WE# is active LOW.
F3 S_LB# Input SRAM Lower Byte: When LOW, it selects the SRAM address lower byte
(DQ0–DQ7).
F4 S_UB# Input SRAM Upper Byte: When LOW, it selects the SRAM address upper byte
(DQ8–DQ15).
B7, B9, B10, DQ0–DQ15 Input/ Data Inputs/Outputs: Input array data on the second CE# and WE#
C7, C8, C9, Output cycle during PROGRAM command. Input commands to the command
C10, D7, E6, user interface when CE# and WE# are active. Output data when CE#
E8, E9, E10, and OE# are active.
F7, F8, F9, F10
(continued on next page)
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2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
BALL DESCRIPTIONS (continued)
66-BALL FBGA
NUMBERS SYMBOL TYPE DESCRIPTION
E4 F_VPP Input/ Flash Program/Erase Power Supply: [0.9V–2.2V or 11.4V–12.6V].
Supply Operates as input at logic levels to control complete device protection.
Provides backward compatibility for factory programming when driven
to 11.4V–12.6V. A lower F_VPP voltage range (0.0V–2.2V) is available on
the MT28C3212P2NFL device.
D10, H3 F_VCC Supply Flash Power Supply: [1.65V–1.95V or 1.80V–2.20V]. Supplies power for
device operation.
A9, H8 F_VSS Supply Flash Specific Ground: Do not float any ground pin.
D9 S_VCC Supply SRAM Power Supply: [1.65V–1.95V or 1.80V–2.20V]. Supplies power for
device operation.
D3 S_VSS Supply SRAM Specific Ground: Do not float any ground pin.
A10 VCCQ Supply I/O Power Supply: [1.65–1.95V or 1.80V–2.20V]. This input should be tied
directly to VCC.
A1, A2, A11, NC – No Connect: Lead is not internally connected; it may be driven or
A12, C4, H1, floated.
H2, H10, H11,
H12
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2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
NOTE: 1. Two devices may not drive the memory bus at the same time.
2. Allowable flash read modes include read array, read query, read configuration, and read status.
3. Outputs are dependent on a separate device controlling bus outputs.
4. Modes of the Flash and SRAM can be interleaved so that while one is disabled, the other controls outputs.
5. SRAM is enabled and/or disabled with the logical function: S_CE1# or S_CE2.
6. Simultaneous operations can exist, as long as the operations are interleaved such that only one device attempts to
control the bus outputs at a time.
7. Data output on lower byte only; upper byte High-Z.
8. Data output on upper byte only; lower byte High-Z.
9. Data input on lower byte only.
10. Data input on upper byte only.
TRUTH TABLE – FLASH
FLASH SIGNALS SRAM SIGNALS MEMORY OUPUT
MODES
F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB#
MEMORY DQ0–DQ15 NOTES
BUS CONTROL
Read H L L H SRAM must be High-Z Flash DOUT 1, 2, 3
Write H L H L Flash DIN 1
Standby H H X X Other High-Z 4
Output Disable H L H H SRAM any mode allowable Other High-Z 4, 5
Reset L X X X Other High-Z 4, 6
TRUTH TABLE – SRAM
FLASH SIGNALS SRAM SIGNALS MEMORY OUPUT
MODES
F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB#
MEMORY DQ0–DQ15 NOTES
BUS CONTROL
Read
DQ0–DQ15 L H L H L L SRAM D OUT 1, 3
DQ0–DQ7 L H L H H L SRAM DOUT LB 7
DQ8–DQ15 Flash must be High-Z L H L H L H SRAM DOUT UB 8
Write
DQ0–DQ15 L H H L L L SRAM D IN 1, 3
DQ0–DQ7 L H H L H L SRAM DIN LB 9
DQ8–DQ15 L H H L L H SRAM DIN UB 10
Standby H X X X X X Other High-Z 4
Flash any mode allowable X L X X X X Other High-Z 4
Output Disable L H X X X X Other High-Z 4
Page 8
FLASH
8
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
ARCHITECTURE AND MEMORY
ORGANIZATION
The Flash memory device contains two separate
memory banks (bank a and bank b) for simultaneous
READ and WRITE operations. Bank a is 2Mb deep and
contains 8 x 4K-word parameter blocks and seven 32K-
word blocks. Bank b is 28Mb deep, is equally sectored,
and contains fifty-six 32K-word blocks.
Figures 2 and 3 show the top and bottom memory
organizations.
Page 9
FLASH
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2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
Figure 2
Bottom Boot Block Device
Bank b = 28Mb
Block Block Size Address Range
(K-bytes/K-words) (x16)
70 64/32 1F8000h-1FFFFFh
69 64/32 1F0000h-1F7FFFh
68 64/32 1E8000h-1EFFFFh
67 64/32 1E0000h-1E7FFFh
66 64/32 1D8000h-1DFFFFh
65 64/32 1D0000h-1D7FFFh
64 64/32 1C8000h-1CFFFFh
63 64/32 1C0000h-1C7FFFh
62 64/32 1B8000h-1BFFFFh
61 64/32 1B0000h-1B7FFFh
60 64/32 1A8000h-1AFFFFh
59 64/32 1A0000h-1A7FFFh
58 64/32 198000h-19FFFFh
57 64/32 190000h-197FFFh
56 64/32 188000h-18FFFFh
55 64/32 180000h-187FFFh
54 64/32 178000h-17FFFFh
53 64/32 170000h-177FFFh
52 64/32 168000h-16FFFFh
51 64/32 160000h-167FFFh
50 64/32 158000h-15FFFFh
49 64/32 150000h-157FFFh
48 64/32 148000h-14FFFFh
47 64/32 140000h-147FFFh
46 64/32 138000h-13FFFFh
45 64/32 130000h-137FFFh
44 64/32 128000h-12FFFFh
43 64/32 120000h-127FFFh
42 64/32 118000h-11FFFFh
41 64/32 110000h-117FFFh
40 64/32 108000h-10FFFFh
39 64/32 100000h-107FFFh
38 64/32 0F8000h-0FFFFFh
37 64/32 0F0000h-0F7FFFh
36 64/32 0E8000h-0EFFFFh
35 64/32 0E0000h-0E7FFFh
34 64/32 0D800h-0DFFFFh
33 64/32 0D0000h-0D7FFFh
32 64/32 0C8000h-0CFFFFh
31 64/32 0C0000h-0C7FFFh
30 64/32 0B8000h-0BFFFFh
29 64/32 0B0000h-0B7FFFh
28 64/32 0A8000h-0AFFFFh
27 64/32 0A0000h-0A7FFFh
26 64/32 098000h-097FFFh
25 64/32 090000h-097FFFh
24 64/32 088000h-087FFFh
23 64/32 080000h-087FFFh
22 64/32 078000h-07FFFFh
21 64/32 070000h-077FFFh
20 64/32 068000h-067FFFh
19 64/32 060000h-067FFFh
18 64/32 058000h-05FFFFh
17 64/32 050000h-057FFFh
16 64/32 048000h-04FFFFh
15 64/32 040000h-047FFFh
Bank a = 4Mb
Block Block Size Address Range
(K-bytes/K-words) (x16)
14 64/32 038000h-03FFFFh
13 64/32 030000h-037FFFh
12 64/32 028000h-02FFFFh
11 64/32 020000h-027FFFh
10 64/32 018000h-01FFFFh
9 64/32 010000h-017FFFh
8 64/32 008000h-00FFFFh
7 8/4 007000h-007FFFh
6 8/4 006000h-006FFFh
5 8/4 005000h-005FFFh
4 8/4 004000h-004FFFh
3 8/4 003000h-003FFFh
2 8/4 002000h-002FFFh
1 8/4 001000h-001FFFh
0 8/4 000000h-000FFFh
Page 10
FLASH
10
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
Figure 3
Top Boot Block Device
Bank b = 28Mb
Block Block Size Address Range
(K-bytes/K-words) (x16)
55 64/32 1B8000h-1BFFFFh
54 64/32 1B0000h-1B7FFFh
53 64/32 1A8000h-1AFFFFh
52 64/32 1A0000h-1A7FFFh
51 64/32 198000h-19FFFFh
50 64/32 190000h-197FFFh
49 64/32 188000h-18FFFFh
48 64/32 180000h-187FFFh
47 64/32 178000h-17FFFFh
46 64/32 170000h-177FFFh
45 64/32 168000h-16FFFFh
44 64/32 160000h-167FFFh
43 64/32 158000h-15FFFFh
42 64/32 150000h-157FFFh
41 64/32 148000h-14FFFFh
40 64/32 140000h-147FFFh
39 64/32 138000h-13FFFFh
38 64/32 130000h-137FFFh
37 64/32 128000h-12FFFFh
36 64/32 120000h-127FFFh
35 64/32 118000h-11FFFFh
34 64/32 110000h-117FFFh
33 64/32 108000h-10FFFFh
32 64/32 100000h-107FFFh
31 64/32 0F8000h-0FFFFFh
30 64/32 0F0000h-0F7FFFh
29 64/32 0E8000h-0EFFFFh
28 64/32 0E0000h-0E7FFFh
27 64/32 0D8000h-0DFFFFh
26 64/32 0D0000h-0D7FFFh
25 64/32 0C8000h-0CFFFFh
24 64/32 0C0000h-0C7FFFh
23 64/32 0B8000h-0BFFFFh
22 64/32 0B0000h-0B7FFFh
21 64/32 0A8000h-0AFFFFh
20 64/32 0A0000h-0A7FFFh
19 64/32 098000h-09FFFFh
18 64/32 090000h-097FFFh
17 64/32 088000h-08FFFFh
16 64/32 080000h-087FFFh
15 64/32 078000h-07FFFFh
14 64/32 070000h-077FFFh
13 64/32 068000h-06FFFFh
12 64/32 060000h-067FFFh
11 64/32 058000h-05FFFFh
10 64/32 050000h-057FFFh
9 64/32 048000h-04FFFFh
8 64/32 040000h-047FFFh
7 64/32 038000h-03FFFFh
6 64/32 030000h-037FFFh
5 64/32 028000h-02FFFFh
4 64/32 020000h-027FFFh
3 64/32 018000h-01FFFFh
2 64/32 010000h-017FFFh
1 64/32 008000h-00FFFFh
0 64/32 000000h-007FFFh
Bank a = 4Mb
Block Block Size Address Range
(K-bytes/K-words) (x16)
70 8/4 1FF000h-1FFFFFh
69 8/4 1FE000h-1FEFFFh
68 8/4 1FD000h-1FDFFFh
67 8/4 1FC000h-1FCFFFh
66 8/4 1FB000h-1FBFFFh
65 8/4 1FA000h-1FAFFFh
64 8/4 1F9000h-1F9FFFh
63 8/4 1F8000h-1F8FFFh
62 64/32 1F0000h-1F7FFFh
61 64/32 1E8000h-1EFFFFh
60 64/32 1E0000h-1E7FFFh
59 64/32 1D8000h-1DFFFFh
58 64/32 1D0000h-1D7FFFh
57 64/32 1C8000h-1CFFFFh
56 64/32 1C0000h-1C7FFFh
Page 11
FLASH
11
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
FLASH MEMORY OPERATING MODES
COMMAND STATE MACHINE
Commands are issued to the command state machine (CSM) using standard microprocessor write timings. The CSM acts as an interface between external
microprocessors and the internal write state machine
(WSM). The available commands are listed in Table 4,
their definitions are given in Table 5 and their descriptions in Table 6. Program and erase algorithms are automated by the on-chip WSM. Table 7 shows the CSM
transition states. Once a valid PROGRAM/ERASE command is entered, the WSM executes the appropriate
algorithm, which generates the necessary timing signals to control the device internally. A command is
valid only if the exact sequence of WRITEs is completed.
After the WSM completes its task, the write state machine status (WSMS) bit (SR7) (see Table 9) is set to a
logic HIGH level (VIH), allowing the CSM to respond to
the full command set again.
OPERATIONS
Device operations are selected by entering a standard JEDEC 8-bit command code with conventional
microprocessor timings into an on-chip CSM through
I/O pins DQ0–DQ7. The number of bus cycles required
to activate a command is typically one or two. The first
operation is always a WRITE. Control pins F_CE# and
F_WE# must be at a logic LOW level (VIL), and F_OE#
and F_RP# must be at logic HIGH (VIH). The second
operation, when needed, can be a WRITE or a READ
depending upon the command. During a READ operation, control pins F_CE# and F_OE# must be at a logic
LOW level (VIL), and F_WE# and F_RP# must be at logic
HIGH (VIH).
Table 8 illustrates the bus operations for all the
modes: write, read, reset, standby, and output disable.
When the device is powered up, internal reset circuitry initializes the chip to a read array mode of operation. Changing the mode of operation requires that a
command code be entered into the CSM. For each one
of the two flash memory partitions, an on-chip status
register is available. These two registers allow the monitoring of the progress of various operations that can
take place on a memory bank. One of the two status
registers is interrogated by entering a READ STATUS
REGISTER command onto the CSM (cycle 1), specifying an address within the memory partition boundary,
and reading the register data on I/O pins DQ0–DQ7
(cycle 2). Status register bits SR0-SR7 correspond to
DQ0–DQ7 (see Table 9).
COMMAND DEFINITION
Once a specific command code has been entered,
the WSM executes an internal algorithm, generating
the necessary timing signals to program, erase, and
verify data. See Table 5 for the CSM command definitions and data for each of the bus cycles.
STATUS REGISTER
The status register allows the user to determine
whether the state of a PROGRAM/ERASE operation is
pending or complete. The status register is monitored
by toggling F_OE# and F_CE# and reading the resulting status code on I/O pins DQ0–DQ7. The high-order
I/Os (DQ8–DQ15) are set to 00h internally, so only the
Table 4
Command State Machine Codes For Device Mode Selection
COMMAND DQ0–DQ7 CODE ON DEVICE MODE
10h/40h Program setup/alternate program setup
20h Block erase setup
50h Clear status register
60h Protection configuration setup
70h Read status register
90h Read protection configuration register
98h Read query
B0 h Program/erase suspend
C0h Protection register program/lock
D0h Program/erase resume - erase confirm
FF h Read array
Page 12
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2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
low-order I/O pins (DQ0–DQ7) need to be interpreted.
Address lines select the status register pertinent to the
selected memory partition.
Register data is updated and latched on the rising
edge of F_OE# or F_CE#, whichever occurs first. The
latest falling edge of either of these two signals updates the latch within a given READ cycle. Latching the
data prevents errors from occurring if the register input
changes during a status register read.
The status register provides the internal state of the
WSM to the external microprocessor. During periods
when the WSM is active, the status register can be polled
to determine the WSM status. Table 9 defines the status register bits.
After monitoring the status register during a
PROGRAM/ERASE operation, the data appearing on
DQ0–DQ7 remains as status register data until a new
command is issued to the CSM. To return the device to
other modes of operation, a new command must be
issued to the CSM.
COMMAND STATE MACHINE OPERATIONS
The CSM decodes instructions for the commands
listed in Table 4. The 8-bit command code is input to
the device on DQ0–DQ7 (see Table 5 for command
definitions). During a PROGRAM or ERASE cycle, the
CSM informs the WSM that a PROGRAM or ERASE cycle
has been requested.
During a PROGRAM cycle, the WSM controls the
program sequences and the CSM responds to a PROGRAM SUSPEND command only.
During an ERASE cycle, the CSM responds to an
ERASE SUSPEND command only. When the WSM has
completed its task, the WSMS bit (SR7) is set to a logic
HIGH level and the CSM responds to the full command
set. The CSM stays in the current command state until
the microprocessor issues another command.
The WSM successfully initiates an ERASE or PROGRAM operation only when VPP is within its correct voltage range.
Table 5
Command Definitions
FIRST BUS CYCLE SECOND BUS CYCLE
COMMAND OPERATION ADDRESS DATA OPERATION ADDRESS DATA
READ ARRAY WRITE WA F Fh
READ PROTECTION CONFIGURATION REGISTER WRITE IA 90h READ I A ID
READ STATUS REGISTER WRITE BA 70h READ BA SRD
CLEAR STATUS REGISTER WRITE BA 50h
READ QUERY WRITE QA 98h READ QA QD
BLOCK ERASE SETUP WRITE BA 20h WRITE BA D0h
PROGRAM SETUP/ALTERNATE PROGRAM SETUP WRITE WA 40h/10h WRITE WA WD
PROGRAM/ERASE SUSPEND WRITE BA B0h
PROGRAM/ERASE RESUME - ERASE CONFIRM WRITE BA D0h
LOCK BLOCK WRITE BA 60h WRITE BA 01h
UNLOCK BLOCK WRITE BA 60h WRITE BA D0h
LOCK DOWN BLOCK WRITE BA 60h WRITE BA 2Fh
PROTECTION REGISTER PROGRAM WRITE PA C0h WRITE PA PD
PROTECTION REGISTER LOCK WRITE LPA C0h WRITE LPA FFFDh
NOTE: 1. WA: Word address of memory location to be written, or read
2. IA: Identification code address
3. BA: Address within the block
4. ID: Identification code data
5. SRD: Data read from the status register
6. QA: Query code address
7. QD: Query code data
8. WD: Data to be written at the location WA
9. PA: Protection register address
10. LPA: Lock protection register address
11. PD: Protection register data
Page 13
FLASH
13
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
Table 6
Command Descriptions
CODE DEVICE MODE BUS CYCLE DESCRIPTION
10h Alt. Program Setup First Operates the same as a PROGRAM SETUP command.
20h Erase Setup First Prepares the CSM for an ERASE CONFIRM command. If the next
command is not ERASE CONFIRM, the CSM sets both SR4 and SR5 of
the status register to a “1,” places the device into read status register
mode, and waits for another command.
40h Program Setup First A two-cycle command: The first cycle prepares for a PROGRAM
operation, the second cycle latches addresses and data and initiates
the WSM to execute the program algorithm. The Flash outputs status
register data on the falling edge of F_OE# or F_CE#, whichever
occurs first.
50h Clear Status First The WSM can set the program status (SR4), and erase status (SR5) bits
Register in the status register to “1,” but it cannot clear them to “0.” Issuing
this command clears those bits to “0.”
60h Protection First Prepares the CSM for changes to the block locking status. If the next
Configuration command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK
Setup DOWN, then the CSM sets both the program and erase status register
bits to indicate a command sequence error.
70h Read Status First Places the device into read status register mode. Reading the device
Register outputs the contents of the status register, regardless of the address
presented to the device. The device automatically enters this mode
after a PROGRAM or ERASE operation has been initiated.
90h Read Protection First Puts the device into the read protection configuration mode so that
Configuration reading the device outputs the manufacturer/device codes or block
lock status.
98h Read Query First Puts the device into the read query mode so that reading the device
outputs common Flash interface information.
B0h Program Suspend First Suspends the currently executing PROGRAM/ERASE operation. The
status register indicates when the operation has been successfully
Erase Suspend First suspended by setting either the program suspend (SR2) or erase
suspend (SR6) and the WSMS bit (SR7) to a “1” (ready). The WSM
continues to idle in the suspend state, regardless of the state of all
input control pins except F_RP#, which immediately shuts down the
WSM and the remainder of the chip if F_RP# is driven to VIL.
C0h Program Device First Writes a specific code into the device protection register.
Protection Register
Lock Device First Locks the device protection register; data can no longer be changed.
Protection register
(continued on the next page)
Page 14
FLASH
14
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
Table 6
Command Descriptions (continued)
CODE DEVICE MODE BUS CYCLE DESCRIPTION
D0h Erase Confirm First If the previous command was an ERASE SETUP command, then the
CSM closes the address and data latches, and it begins erasing the
block indicated on the address pins. During programming/erase, the
device responds only to the READ STATUS REGISTER, PROGRAM
SUSPEND, or ERASE SUSPEND commands and outputs status register
data on the falling edge of F_OE# or F_CE#, whichever occurs last.
Program/Erase First If a PROGRAM or ERASE operation was previously suspended, this
Resume command resumes the operation.
FFh Read Array First During the array mode, array data is output on the data bus.
01h Lock Block Second If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM latches the address and locks the block indicated on the
address bus.
2Fh Lock Down Second If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM latches the address and locks down the block indicated on
the address bus.
D0h Unlock Block Second If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM latches the address and unlocks the block indicated on the
address bus. If the block had been previously set to lock down, this
operation has no effect.
00h Invalid/Reserved Unassigned command that should not be used.
Page 15
FLASH
15
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
CLEAR STATUS REGISTER
The internal circuitry can set, but not clear, the block
lock status bit (SR1), the VPP status bit (SR3), the program status bit (SR4), and the erase status bit (SR5) of
the status register. The CLEAR STATUS REGISTER command (50h) allows the external microprocessor to clear
these status bits and synchronize to the internal operations. When the status bits are cleared, the device
returns to the read array mode.
READ OPERATIONS
The following READ operations are available: READ
ARRAY, READ PROTECTION CONFIGURATION REGISTER, READ QUERY and READ STATUS REGISTER.
READ ARRAY
The array is read by entering the command code
FFh on DQ0–DQ7. Control pins F_CE# and F_OE# must
be at a logic LOW level (VIL), and F_WE# and F_RP#
must be at a logic HIGH level (VIH) to read data from the
array. Data is available on DQ0–DQ15. Any valid address within any of the blocks selects that address and
allows data to be read from that address. Upon initial
power-up, the device defaults to the read array mode.
READ CHIP PROTECTION IDENTIFICATION DATA
The chip identification mode outputs three types
of information: the manufacturer/device identifier, the
block locking status, and the protection register. Two
bus cycles are required for this operation: the chip identification data is read by entering the command code
90h on DQ0–DQ7 to the bank containing address 00h
and the identification code address on the address
lines. Control pins F_CE# and F_OE# must be at a logic
LOW level (VIL), and F_WE# and F_RP# must be at a
logic HIGH level (VIH) to read data from the protection
configuration register. Data is available on DQ0–DQ15.
After data is read from the protection configuration
register, the READ ARRAY command, FFh, must be issued to the bank containing address 00h prior to issuing other commands. See Table 11 for further details.
READ QUERY
The read query mode outputs common Flash interface (CFI) data when the device is read (see Table 15).
Two bus cycles are required for this operation. It is
possible to access the query by writing the read query
command code 98h on DQ0–DQ7. Control pins F_CE#
and F_OE# must be at a logic LOW level (VIL), and F_WE#
and F_RP# must be at a logic HIGH level (VIH) to read
data from the query. The CFI data structure contains
information such as block size, density, command set,
and electrical specifications. To return to read array
mode, write the read array command code FFh on DQ0–
DQ7.
READ STATUS REGISTER
The status register is read by entering the command
code 70h on DQ0–DQ7. Two bus cycles are required for
this operation: one to enter the command code and a
second to read the status register. In a READ cycle, the
address is latched and register data is updated on the
falling edge of F_OE# or F_CE#, whichever occurs last.
Page 16
FLASH
16
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
Table 7
Command State Machine Transition Table
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(continued on next page)
Page 17
FLASH
17
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
Table 7
Command State Machine Transition Table (continued)
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(continued on next page)
Page 18
FLASH
18
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
Table 7
Command State Machine Transition Table (continued)
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(continued on next page)
Page 19
FLASH
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2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
Table 7
Command State Machine Transition Table
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h89
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h0D
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,emuserE/P
mrifnocBLU
h02
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putes
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margorP
putes
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Page 20
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2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
plished only by blocks; data at single address locations
within the array cannot be erased individually. The
block to be erased is selected by using any valid address within that block. Block erasure is initiated by a
command sequence to the CSM: BLOCK ERASE setup
(20h) followed by BLOCK ERASE CONFIRM (D0h) (see
Table 5). A two-command erase sequence protects
against accidental erasure of memory contents.
When the BLOCK ERASE CONFIRM command is
complete, the WSM automatically executes a sequence
of events to complete the block erasure. During this
sequence, the block is programmed with logic 0s, data
is verified, all bits in the block are erased, and finally
verification is performed to ensure that all bits are correctly erased. Monitoring of the ERASE operation is
possible through the status register (see the Status
Register section).
During the execution of an ERASE operation, the
ERASE SUSPEND command (B0h) can be entered to
direct the WSM to suspend the ERASE operation. Once
the WSM has reached the suspend state, it allows the
CSM to respond only to the READ ARRAY, READ STATUS REGISTER, READ QUERY, READ CHIP PROTECTION CONFIGURATION, PROGRAM SETUP, PROGRAM RESUME, ERASE RESUME and LOCK SETUP
(see the Block Locking section). During the ERASE SUSPEND operation, array data must be read from a block
other than the one being erased. To resume the ERASE
operation, an ERASE RESUME command (D0h) must
be issued to cause the CSM to clear the suspend state
previously set (see Figure 7). It is also possible that an
ERASE in any bank can be suspended and a WRITE to
another block in the same bank can be initiated. After
the completion of a WRITE, an ERASE can be resumed
by writing an ERASE RESUME command.
PROGRAMMING OPERATIONS
There are two CSM commands for programming:
PROGRAM SETUP and ALTERNATE PROGRAM SETUP
(see Table 4).
After the desired command code is entered (10h or
40h command code on DQ0–DQ7), the WSM takes over
and correctly sequences the device to complete the
PROGRAM operation. The WRITE operation may be
monitored through the status register (see the Status
Register section). During this time, the CSM only responds to a PROGRAM SUSPEND command until the
PROGRAM operation has been completed, after which
time all commands to the CSM become valid again.
The PROGRAM operation can be suspended by issuing
a PROGRAM SUSPEND command (B0h). Once the WSM
reaches the suspend state, it allows the CSM to respond only to READ ARRAY, READ STATUS REGISTER,
READ PROTECTION CONFIGURATION, READ QUERY,
PROGRAM SETUP, or PROGRAM RESUME. During the
PROGRAM SUSPEND operation, array data should be
read from an address other than the one being programmed. To resume the PROGRAM operation, a PROGRAM RESUME command (D0h) must be issued to
cause the CSM to clear the suspend state previously
set (see Figure 4 for programming operation and Figure
5 for program suspend and program resume).
Taking F_RP# to VIL during programming aborts the
PROGRAM operation.
ERASE OPERATIONS
An ERASE operation must be used to initialize all
bits in an array block to “1s.” After BLOCK ERASE confirm is issued, the CSM responds only to an ERASE
SUSPEND command until the WSM completes its task.
Block erasure inside the memory array sets all bits
within the address block to logic 1s. Erase is accom-
Table 8
Bus Operations
MODE F_RP# F_CE# F_OE# F_WE# ADDRESS DQ0–DQ15
Read (array, status registers, VIH VIL VIL VIH XDOUT
device identification register, or
query)
Standby VIH VIH X X X High-Z
Output Disable VIH VIH X X X High-Z
Reset VIL X X X X High-Z
Write VIH VIL VIH VIL XDIN
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2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
STATUS
BIT # STATUS REGISTER BIT DESCRIPTION
SR7 WRITE STATE MACHINE STATUS (WSMS) Check write state machine bit first to determine word
1 = Ready program or block erase completion, before checking
0 = Busy program or erase status bits.
SR6 ERASE SUSPEND STATUS (ESS) When ERASE SUSPEND is issued, WSM halts execution and
1 = BLOCK ERASE Suspended sets both WSMS and ESS bits to “1.” ESS bit remains set to
0 = BLOCK ERASE in “1” until an ERASE RESUME command is issued.
Progress/Completed
SR5 ERASE STATUS (ES) When this bit is set to “1,” WSM has applied the maximum
1 = Error in Block Erasure number of erase pulses to the block and is still unable to
0 = Successful BLOCK ERASE verify successful block erasure.
SR4 PROGRAM STATUS (PS) When this bit is set to “1,” WSM has attempted but failed to
1 = Error in PROGRAM program a word.
0 = Successful PROGRAM
SR3 VPP STATUS (VPPS) The VPP status bit does not provide continuous indication
1 = VPP Low Detect, Operation Abort of the VPP level. The WSM interrogates the VPP level only
0 = VPP = OK after the program or erase command sequences have been
entered and informs the system if VPP has not been switched
on. The VPP level is also checked before the PROGRAM/ERASE
operation is verified by the WSM. The MT28C3212P2NFL
device allows PROGRAM or ERASE at 0V, in which case SR3 is
held at “0.”
SR2 PROGRAM SUSPEND STATUS (PSS) When PROGRAM SUSPEND is issued, WSM halts execution
1 = PROGRAM Suspended and sets both WSM and PSS bits to “1.” PSS bit remains set to
0 = PROGRAM in Progress/Completed “1” until a PROGRAM RESUME command is issued.
SR1 BLOCK LOCK STATUS (BLS) If a PROGRAM or ERASE operation is attempted to one of
1 = PROGRAM/ERASE Attempted on a the locked blocks, this is set by the WSM. The operation
Locked Block; Operation Aborted specified is aborted, and the device is returned to read status
0 = No Operation to Locked Blocks mode.
SR0 RESERVED FOR FUTURE This bit is reserved for future.
ENHANCEMENT
Table 9
Status Register Bit Definition
WSMS ESS ES PS VPPS PSS BLS R
76543210
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2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
Figure 4
Automated Word Programming
Flowchart
NOTE: 1. Full status register check can be done after each word or after a sequence of words.
2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation
attempts.
BUS
OPERATION COMMAND COMMENTS
WRITE WRITE Data = 40h or 10h
PROGRAM Addr = Address of word to be
SETUP programmed
WRITE WRITE Data = Word to be
DATA programmed
Addr = Address of word to be
programmed
READ Status register data;
toggle OE# or CE# to update
status register.
Standby Check SR7
1 = Ready, 0 = Busy
Repeat for subsequent words.
Write FFh after the last word programming operation
to reset the device to read array mode.
BUS
OPERATION COMMAND COMMENTS
Standby Check SR1
1 = Detect locked block
Standby Check SR3
2
1 = Detect VPP low
Standby Check SR4
3
1 = Word program error
YES
NO
Full Status Register
Check (optional)
NO
YES
PROGRAM
SUSPEND?
SR7 = 1?
Issue PROGRAM SETUP
Command and
Word Address
Start
Word Program Passed
VPP Range Error
Word Program Failed
FULL STATUS REGISTER CHECK FLOW
Read Status Register
Bits
Issue Word Address
and Word Data
PROGRAM
SUSPEND Loop
1
YES
NO
SR1 = 0?
YES
NO
SR3 = 0?
YES
NO
SR4 = 0?
Word Program
Completed
Read Status Register
Bits
PROGRAM Attempted
on a Locked Block
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2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
Issue READ ARRAY
Command
PROGRAM
Complete
Finished
Reading
?
Issue PROGRAM
RESUME Command
YES
YES
NO
NO
SR2 = 1?
Start
PROGRAM Resumed
Read Status Register
Bits
Issue PROGRAM
SUSPEND Command
YES
NO
SR7 = 1?
Figure 5
PROGRAM SUSPEND/
PROGRAM RESUME Flowchart
BUS
OPERATION COMMAND COMMENTS
WRITE PROGRAM Data = B0h
SUSPEND
READ Status register data;
toggle OE# or CE# to update
status register.
Standby Check SR7
1 = Ready
Standby Check SR2
1 = Suspended
WRITE READ Data = FFh
MEMORY
READ Read data from block other
than that being programmed.
WRITE PROGRAM Data = D0h
RESUME
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2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
YES
NO
Full Status Register
Check (optional)
NO
YES
ERASE
SUSPEND?
SR 7 = 1?
Start
BLOCK ERASE Passed
VPP Range Error
BLOCK ERASE Failed
FULL STATUS REGISTER CHECK FLOW
Read Status Register
Bits
ERASE
SUSPEND Loop
1
YES
NO
SR1 = 0?
YES
NO
YES
NO
BLOCK ERASE
Completed
Read Status Register
Bits
ERASE Attempted
on a Locked Block
SR3 = 0?
SR5 = 0?
Issue ERASE SETUP
Command and
Block Address
Issue BLOCK ERASE
CONFIRM Command
and Block Address
Figure 6
BLOCK ERASE Flowchart
NOTE: 1. Full status register check can be done after each block or after a sequence of blocks.
2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full
status is checked.
BUS
OPERATION COMMAND COMMENTS
WRITE WRITE Data = 20h
ERASE Block Addr = Address
SETUP within block to be erased
WRITE ERASE Data = D0h
Block Addr = Address
within block to be erased
READ Status register data;
toggle OE# or CE# to
update status register.
Standby Check SR7
1 = Ready, 0 = Busy
Repeat for subsequent blocks.
Write FFh after the last BLOCK ERASE operation to
reset the device to read array mode.
BUS
OPERATION COMMAND COMMENTS
Standby Check SR1
1 = Detect locked block
Standby Check SR3
2
1 = Detect VPP block
Standby Check SR4 and SR5
1 = BLOCK ERASE
command error
Standby Check SR5
3
1 = BLOCK ERASE error
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2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
READ
PROGRAM
Issue READ ARRAY
Command
PROGRAM
Loop
ERASE
Complete
READ or
PROGRAM?
YES
NO
Issue ERASE
RESUME Command
READ or
PROGRAM
Complete?
YES
NO
SR6 = 1?
Start
ERASE Continued
Read Status Register
Bits
Issue ERASE
SUSPEND Command
2
(Note 1)
YES
NO
SR7 = 1?
Figure 7
ERASE SUSPEND/ERASE RESUME
Flowchart
NOTE: 1. See BLOCK ERASE Flowchart for complete erasure procedure.
2. See Word Programming Flowchart for complete programming procedure.
BUS
OPERATION COMMAND COMMENTS
WRITE ERASE Data = B0h
SUSPEND
READ Status register data;
toggle OE# or CE# to
update status register.
Standby Check SR7
1 = Ready
Standby Check SR6
1 = Suspended
WRITE READ Data = FFh
MEMORY
READ Read data from block
other than that being
erased.
WRITE ERASE Data = D0h
RESUME
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2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
READ-WHILE-WRITE/ERASE
CONCURRENCY
It is possible for the device to read from one bank
while erasing/writing to another bank. Once a bank
enters the WRITE/ERASE operation, the other bank
automatically enters read array mode. For example,
during a READ CONCURRENCY operation, if a PROGRAM/ERASE command is issued in bank a, then bank
a changes to the read status mode and bank b defaults
to the read array mode. The device reads from bank b if
the latched address resides in bank b (see Figure 8).
Similarly, if a PROGRAM/ERASE command is issued in
bank b, then bank b changes to read status mode and
bank a defaults to read array mode. When returning to
bank a, the device reads program/erase status if the
latched address resides in bank a. A correct bank address must be specified to read status register after
returning from concurrent read in the other bank.
When reading the CFI area, or the chip protection
register, the possible concurrent operations are reported in Figures 9a and 9b.
Figure 8
READ-While-WRITE Concurrency
Bank a
1 - Erasing/writing to bank a
2 - Erasing in bank a can be
suspended, and a WRITE to
another block in bank a
can be initiated.
3 - After the WRITE in that block
is complete, an ERASE can
be resumed by writing an
ERASE RESUME command.
1 - Reading bank a
Bank b
1 - Reading from bank b
1 - Erasing/writing to bank b
2 - Erasing in bank b can be
suspended, and a WRITE to
another block in bank b
can be initiated.
3 - After the WRITE in that block
is complete, an ERASE can
be resumed by writing an
ERASE RESUME command.
Figure 9a
Top Boot Block Device
Figure 9b
Bottom Boot Block Device
BANK a BANK b
Reading the READ Not Not
CFI or Chip Supported Supported
Protection
WRITE Not Not
Register
ERASE Supported Supported
BANK a BANK b
Reading the READ Not Supported
CFI or Chip Supported
Protection
WRITE Not Supported
Register
ERASE Supported
BLOCK LOCKING
The Flash memory of the MT28C3212P2FL or
MT28C3212P2NFL device provides a flexible locking
scheme which allows each block to be individually
locked or unlocked with no latency.
The device offers two-level protection for the blocks.
The first level allows software-only control of block locking (for data which needs to be changed frequently),
while the second level requires hardware interaction
before locking can be changed (code which does not
require frequent updates).
Control pins F_WP#, DQ0, and DQ1 define the state
of a block; for example, state [001] means F_WP# = 0,
DQ0 = 0 and DQ1 = 1.
Table 10 defines all of the possible locking states.
NOTE: All blocks are software-locked upon comple-
tion of the power-up sequence.
LOCKED STATE
After a power-up sequence completion, or after a
reset sequence, all blocks are locked (states [001] or
[101]). This means full protection from alteration. Any
PROGRAM or ERASE operations attempted on a locked
block will return an error on bit SR1 of the status register. The status of a locked block can be changed to
unlocked or lock down using the appropriate software
commands. Writing the lock command sequence, 60h
followed by 01h, can lock an unlocked block.
UNLOCKED STATE
Unlocked blocks (states [000], [100], [110]) can be
programmed or erased. All unlocked blocks return to
the locked state when the device is reset or powered
down. An unlocked block can be locked or locked down
using the appropriate software command sequence,
60h followed by D0h. (See Table 5.)
LOCKED DOWN STATE
Blocks locked down (state [011]) are protected from
PROGRAM and ERASE operations, but their protection
status cannot be changed using software commands
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2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
alone. A locked or unlocked block can be locked down
by writing the lock down command sequence, 60h followed by 2Fh. Locked down blocks revert to the locked
state when the device is reset or powered down.
The LOCK DOWN function is dependent on the
F_WP# input pin. When F_WP# = 0, blocks in lock down
[011] are protected from program, erase, and lock status changes. When F_WP# = 1, the LOCK DOWN function is disabled ([111]) and locked down blocks can be
individually unlocked by a software command to the
[110] state, where they can be erased and programmed.
These blocks can then be relocked [111] and unlocked
[110], as desired, as long as F_WP# remains HIGH.
When F_WP# goes LOW, blocks that were previously
locked down return to the lock down state [011] regard-
less of any changes made while F_WP# was HIGH. Device reset or power-down resets all locks, including
those in lock down, to the locked state (see Table 10).
READING A BLOCK’S LOCK STATUS
The lock status of every block can be read in the
read device identification mode. To enter this mode,
write 90h to the bank containing address 00h. Subsequent READs at block address +00002 will output the
lock status of that block. The lowest two output pins,
DQ0 and DQ1, represent the lock status. DQ0 indicates
the block lock/unlock status and is set by the LOCK
command and cleared by the UNLOCK command. It is
also automatically set when entering lock down. DQ1
indicates lock down status and is set by the LOCK
Table 10
Block Locking State Transition
ERASE/PROGRAM LOCK
F_WP# DQ1 DQ0 NAME ALLOWED LOCK UNLOCK DOWN
0 0 0 Unlocked Yes To [001] – To [011]
0 0 1 Locked (Default) No – To [000] To [011]
0 1 1 Lock Down No – – –
1 0 0 Unlocked Yes To [101] – To [111]
1 0 1 Locked No – To [100] To [111]
1 1 0 Lock Down Yes To [111] – To [111]
Disabled
1 1 1 Lock Down No – To [110] –
Disabled
ITEM ADDRESS DATA
Manufacturer Code (x16) 00000h 002Ch
Device Code 00001h
·
Top boot configuration 44A2h
·
Bottom boot configuration 44A3h
Block Lock Configuration
2
XX002h Lock
·
Block is unlocked DQ0 = 0
·
Block is locked DQ0 = 1
·
Block is locked down DQ1 = 1
Chip Protection Register Lock 80h PR Lock
Chip Protection Register 1 81h–84h Factory Data
Chip Protection Register 2 85h–88h User Data
NOTE: 1. Other locations within the configuration address space are reserved by
Micron for future use.
2. “XX” specifies the block address of lock configuration.
Table 11
Chip Protection Configuration Addressing
1
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2 MEG x 16 PAGE FLASH
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DOWN command. It can only be cleared by reset or
power-down, not by software. Table 10 shows the block
locking state transition scheme. The READ ARRAY command, FFh, must be issued to the bank containing address 00h prior to issuing other commands.
LOCKING OPERATIONS DURING ERASE
SUSPEND
Changes to block lock status can be performed during an ERASE SUSPEND by using the standard locking
command sequences to unlock, lock, or lock down. This
is useful in the case when another block needs to be
updated while an ERASE operation is in progress.
To change block locking during an ERASE operation, first write the ERASE SUSPEND command (B0h),
then check the status register until it indicates that the
ERASE operation has been suspended. Next, write the
desired lock command sequence to block lock, and the
lock status will be changed. After completing any desired LOCK, READ, or PROGRAM operations, resume
the ERASE operation with the ERASE RESUME command (D0h).
If a block is locked or locked down during an ERASE
SUSPEND on the same block, the locking status bits
are changed immediately. When the ERASE is resumed,
the ERASE operation completes.
A locking operation cannot be performed during a
PROGRAM SUSPEND.
STATUS REGISTER ERROR CHECKING
Using nested locking or program command sequences during ERASE SUSPEND can introduce ambiguity into status register results.
Following protection configuration setup (60h), an
invalid command produces a lock command error (SR4
and SR5 are set to “1”) in the status register. If a lock
command error occurs during an ERASE SUSPEND,
SR4 and SR5 are set to “1” and remain at “1” after the
ERASE SUSPEND command is issued. When the ERASE
is complete, any possible error during the ERASE cannot be detected via the status register because of the
previous locking command error.
A similar situation happens if an error occurs during
a program operation error nested within an ERASE
SUSPEND.
CHIP PROTECTION REGISTER
A 128-bit protection register can be used to fullfill
the security considerations in the system (preventing
device substitution).
The 128-bit security area is divided into two 64-bit
segments. The first 64 bits are programmed at the
manufacturing site with a unique 64-bit number. The
other segment is left blank for customers to program as
desired. (See Figure 10).
READING THE CHIP PROTECTION REGISTER
The chip protection register is read in the device
identification mode. To enter this mode, load the 90h
command to the bank containing address 00h. Once in
this mode, READ cycles from addresses shown in Table
11 retrieve the specified information. To return to the
read array mode, write the READ ARRAY command
(FFh). The read array command, FFh, must be issued to
the bank containing address 00h prior to issuing other
commands.
PAGE READ MODE
The initial portion of the page mode cycle is the
same as the asynchronous access cycle. Holding CE#
LOW and toggling addresses A0–A1 allows random access of other words in the page.
The page size can be customized at the factory to
four or eight words as required; but if no specification is
made, the normal size is four words.
ASYNCHRONOUS READ CYCLE
When accessing addresses in a random order or
when switching between pages, the access time is given
by tAA.
When F_CE# and F_OE# are LOW, the data is placed
on the data bus and the processor can read the data.
Figure 10
Protection Register Memory Map
4 Words
Factory-Programmed
4 Words
User-Programmed
PR Lock 0
88h
85h
84h
81h
80h
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2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
STANDBY MODE
Icc supply current is reduced by applying a logic
HIGH level on F_CE# and F_RP# to enter the standby
mode. In the standby mode, the outputs are placed in
High-Z. Applying a CMOS logic HIGH level on F_CE#
and F_RP# reduces the current to ICC2 (MAX). If the
device is deselected during an ERASE operation or during programming, the device continues to draw current until the operation is complete.
AUTOMATIC POWER SAVE MODE (APS)
Substantial power savings are realized during periods when the Flash array is not being read and the
device is in the active mode. During this time the device switches to the automatic power save (APS) mode.
When the device switches to this mode, ICC is reduced
to ICC2. The low level of power is maintained until another operation is initiated. In this mode, the I/O pins
retain the data from the last memory address read until a new address is read. This mode is entered automatically if no address or control pins toggle.
VPP/VCC PROGRAM AND ERASE
VOLTAGES
The MT28C3212P2FL Flash memory provides insystem programming and erase with VPP in the 0.9V–
2.2V range (VPP1). In addition to the flexible block locking, the VPP programming voltage can be held LOW for
absolute hardware write protection of all blocks in the
Flash device. When VPP is below VPPLK, any PROGRAM or
ERASE operation results in an error, prompting the corresponding status register bit (SR3) to be set.
The MT28C3212P2NFL Flash memory provides insystem programming and erase with VPP in the 0.0V–
2.2V range (VPP1).
VPP at 12V ±5% (VPP2) is supported for a maximum
of 100 cycles and 10 cumulative hours. The device
can withstand 100,000 WRITE/ERASE operations when
VPP = VCC.
During WRITE and ERASE operations, the WSM
monitors the VPP voltage level. WRITE/ERASE operations are allowed only when VPP is within the ranges
specified in Table 12.
When VCC is below VLKO or VPP is below VPPLK, any
WRITE/ERASE operation is prevented.
DEVICE RESET
To correctly reset the device, the RST# signal must
be asserted (RST# = VIL) for a minimum of tRP. After
reset, the device can be accessed for a READ operation
with a delayed access time of tRWH from the rising edge
of RST#. The circuitry used for generating the RST#
signal needs to be common with the rest of the system
reset to ensure that correct system initialization occurs.
Please refer to the timing diagram for further details.
POWER-UP SEQUENCE
The following power-up sequence must be observed
to properly initialize the device:
• RST# must be at VIL.
• Power on VCC/VCCQ (VCC VCCQ at all times).
• Wait 2µS after VCC reaches VCC (MIN).
• Take RST# from VIL to VIH.
• The RST# transition from VIL to VIH must be less
than 10µS.
Table 12
VPP Ranges (V)
IN-SYSTEM IN-FACTORY
DEVICE MIN MAX MIN MAX
MT28C3212P2FL 0.9 2.2 11.4 12.6
MT28C3212P2NFL 0.0 2.2 11.4 12.6
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2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
ABSOLUTE MAXIMUM RATINGS*
Voltage to Any Pin Except VCC and VPP
with Respect to VSS ............................ -0.5V to +2.45V
VPP Voltage (for BLOCK ERASE and PROGRAM
with Respect to VSS) ....................... -0.5V to +13.5V**
VCC and VCCQ Supply Voltage
with Respect to VSS ............................ -0.3V to +2.45V
Output Short Circuit Current............................... 100mA
Operating Temperature Range .............. -40oC to +85oC
Storage Temperature Range................. -55oC to +125oC
Soldering Cycle ........................................... 260oC for 10s
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
**Maximum DC voltage on VPP may overshoot to +13.5V
for periods <20ns.
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL MIN MAX UNITS NOTES
Operating temperature
t
A -40 +85
o
C
VCC supply voltage F_VCC, S_VCC 1.65 2.2 V
I/O supply voltage (VCC = 1.65V–1.95V) VCCQ 1.65 1.95 V 1
I/O supply voltage (VCC = 1.80V–2.20V) VCCQ 1.80 2.20 V 1
VPP voltage VPP1 0.9 2.2 V
(MT28C3212P2FL only)
VPP voltage VPP1 0.0 2.2 V
(MT28C3212P2NFL only)
VPP in-factory programming voltage VPP2 11.4 12.6 V 2
Data retention supply voltage S_VDR 1.0 – V
Block erase cycling – 100,000 Cycles
Figure 11
Output Load Circuit
I/O
14.5K
30pF
V
CC
V
SS
14.5K
FLASH ELECTRICAL SPECIFICATIONS
NOTE: 1. Use only one of the two I/O supply voltage ranges, 1.65V–1.95V or 1.80V–2.20V.
2. 12V VPP is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours.
Page 31
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2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
COMBINED DC CHARACTERISTICS
1
VCC = 1.65V–1.95V or
1.80V–2.20V
VCCQ = 1.65V–1.95V or
1.80V–2.20V
DESCRIPTION CONDITIONS SYMBOL MIN TYP MAX UNITS NOTES
Input low voltage VIL -0.4 – 0.4 V
Input high voltage VIH VCCQ - – VCCQ + V
0.4V 0.3V
Output low voltage VOL – – 0.10 V
IOL = 100µA
Output high voltage VOH VCCQ - – – V
IOH = 100µA 0.1V
VPP lock out voltage VPPLK – – 0.4 V
VPP during PROGRAM/ERASE VPP1 0.9 – 2.2 V
operations (MT28C3212P2FL only) VPP2 11.4 – 12.6 V 2
VPP during PROGRAM/ERASE VPP1 0.0 – 2.2 V
operations (MT28C3212P2NFL only) VPP2 11.4 – 12.6 V 2
VCC PROGRAM/ERASE lock voltage VLKO 1.0 – – V
Input leakage current IL ––1 mA
Output leakage current IOZ ––1 mA
F_VCC asynchronous ICC1 ––15mA
read current at 95ns
F_VCC page mode ICC2 ––5mA
read current at 35ns
F_VCC plus S_VCC standby current ICC3 –2560 mA
F_VCC program current ICC4+IPP3 ––55mA
F_VCC erase current ICC5+IPP4 ––65mA
F_VCC/S_VCC erase suspend current ICC6 ––60mA
F_VCC/S_VCC
program suspend ICC7 ––60mA
current
Read-while-write current ICC8 ––80mA
S_VCC read/write operating VIN = VIH or VIL ICC9 –1225mA3
supply current – page access chip enabled, IOL = 0
mode
NOTE: 1. All currents are in RMS unless otherwise noted.
2. 12V VPP is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours.
3. Operating current is a linear function of operating frequency and voltage. Operating current can be calculated using
the formula shown with operating frequency (f) expressed in MHz and operating voltage (V) in volts.
Example: When operating at 2 MHz at 2V, the device will draw a typical active current of 0.8*2* = 3.2mA in the page
access mode. This parameter is specified with the outputs disabled to avoid external loading effects. The user must
add current required to drive output capacitance expected in the actual system.
(continued on the next page)
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2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
COMBINED DC CHARACTERISTICS1 (continued)
VCC = 1.65V–1.95V or
1.80V–2.20V
VCCQ = 1.65V–1.95V or
1.80V–2.20V
DESCRIPTION CONDITIONS SYMBOL MIN TYP MAX UNITS NOTES
S_VCC read/write operating VIN = VIH or VIL ICC10 –38mA3
supply current – word access chip enabled, IOL = 0
mode
VPP read current VPP ≤ VCC IPP1 ––1 mA
VPP ³ VCC – – 200 mA
VPP standby current VPP ≤ VCC IPP2 ––1 mA
VPP ³ VCC – – 200 mA
VPP erase suspend current VPP = VPP1 IPP5 ––1 mA
VPP = VPP2 – – 200 mA
VPP program suspend current VPP = VPP1 IPP6 ––1 mA
VPP = VPP2 – – 200 mA
NOTE: 1. All currents are in RMS unless otherwise noted.
2. 12V VPP is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours.
3. Operating current is a linear function of operating frequency and voltage. Operating current can be calculated using
the formula shown with operating frequency (f) expressed in MHz and operating voltage (V) in volts.
Example: When operating at 2 MHz at 2V, the device will draw a typical active current of 0.8*2* = 3.2mA in the page
access mode. This parameter is specified with the outputs disabled to avoid external loading effects. The user must
add current required to drive output capacitance expected in the actual system.
Page 33
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33
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
FLASH READ CYCLE TIMING REQUIREMENT
VCC = 1.65V–1.95V
-10 -11
VCC = 1.65V–1.95V VCC = 1.65V–1.95V
PARAMETER SYMBOL MIN MAX MIN MAX UNITS
Address to output delay
t
AA 100 110 ns
CE# LOW to output delay
t
ACE 100 110 ns
Page address access
t
APA 35 45 ns
OE# LOW to output delay
t
AOE 30 30 ns
F_RP# HIGH to output delay
t
RWH 200 200 ns
F_RP# LOW pulse width
t
RP 125 125 ns
CE# or OE# HIGH to output High-Z
t
OD 25 25 ns
Output hold from address, CE# or OE# change
t
OH 0 0 ns
READ cycle time
t
RC 100 110 ns
FLASH READ CYCLE TIMING REQUIREMENT
VCC = 1.80V–2.20V
-10 -11
VCC = 1.80V–2.20V VCC = 1.80V–2.20V
PARAMETER SYMBOL MIN MAX MIN MAX UNITS
Address to output delay
t
AA 95 100 ns
CE# LOW to output delay
t
ACE 95 100 ns
Page address access
t
APA 35 45 ns
OE# LOW to output delay
t
AOE 30 30 ns
F_RP# HIGH to output delay
t
RWH 150 150 ns
F_RP# LOW pulse width
t
RP 100 100 ns
CE# or OE# HIGH to output High-Z
t
OD 25 25 ns
Output hold from address, CE# or OE# change
t
OH 0 0 ns
READ cycle time
t
RC 95 100 ns
Page 34
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34
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
FLASH WRITE CYCLE TIMING REQUIREMENTS
-10/-11
V
CC = 1.65V–1.95V or
1.80V–2.20V
PARAMETER SYMBOL MIN MAX UNITS
Reset HIGH recovery to WE# going LOW
t
RS 150 ns
CE# setup to WE# going LOW
t
CS 0 ns
Write pulse width
t
WP 50 ns
Data setup to WE# going HIGH
t
DS 50 ns
Address setup to WE# going HIGH
t
AS 50 ns
CE# hold from WE# HIGH
t
CH 0 ns
Data hold from WE# HIGH
t
DH 0 n s
Address hold from WE# HIGH
t
AH 9 n s
Write pulse width HIGH
t
WPH 30 ns
WP# setup to WE# going HIGH
t
RHS 200 ns
VPP setup to WE# going HIGH
t
VPS 200 ns
Write recovery before READ
t
WOS 50 ns
WP# hold from valid SRD
t
RHH 0 ns
VPP hold from valid SRD
t
VPH 0 ns
WE# HIGH to data valid
t
WB
t
AA+50 ns
FLASH ERASE AND PROGRAM CYCLE TIMING REQUIREMENTS
-10/-11
V
CC = 1.65V–1.95V or
1.80V–2.20V
PARAMETER TYP MAX UNITS
4KW parameter block program time 0.1 0.3 s
32KW parameter block program time 0.8 2.4 s
Word program time 8 185 µs
4KW parameter block erase time 1 4 s
32KW parameter block erase time 1.5 5 s
Program suspend latency 510µs
Erase suspend latency 520µs
Page 35
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2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
TWO-CYCLE PROGRAMMING/ERASE OPERATION
VALID ADDRESS VALID ADDRESS VALID ADDRESS
UNDEFINED
t
CH
t
DH
t
RHS
t
DS
A0–A20
OE#
CE#
WE#
V
PP
RP#
WP#
V
IH
V
IH
V
IL
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IPPLK
V
IL
V
IPPH
t
AS
t
AH
t
WPH
t
RS
t
WP
t
WOS
t
CS
t
WB
CMD
CMD/
DATA
DQ0–DQ15
V
OH
V
OL
t
RHH
t
VPS
t
VPPH
STATUS
High-Z
NOTE: 1. The WRITE cycles for the WORD PROGRAMMING command are followed by a READ ARRAY DATA cycle.
-10/-11
VCC = 1.65V–1.95V or
1.80V–2.20V
SYMBOL MIN MAX UNITS
WRITE TIMING PARAMETERS
-10/-11
VCC = 1.65V–1.95V or
1.80V–2.20V
SYMBOL MIN MAX UNITS
t
RS 150 ns
t
CS 0 ns
t
WP 50 ns
t
DS 50 ns
t
AS 50 ns
t
CH 0 ns
t
DH 0 ns
t
AH 9 ns
t
RHS 200 ns
t
VPS 200 ns
t
WOS 50 ns
t
RHH 0 ns
t
VPH 0 ns
t
WB
t
AA+50 ns
Page 36
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36
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
SINGLE ASYNCHRONOUS READ OPERATION
READ TIMING PARAMETERS
(VCC = 1.65V–1.95V)
-10 -11
VCC = 1.65V–1.95V VCC = 1.65V–1.95V
SYMBOL MIN MAX MIN MAX UNITS
t
AA 100 110 n s
t
AC E 100 110 n s
t
AO E 30 30 n s
t
RW H 200 200 n s
t
OD 25 25 n s
t
OH 0 0 ns
t
RC 100 110 n s
VALID ADDRESS
UNDEFINED
t
OD
t
AA
t
ACE
t
OH
A0–A20
OE#
CE#
WE#
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
RC
t
RWH
DQ0–DQ15
RP#
V
OH
V
OL
VALID OUTPUT
High-Z
t
AOE
READ TIMING PARAMETERS
(VCC = 1.80V–2.20V)
-10 -11
VCC = 1.80V–2.20V VCC = 1.80V–2.20V
SYMBOL MIN MAX MIN MAX UNITS
t
AA 95 100 ns
t
ACE 95 100 ns
t
AO E 30 30 n s
t
RW H 150 150 n s
t
OD 25 25 n s
t
OH 0 0 ns
t
RC 95 100 n s
Page 37
FLASH
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2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
ASYNCHRONOUS PAGE MODE READ OPERATION
VALID ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
UNDEFINED
t
OD
t
AA
t
ACE
t
OH
t
A
PA
t
AOE
t
RMH
A0–A1
F_OE#
F_CE#
F_WE#
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
VALID ADDRESS
A2–A20
V
IH
V
IL
F_RP#
V
IH
V
IL
DQ0–DQ15
V
OH
V
OL
High-Z
READ TIMING PARAMETERS
(VCC = 1.65V–1.95V)
-10 -11
VCC = 1.65V–1.95V VCC = 1.65V–1.95V
SYMBOL MIN MAX MIN MAX UNITS
t
AA 100 110 n s
t
AC E 100 110 n s
t
AP A 35 45 n s
t
AO E 30 30 n s
t
RW H 200 200 n s
t
OD 25 25 n s
t
OH 0 0 ns
READ TIMING PARAMETERS
(VCC = 1.80V–2.20V)
-10 -11
VCC = 1.80V–2.20V VCC = 1.80V–2.20V
SYMBOL MIN MAX MIN MAX UNITS
t
AA 95 100 ns
t
ACE 95 100 ns
t
AP A 35 45 n s
t
AO E 30 30 n s
t
RW H 150 150 n s
t
OD 25 25 n s
t
OH 0 0 ns
Page 38
FLASH
38
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
RESET OPERATION
F_OE#
DQ0–DQ15
V
IH
V
IL
F_RST#
V
IH
V
IL
F_CE#
V
IH
V
IL
V
OH
V
OL
t
RWH
t
RP
READ TIMING PARAMETERS
(VCC = 1.65V–1.95V)
-10 -11
VCC = 1.65V–1.95V VCC = 1.65V–1.95V
SYMBOL MIN MAX MIN MAX UNITS
t
RW H 200 200 n s
t
RP 125 125 n s
READ TIMING PARAMETERS
(VCC = 1.80V–2.20V)
-10 -11
VCC = 1.80V–2.20V VCC = 1.80V–2.20V
SYMBOL MIN MAX MIN MAX UNITS
t
RW H 150 150 n s
t
RP 100 100 n s
Page 39
FLASH
39
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
Table 15
CFI
OFFSET DATA DESCRIPTION
00 2Ch Manufacturer Code
01 A2h Top Boot Block Device Code
A3h Bottom Boot Block Device Code
02–0F reserved Reserved
10, 11 0051,0052 “QR”
12 0059 “Y”
13, 14 0003, 0000 Primary OEM Command Set
15, 16 0039, 0000 Address for Primary Extended Table
17, 18 0000, 0000 Alternate OEM Command Set
19, 1A 0000, 0000 Address for OEM Extended Table
1B 0017 VCC MIN for Erase/Write; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD
1C 0022 VCC MAX for Erase/Write; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD
1D 00B4 VPP MIN for Erase/Write; Bit7–Bit4 Volts in Hex; Bit3–Bit0 100mV in BCD
1E 00C6 VPP MAX for Erase/Write; Bit7–Bit4 Volts in Hex; Bit3–Bit0 100mV in BCD
1F 0003 Typical timeout for single byte/word program, 2n µs, 0000 = not supported
20 0000 Typical timeout for maximum size multiple byte/word program, 2n µs, 0000 = not
supported
21 0009 Typical timeout for individual block erase, 2n ms, 0000 = not supported
22 0000 Typical timeout for full chip erase, 2n ms, 0000 = not supported
23 000C Maximum timeout for single byte/word program, 2n µs, 0000 = not supported
24 0000 Maximum timeout for maximum size multiple byte/word program, 2n µs, 0000 = not
supported
25 0003 Maximum timeout for individual block erase, 2n ms, 0000 = not supported
26 0000 Maximum timeout for full chip erase, 2n ms, 0000 = not supported
27 0016 Device size, 2n bytes
28 0001 Bus Interface x8 = 0, x16 = 1, x8/x16 = 2
29 0000 Flash device interface description 0000 = async
2A, 2B 0000, 0000 Maximum number of bytes in multi-byte program or page, 2
n
2C 0003 Number of erase block regions within device (4K words and 32K words)
2D, 2E 0037, 0000 Top boot block device erase block region information 1, 8 blocks …
0007, 0000 Bottom boot block device erase block region information 1, 8 blocks …
2F, 30 0000, 0001 Top boot block device ...of 8KB
0020, 0000 Bottom boot block device ...of 8KB
31, 32 0006, 0000 7 blocks of …
33, 34 0000, 0001 ……64KB
35, 36 0007, 0000 Top boot block device 56 blocks of
0037, 0000 Bottom boot block device 56 blocks of
(continued on the next page)
Page 40
FLASH
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2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
Table 15
CFI (continued)
OFFSET DATA DESCRIPTION
37, 38 0020, 0000 Top boot block device……64KB
0000, 0001 Bottom boot block device……64KB
39, 3A 0050, 0052 “PR”
3B 0049 “I”
3C 0030 Major version number, ASCII
3D 0031 Minor Version Number, ASCII
3E 00E6 Optional Feature and Command Support
3F 0002 Bit 0 Chip erase supported no = 0
40 0000 Bit 1 Suspend erase supported = yes = 1
41 0000 Bit 2 Suspend program supported = yes = 1
Bit 3 Chip lock/unlock supported = no = 0
Bit 4 Queued erase supported = no = 0
Bit 5 Instant individual block locking supported = yes = 1
Bit 6 Protection bits supported = yes = 1
Bit 7 Page mode read supported = yes = 1
Bit 8 Synchronous read supported = yes = 1
Bit 9 Simultaneous operation supported = yes = 1
42 0001 Program supported after erase suspend = yes
43, 44 0003, 0000 Bit 0 Block Lock Status active = yes; Bit 1 Block Lock Down active = yes
45 0018 VCC supply optimum; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD
46 00C0 VPP supply optimum; Bit7–Bit4 Volts in Hex; Bit3–Bit0 100mV in BCD
47 0001 Number of protection register fields in JEDEC ID space
48, 49 0080, 0000 Lock bytes LOW address, lock bytes HIGH address
4A, 4B 0003, 0003 2n factory programmed bytes, 2n user programmable bytes
4C 0002 Background Operation
0000 = Not used
0001 = 4% block split
0002 = 12% block split
0003 = 25% block split
0004 = 50% block split
4D 0000 Burst Mode Type
0000 = No burst mode
00x1 = 4 words max
00x2 = 8 words max
00x3 = 16 words max
001x = Linear burst, and/or
002x = Interleaved burst, and/or
004x = Continuous burst
4E 0002 Page Mode Type
0000 = No page mode
0001 = 4-word page
0002 = 8-word page
0003 = 16-word page
0004 = 32-word page
4F 0002 SRAM density, 2Mb (128K x 16)
Page 41
SRAM
41
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
SRAM OPERATING MODES
SRAM READ ARRAY
The operational state of the SRAM is determined by
S_CE1#, S_CE2, S_WE#, S_OE#, S_UB#, and S_LB#, as
indicated in the Truth Table. To perform an SRAM
READ operation, S_CE1#, and S_OE#, must be at VIL,
and S_CE2 and S_WE# must be at VIH. When in this
state, S_UB# and S_LB# control whether the lower byte
is read (S_UB# VIH, S_LB# VIL), the upper byte is read
(S_UB# VIL, S_LB# VIH), both upper and lower bytes are
read (S_UB# VIL, S_LB# VIL), or neither are read (S_UB#
VIH, S_LB# VIH) and the device is in a standby state.
While performing an SRAM READ operation, current consumption may be reduced by reading within a
16-word page. This is done by holding S_CE1# and
SRAM FUNCTIONAL BLOCK DIAGRAM
DQ0–DQ7
WORD
ADDRESS
DECODE
LOGIC
PAGE
ADDRESS
DECODE
LOGIC
CONTROL
LOGIC
8K-PAGE
x16 WORD
x16 BIT
RAM ARRAY
WORD
MUX
DQ8–DQ15
INPUT/
OUTPUT
MUX
AND
BUFFERS
S_CE1#
A4–A16
A0–A3
S_OE#
S_UB#
S_LB#
S_CE2
S_WE#
S_OE# at VIL, S_WE# and S_CE2 at VIH, and toggling
addresses A0-A3. S_UB# and S_LB# control the data
width as described above.
SRAM WRITE ARRAY
In order to perform an SRAM WRITE operation,
S_CE1# and S_WE# must be at VIL, and S_CE2 and
S_OE# must be at VIH. When in this state, S_UB# and
S_LB# control whether the lower byte is written (S_UB#
VIH, S_LB# VIL), the upper byte is written (S_UB# VIL,
S_LB# VIH), both upper and lower bytes are written
(S_UB# VIL, S_LB# VIL), or neither are written (S_UB#
VIH, S_LB# VIH) and the device is in a standby state.
Page 42
SRAM
42
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
TIMING TEST CONDITIONS
Input pulse levels .................... 0.1V VCC to 0.9V VCC
Input rise and fall times .................................... 5ns
Input timing reference levels ......................... 0.5V
Output timing reference levels ..................... 0.5V
Operating Temperature ............... -40oC to +85oC
SRAM READ CYCLE TIMING
-10/-11
VCC = 1.65V–1.95V VCC = 1.80V–2.20V
DESCRIPTION SYMBOL MIN MAX MIN MAX UNITS
Read cycle time
t
RC 100 85 ns
Address access time
t
AA 100 85 ns
Chip enable to valid output
t
CO 100 85 ns
Output enable to valid output
t
OE 35 35 ns
Byte select to valid output
t
LB, tUB 100 85 ns
Chip enable to Low-Z output
t
LZ 0 0 ns
Output enable to Low-Z output
t
OLZ 0 0 ns
Byte select to Low-Z output
t
LBZ, tUBZ 0 0 ns
Chip enable to High-Z output
t
HZ 0 15 0 15 ns
Output disable to High-Z output
t
OHZ 0 15 0 15 ns
Byte select disable to High-Z output
t
LBHZ, tUBHZ 0 15 0 15 ns
Output hold from address change
t
OH 5 5 ns
SRAM WRITE CYCLE TIMING
-10/-11
VCC = 1.65V–1.95V VCC = 1.80V–2.20V
DESCRIPTION SYMBOL MIN MAX MIN MAX UNITS
Write cycle time
t
WC 100 85 ns
Chip enable to end of write
t
CW 100 85 ns
Address valid to end of write
t
AW 100 85 ns
Byte select to end of write
t
LBW, tUBW 100 85 ns
Address setup time
t
AS 0 0 ns
Write pulse width
t
WP 50 50 ns
Write recovery time
t
WR 0 0 ns
Write to High-Z output
t
WHZ 0 15 0 15 ns
Data to write time overlap
t
DW 50 50 ns
Data hold from write time
t
DH 0 0 ns
End write to Low-Z output
t
OW 0 0 ns
Page 43
SRAM
43
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
DON’T CARE
ADDRESS
S_CE1#
S_CE2
S_OE#
S_LB#, S_UB#
DATA-OUT
t
RC
t
AA
t
HZ (1, 2)
t
CO
t
LBLZ, tUBLZ
t
LBHZ, tUBHZ
DATA VALID
High-Z
t
OE
t
LZ(2)
t
OLZ
t
OHZ (1)
t
LB, tUB
READ CYCLE 1
(S_CE1# = S_OE# = VIL; S_CE2, S_WE# = VIH)
ADDRESS
DATA-OUT
t
RC
t
AA
t
OH
PREVIOUS
DATA VALID
DATA VALID
READ CYCLE 2
(S_WE# = VIH)
READ TIMING PARAMETERS
-10/-11
VCC = 1.65V–1.95V VCC = 1.80V–2.20V
SYMBOL MIN MAX MIN MAX UNITS
t
RC 100 85 n s
t
AA 100 85 n s
t
CO 100 85 n s
t
OE 35 35 n s
t
LB, tUB 100 85 ns
t
LZ 0 0 ns
-10/-11
VCC = 1.65V–1.95V VCC = 1.80V–2.20V
SYMBOL MIN MAX MIN MAX UNITS
t
OLZ 0 0 ns
t
HZ 0 15 0 15 ns
t
OHZ 0 15 0 15 ns
t
LBHZ, tUBHZ 0 15 0 15 ns
t
OH 5 5 ns
Page 44
SRAM
44
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
WRITE CYCLE
(S_WE# CONTROL)
DON’T CARE
ADDRESS
S_CE1#
S_CE2
DATA-OUT
t
WC
t
AW
t
WR
t
CW
t
WHZ
t
OW
High-Z
S_LB#, S_UB#
t
LBW, tUBW
S_WE#
DATA-IN
t
AS
t
WP
t
DH
t
DW
DATA VALID
High-Z
WRITE TIMING PARAMETERS
-10/-11
VCC = 1.65V–1.95V VCC = 1.80V–2.20V
SYMBOL MIN MAX MIN MAX UNITS
t
WC 100 85 n s
t
CW 100 85 n s
t
AW 100 85 n s
t
LBW, tUBW 100 85 ns
t
AS 0 0 ns
t
WP 50 50 n s
-10/-11
VCC = 1.65V–1.95V VCC = 1.80V–2.20V
SYMBOL MIN MAX MIN MAX UNITS
t
WR 0 0 ns
t
WHZ 0 15 0 15 ns
t
DW 50 50 n s
t
DH 0 0 ns
t
OW 0 0 ns
Page 45
SRAM
45
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
WRITE CYCLE 2
(S_CE1# CONTROL)
DON’T CARE
ADDRESS
S_CE1#
DATA-OUT
t
WC
t
AW
t
WR
t
CW
t
WHZ
t
LZ
High-Z
S_LB#, S_UB#
S_WE#
DATA-IN
t
AS
t
WP
t
LBW, tUBW
t
DH
t
DW
DATA VALID
WRITE TIMING PARAMETERS
-10/-11
VCC = 1.65V–1.95V VCC = 1.80V–2.20V
SYMBOL MIN MAX MIN MAX UNITS
t
WC 100 85 n s
t
CW 100 85 n s
t
AW 100 85 n s
t
LBW, tUBW 100 85 ns
t
AS 0 0 ns
t
WP 50 50 n s
-10/-11
VCC = 1.65V–1.95V VCC = 1.80V–2.20V
SYMBOL MIN MAX MIN MAX UNITS
t
WR 0 0 ns
t
WHZ 0 15 0 15 ns
t
DW 50 50 n s
t
DH 0 0 ns
t
OW 0 0 ns
Page 46
46
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
66-BALL FBGA
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 36% Pb, 2%Ag
SOLDER BALL PAD: Ø .27mm
MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE: PLASTIC LAMINATE
1.40 MAX
0.80
(TYP)
8.80
0.80
(TYP)
8.00 ±0.10
12.00 ±0.10
4.40
±0.05 6.00 ±0.05
66X Ø 0.35
BALL A12
BALL A1
BALL A1
BALL #1 ID
5.60
2.80 ±0.05
4.00 ±0.05
0.10
1.05 ±0.075
C
C
SEATING PLANE
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PREREFLOW DIAMETER IS Ø 0.33
C
L
C
L
NOTE: 1. All dimensions in millimeters
MAX
or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.27mm per side.
DATA SHEET DESIGNATION
This data sheet contains minimum and maximum limits specified over the complete power supply and
temperature range for production devices. Although considered final, these specifications are subject to change,
as further product development and data characterization sometimes occur.
Page 47
47
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
REVISION HISTORY
Rev. 2, Pub. 4/02 ................................................................................................................................................................ 4/02
• Updated the chip protection mode and register information.
• Updated the block locking information.
• Removed the tCBPH parameter.
Rev. 2, Pub. 6/01 ................................................................................................................................................................ 6/01
• Data sheet designation change (removed “Advance”)
Initial published release, Rev. 1, Advance ................................................................................................................... 5/01
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