MSU2032L16 , low working voltage 16 MHz ROM less MCU
MSU2032C16 , 16 MHz ROM less MCU
MSU2032C25 , 25 MHz ROM less MCU
MSU2032C40 , 40 MHz ROM less MCU
MSU2052L16 , low working voltage 16 MHz 4 KB internal ROM MCU
MSU2052C16 , 16 MHz 4 KB internal ROM MCU
MSU2052C25 , 25 MHz 4 KB internal ROM MCU
MSU2052C40 , 40 MHz 4 KB internal ROM MCU
Description
The MVI MSU2052 series product is an 8 - bit
single chip microcontroller . It provides hardware
features and a powerful instruction set, necessary to make it a versatile and cost effective
controller for those applications demand up to
32 I/O pins or need up to 64 K byte external
memory either for program or for data or mixed.
A serial input / output port is provided for I/O
expansion, Inter - processor communications,
and full duplex UART.
Ordering Information
MSU2032ihhk
MSU2052ihh - yyyk
i: process identifier {L, C}.
hh: working clock in MHz {16, 25, 40}.
yyy: production code {001, ..., 999}
k: package type postfix {as below table}.
Features
MSU2052/U2032
Working voltage : L series at 2.7V through 4.5V
while S & C series at 4.5 V through 5.5 V
General 80C51 family compatible
64 K byte External Memory Space
8 K byte ROM
256 byte data RAM
Three 16 bit Timers/Counters
Four 8-bit I/O ports
Full duplex serial channel
Bit operation instructions
Page free jumps
8 - bit Unsigned Division
8 - bit Unsigned Multiply
BCD arithmatic
Direct Addressing
Indirect Addressing
Nested Interrupt
Two priority level interrupt
A serial I/O port
Power save modes:
Idle mode and Power down mode
Working at 16/25/40 MHz Clock
Pin/Pad
Pa ck age
Postfi x
dice
blank
40 L PD IP
P
44 L PL C C
J
44 L PQ F P
Q
44 L LQFP
U
Specifications subject to change without notice, contact your sales representatives for the most recent information.
Rev. 1.0 February 1998
Con figura tion
page 18
pa ge 2
pa ge 2
pa ge 2
pa ge 2
Di me ns i on
page 18
page 14
page 15
page 16
page 17
L ogo S i z e at
Top M a r ki ng
-
5.0 x 4.2 mm
4.5 x 3.8 mm
2.8 x 2.4 mm
2.8 x 2.4 mm
Cro ss Referen ce
M.V.I.
W.B.
Philip s
L.G.
Intel
CCL . it ri
Atmel
1
MSU2052
W78C52
80C52
GMS80C502
80C52
CIC80520
AT80 C52
MSU2032
W78C32
80C32
GMS80C302
80C32
- - - - AT8 0C32
Page 2
MOSEL VITELIC
Pin Configurations
P 1.4
P 1.3
P 1.2
T2EX/P 1.1
6 5 4 3 2 1 44 43 42 41 40
7
P 1.5
8
P 1.6
P 1.7
9
MSU2032ihhJ,
10
RES
RXD/P 3.0
NC
TXD/P 3.1
#INT0/P 3.2
#INT1/P 3.3
T0/P 3.4
T1/P 3.5
MSU2052ihh-
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
#RD/P 3.7
#WR/P 3.6
44L PLCC
(Top View)
XTAL2
XTAL1
T2/P 1.0NCVDD
yyyJ
NC
VSS
AD0/P 0.0
A8/P 2.0
A9/P 2.1
AD1/P 0.1
AD2/P 0.2
A10/P 2.2
A11/P 2.3
AD3/P 0.3
39
38
37
36
35
34
33
32
31
30
29
A12/P 2.4
AD4/P 0.4
AD5/P 0.5
AD6/P 0.6
AD7/P 0.7
#EA
NC
ALE
#PSEN
A15/P 2.7
A14/P 2.6
A13/P 2.5
P 1.5
P 1.6
P 1.7
RES
RXD/P 3.0
TXD/P 3.1
#INT0/P 3.2
#INT1/P 3.3
T0/P 3.4
T1/P 3.5
NC
MSU2052/U2032
P 1.4
P 1.3
P 1.2
T2EX/P 1.1
T2/P 1.0NCVDD
44 43 42 41 40 41 40 39 38 37 34
1
2
3
4
MSU2032ihhQ,
5
6
7
8
9
10
11
MSU2052ihh-
yyyQ
44L PQFP
(Top View)
12 13 14 15 16 17 18 19 20 21 22
VSS
XTAL2
XTAL1
#RD/P 3.7
#WR/P 3.6
NC
AD0/P 0.0
A8/P 2.0
A9/P 2.1
AD1/P 0.1
AD2/P 0.2
A10/P 2.2
A11/P 2.3
AD3/P 0.3
33
32
31
30
29
28
27
26
25
24
23
A12/P 2.4
AD4/P 0.4
AD5/P 0.5
AD6/P 0.6
AD7/P 0.7
#EA
NC
ALE
#PSEN
A15/P 2.7
A14/P 2.6
A13/P 2.5
T2EX/P1.0
T2/P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RES
RXD/P3.0
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
#WR/P3.6
#RD/P3.7
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
40L PDIP
9
(Top View)
10
11
12
13
14
15
16
17
18
19
20
VDD
40
AD0/P0.0
39
AD1/P0.1
38
MSU2032ihhP, MSU2052ihh-
AD2/P0.2
37
AD3/P0.3
36
AD4/P0.4
35
AD5/P0.5
34
33
32
31
30
29
28
27
26
25
yyyP
24
23
22
21
AD6/P0.6
AD7/P0.7
#EA
ALE
#PSEN
A15/P2.7
A14/P2.6
A13/P2.5
A12/P2.4
A11/P2.3
A10/P2.2
A9/P2.1
A8/P2.0
RXD/P 3.0
TXD/P 3.1
#INT0/P 3.2
#INT1/P 3.3
T0/P 3.4
T1/P 3.5
P 1.5
P 1.6
P 1.7
RES
NC
P 1.4
P 1.3
P 1.2
T2EX/P 1.1
T2/P 1.0NCVDD
44 43 42 41 40 41 40 39 38 37 34
1
2
3
4
MSU2032ihhU,
5
6
7
8
9
10
11
MSU2052ihh-
yyyU
44L LQFP
(Top View)
12 13 14 15 16 17 18 19 20 21 22
VSS
XTAL2
XTAL1
#RD/P 3.7
#WR/P 3.6
NC
AD0/P 0.0
A8/P 2.0
A9/P 2.1
AD1/P 0.1
AD2/P 0.2
A10/P 2.2
A11/P 2.3
AD3/P 0.3
33
32
31
30
29
28
27
26
25
24
23
A12/P 2.4
AD4/P 0.4
AD5/P 0.5
AD6/P 0.6
AD7/P 0.7
#EA
NC
ALE
#PSEN
A15/P 2.7
A14/P 2.6
A13/P 2.5
Rev. 1.0 February 1998
2
Page 3
MOSEL VITELIC
Block Diagram
Timer 2
RES
Vdd
Vss
Timer 1Timer 0
Reset
Circuit
Power
Circuit
Interrupt
Circuit
to pertinent blocks
to whole chip
to pertinent blocks
Stack
Pointer
ALU
Decoder &
Register
Buffer1Buffer2
Acc
256 bytes
RAM
MSU2052/U2032
8K bytes
ROM
Register
Buffer
DPTR
PC
Increamenter
XTAL2
XTAL1
#EA
#PSEN
ALE
Timming
Generator
Instruction
Register
to whole system
Port 3
Latch
Port 3
Driver
PSW
Port 1
Latch
Port 1
Driver
Port 2
Latch
Port 2
Driver
Program
Counter
Port 0
Latch
Port 0
Driver
8888
Rev. 1.0 February 1998
3
Page 4
MOSEL VITELIC
Pin Descriptions
Dice
40 PDIP
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pad#
39
40
41
42
43
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15~17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37,38
44 LQFP
Pin#
40
41
42
43
44
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
29
30
31
32
33
34
35
36
37
38
44 PQFP
Pin#
40
41
42
43
44
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
29
30
31
32
33
34
35
36
37
38
44 PLCC
Pin#
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
21
22
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
42
43
44
Symbol
T2EX/P1.0
T2/P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RES
RXD/P3.0
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
#WR/P3.6
#RD/P3.7
XTAL2
XTAL1
VSS
A8/P2.0
A9/P2.1
A10/P2.2
A11/P2.3
A12/P2.4
A13/P2.5
A14/P2.6
A15/P2.7
#PSEN
ALE
#EA
AD7/P0.7
AD6/P0.6
AD5/P0.5
AD4/P0.4
AD3/P0.3
AD2/P0.2
AD1/P0.1
AD0/P0.0
VDD
Active
L/L/-
L/L/-
L
H
L
I/O
Names
i/o
bit 0 of Port 1 & timer 2
i/o
bit 1 of Port 1 & timer control
i/o
bit 2 of Port 1
i/o
bit 3 of Port 1
i/o
bit 4 of Port 1
i/o
bit 5 of Port 1
i/o
bit 6 of Port 1
i/o
bit 7 of Port 1
i
Reset
i/o
bit 0 of Port 3 & Receive data
i/o
bit 1 of Port 3 & Transmit data
i/o
bit 2 of Port 3 & low true Interrupt 0
i/o
bit 3 of Port 3 & low true Interrupt 1
i/o
bit 4 of Port 3 & Timer 0
i/o
bit 5 of Port 3 & Timer 1
i/o
bit 6 of Port 3 & Write (low enable)
i/o
bit 7 of Port 3 & Read (low enable)
o
Crystal out
i
Crystal in
Sink Voltage, Ground
i/o
bit 0 of Port 2 & Address 8
i/o
bit 1 of Port 2 & Address 9
i/o
bit 2 of Port 2 & Address 10
i/o
bit 3 of Port 2 & Address 11
i/o
bit 4 of Port 2 & Address 12
i/o
bit 5 of Port 2 & Address 13
i/o
bit 6 of Port 2 & Address 14
i/o
bit 7 of Port 2 & Address 15
o
Program store enable (low enable)
o
Address latch enable
i
External access first 8 KB memory
i/o
bit 7 of Port 0 & Address or Data 7
i/o
bit 6 of Port 0 & Address or Data 6
i/o
bit 5 of Port 0 & Address or Data 5
i/o
bit 4 of Port 0 & Address or Data 4
i/o
bit 3 of Port 0 & Address or Data 3
i/o
bit 2 of Port 0 & Address or Data 2
i/o
bit 1 of Port 0 & Address or Data 1
i/o
bit 0 of Port 0 & Address or Data 0
Drive Voltage, +3 Vcc (or +5 Vcc)
MSU2052/U2032
Rev. 1.0 February 1998
4
Page 5
MOSEL VITELIC
Pin Descriptions
Vss
Circuit ground potential.
VDD
+3V (or +5 V) power supply during operation.
PORT 0
Port 0 is an 8-bit open drain bidirectional I/O port.
It is also the multiplexed low-order address and data
bus when using external memory.
It also contains the timer 2 & its control pins.
PORT 1
Port 1 is an 8-bit quasi-bidirectional I/O port with
internal pull-up resistance.
PORT 2
Port 2 is an 8-bit quasi-bidirectional I/O port with
internal pull-up resistance. It also emit the high-order
address byte when accessing external memory.
PORT 3
Port 3 is an 8-bit quasi-bidirectinal I/O port with internal
pull-up resistance. It also contains the interrupt, timer,
serial port and #RD as well as #WR pins that are used
by various options. The output latch corresponding to a
secondary function must be programmed to one (1) for
that function to operate. The secondary functions are
assigned to the pins of port 3, as follows:
- RXD/data (P3.0). Serial port's transmitter data output
(asynchronous) or data input/output (asynchronous).
- TXD/clock (P3.1). Serial port's transmitter data
output (asynchronous) or data output (asynchronous).
- #INT0 (P3.2). Interrupt 0 input or gate control input
for counter 0.
- #INT1 (P3.3). Interrupt 1 input or gate control input
for counter 1.
- T0 (P3.4). Input to counter 0.
- T1 (P3.4). Input to counter 1.
- #WR (P3.6). The write control signal latches the data
byte from Port 0 into the External Data Memory.
- #RD (P3.7). The read control signal enables External
Data Memory to Port 0.
RES
A high on this pin for two machine cycles (24 clocks)
while the oscillator is running, resets the device. The
data in RAM is preserved when reset signals - reset
does not clear the data in RAM.
ALE
Provides Address Latch Enable output used for latching
the address into external memory during normal
operation.
#PSEN
The Program Store Enable output is a control signal
that enables the external Program Memory to the bus
during normal fetch operations.
MSU2052/U2032
#EA
When held at a TTL high level, the MSU2052 executes
instructions from the internal ROM when the PC is less
than 4096. When held at a TTL low level, the
MSU2052 fetches all instuctions from external Program
Memory.
XTAL 1
Input to the oscillator's high gain amplifier. A crystal or
external source can be used.
XTAL 2
Output from the oscillator's amplifier. Required when a
crystal is used.
Terms
Idle Mode
During idle mode, the CPU is stopped but below blocks
are kept functioning: clock generator, RAM, timer/
counters, serial port and interrupt block. To save power
consumption, user's software program can invoke this
mode. The on-chip data RAM retains the values during
this mode, but the processor stops executing
instructions. In Idle mode (IDL=1), the oscillator
continues to run and the interrput, and timer blocks
continue to be clocked but the clock signal is gated off
to the CPU. The activities of the CPU no longer exist
unless waiting for an interrupt request.
-An instruction that sets flag (PCON.0) causes that to be
the last instruction executed before going into the Idle
Mode.
-In the Idle Mode, the internal clock signal is gated off to
the CPU, but not to the interrupt, Timer function.
-The CPU status is entirely preserved in its:
the Stack Pointer, Program Counter, Program Status
Word, Accumulator, and all other registers maintain
their data during Idle mode.
-There are three ways to terminate the Idle Mode.
1) By interrupt
Activation of any enabled interrupt will cause flag
(PCON.0) to be cleared by hardware, termination the
Idle Mode. After the program wakes up, the PC value
will point as interrupt vector (if enable IE register) and
execute interrupt service routine then return to PC+1
address after the program wakes up.
2) By hardware reset
Since the clock oscillator is still running, the hardware
reset needs to be held active for only two machine
cycles (24 oscillator periods) to complete the reset. All
SFR and PC value will be cleared to reset value.
3) By one of CLK, DATA, PORT 2.0-2.7 transition to
low (falling edge trigger)
After the program wakes up, the PC value will be
0023h (if enable IE register) and execute interrupt
service routine and then returns to PC+1 address after
the program wakes up.
Rev. 1.0 February 1998
5
Page 6
° C ° C
MOSEL VITELIC
Power Down Mode
It saves the RAM content, stops the clock generator
and disables every other blocks' function until the
coming hardware reset. To save even more power
consumption, user's software program can invoke this
mode. The SFRs and the on-chip data RAM retain
their values during this mode, but the porcessor stops
executing instructions. In Power-Down mode (PD=1)
the oscillator is frozen.
-An instruction that sets flag (PCON.1) causes that to
be the last instruction executed before going into the
Power Down Mode.
-In the Power Down Mode, the on-chip oscillator is
stopped.
With the clock frozen, all functions are stopped, but
the on-chip RAM and Special Function Registers are
held.
-Reset redefines all the SFRs, but does not change the
on-chip RAM.
-There are two ways to terminate the Power Down
Mode.
1) By hardware reset
All SFR and PC value will be cleared to reset value.
2) One of CLK, DATA, PORT 2.0-2.7 transition to low
(falling edge trigger)
After the program wakes up, the PC value will be
0023h (if enable IE register) and execute interrupt
service routine and then returns to PC+1 address after
the program wakes up.
-Care must be taken, however, to ensure that VCC is
not reduced before the Power Down Mode is invoked,
and that VCC is restored to its normal operating level
before the Power Down Mode is terminated.
-The hardware reset must be held active long enough
to allow the oscillator to restart and stabilize.
MSU2052/U2032
General of above
User should fix the attention on using wake up from
port 2:
-The user should write the power down or idle mode
flag value to one RAM address before write PCON to
distinguish waking up from power down mode or idle
mode.
-After idle mode or power down mode wakes up, the
interrupt service routine will be executed first and then
executes PC+1 address if the IE register is enabled
before entering power down mode or idle mode. The
interrupt service routine will not be executed but CPU
executes PC+1 address program if disable IE register.
-After wake up power down or idle mode the IDF flag
will be set by hardware. The IDF flag be cleared at
the ISR execution time. If IE register is disable, the
IDF flag will not be cleared when power down or idle
mode wakes up.
The state of pins during Idle and Power-Down Mode
Mode
Idle
Idle
Power Down
Power Down
Program
memory
Internal
External
Internal
External
Absolute Maximal Rating
Symbol
V
dd
- Vss
IN
V
V
OUT
T (Operating)
T (Storage)
Rev. 1.0 February 1998
Name
DC supply Voltage
Input voltage
output voltage
Operating Temperature
Storage Temperature
(16 MHz, typical operating conditons, valid for U20x2L series)
Symbol
V ILX
V ILE
V ILR
V IHX
V IHE
V IHR
V OLA
V OL0
V OL1
V OHA
V OH0
V OH1
V OH2
I IL
I IH
I TL
I LI
R RES
R X
C IO
I CC
Parameter
Input Low Voltage
"
"
Input High Voltage
"
"
Output Low Voltage
"
"
Output High Voltage
"
"
"
"
"
"
"
Logical 0 Input Current
Logical 1 Input Current
Logic Transition Current
Input Leakage Current
Reset Pulldown Resistance
Crystal feedback Resistance
Pin Capacitance
Power Supply Current
Valid
XTAL1
#EA
RES
XTAL1
#EA
RES
ALE, #PSEN
ports 0,3
ports 1,2
ALE, #PSEN
port 0
ports 1,3
port 2
ports 1,2,3
port 0
ports 1,2,3
port 0
RES
XTAL1,2
Vdd
Vdd
Vdd
Min.Typ.MaxUnit
mV
mV
mV
45
10
4.5
45
V
V
V
mV
mV
mV
V
V
V
V
V
V
V
V
uA
uA
1
uA
uA
8
Kohm
Kohm
pF
mA
7
mA
uA
1.8
2.4
2.2
2.4
1.8
2.4
1.8
2.4
50
90
Vcc+0.3
Vcc+0.3
Vcc+0.3
400
400
400
250
150
330
2
1
10
MSU2052/U2032
Test Conditions
I OL = 3.2 mA
I OL = 3.2 mA
I OL = 1.6 mA
I OH = -60 uA
I OH = -10 uA
I OH = -800 uA
I OH = -80 uA
I OH = -60 uA
I OH = -10 uA
I OH = -60 uA
I OH = -10 uA
V in = 0.45 V
V in = 3.0 V
V in = 1.4 V
0.45V < Vin < Vcc
Freq=1MHz, Ta=25
Active mode, 16 MHz
Idle mode, 16MHz
Power down mode
Rev. 1.0 February 1998
9
Page 10
MOSEL VITELIC
Data Memory Read Cycle Timing
T12T1T2T3T4T5T6T7T8T9T10 T11T12 T1T2
OSC
ALE
#PSEN
#RD
PORT2
PORT0
1
FloatFloatA -AFloat
INST inDATA in
2
3
3468
70
5
ADDRESS A - A
MSU2052/U2032
T3
7
158
ADDRESS
or Flloat
Program Memory Read Cycle Timing
T12 T1T2T3T4T5T6T7T8T9T10 T11T12 T1T2
OSC
ALE
#PSEN
#RD, #WR
PORT2
PORT0
1
FloatFloatA -AFloatFloatFloat
2
5
3
ADDRESS A - A
3468
70
7
158
INST inA -A
ADDRESS A -A
70
15 8
INST in
Rev. 1.0 February 1998
10
Page 11
MOSEL VITELIC
Data Memory Write Cycle Timing
T12T1T2T3T4T5T6T7T8T9T10 T11T12 T1T2
OSC
ALE
#PSEN
#WR
PORT2
PORT0
1
INST
2
234
FloatA -A
7 0
56
ADDRESS A - A
158
DATA OUT
MSU2052/U2032
T3
ADDRESS
or Float
I/O Ports Timing
X1
inputs P0, P1
inputs P2, P3
Output by
MOV Px,Src
RxD at Serial Port
Shift Clock
(Mode 0)
T7T8T9T10 T11 T12T1T2T3T4T5T6T7T8T6
sampled
sampled
current datanext data
sampled
Rev. 1.0 February 1998
11
Page 12
MOSEL VITELIC
Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)
T CLCH
T PXIX
T CLCL
T CHCX
T PXIZ
Vdd-0.5V
70%Vdd
0.45V
20%Vdd-0.1V
T CHCL
T CLCX
Tm.I External Program Memory Read Cycle
#PSEN
ALE
PORT 0
T LHLL
T AVLL
A0 - A7Instruction. INA0 - A7
T LLPL
T LLIV
T LLAXT PLAZT PLIV
T PLPH
MSU2052/U2032
T AVIV
PORT 2
A8 - A15A8 - A15
Tm.II External Data Memory Read Cycle
#PSEN
ALE
T LLDV
#RD
PORT 0
PORT 2
T LLYL
T AVLLT LLAX
A0-A7
from Ri or
T AVYL
T AVDV
T RLAZ
P2.0-P2.7 or A8-A15 from DPH
T RLRH
T RLDV
DATA IN
T YHLH
T RHDZ
T RHDX
A0-A7
From
A8-A15 from PCH
INSTR.
IN
Rev. 1.0 February 1998
12
Page 13
MOSEL VITELIC
Tm.III External Data Memory Write Cycle
#PSEN
ALE
#WR
PORT 0
PORT 2
Application Reference
T LHLL
T AVLL
A0-A7
from Ri or
DPL
T LLYLT WLWH
T QVWX
T LLAX
T AVYL
P2.0-P2.7 or A8-A15 from DPH
T QVWH
DATA OUT
T YHLH
T WHQX
MSU2052/U2032
A0-A7
From
PCL
A8-A15 from PCH
INSTR.
IN
Valid for U2052L16/ U2032L16
X'tal
C1
C2
3 MHz
15 pF
15 pF
R
open
6 MHz
15 pF
15 pF
open
Valid for U2052C16/ U2032C16/
U2052C25/ U2032C25/
U2052C40/ U2032C40
X'tal
C1
C2
12 MHz
30 pF
30 pF
R
open
16 MHz
30 pF
30 pF
open
12 MHz
30 pF
30 pF
open
25 MHz
15 pF
15 pF
62 Kohm
16 MHz
30 pF
30 pF
open
40 MHz
5 pF
5 pF
4.7 Kohm
X'tal
R
C1C2
X1
MSU2052
MSU2032
X2
Rev. 1.0 February 1998
13
Page 14
MOSEL VITELIC
40L 600mil PDIP Information
MSU2052/U2032
D
S
A1
e1
B1B
Note:
1.Dimension D Max & S include mold flash or tie bar
burrs.
2.Dimension E1 does not include interlead flash.
3.Dimenseion D & E1 include mold mismatch and are
determined at the mold parting line.
4.Dimension B1 does not include dambar protrusion/
infrusion.
5.Controlling dimension is inch.
6.General appearance spec. should base on final
visual inspection spec.
A2A
L
Symbol
A1
A2
B1
E1
e1
£\
eA
E
E1
C
eA
£\
Dimension in Inch
minimal/maximal
A
B
C
D
E
L
S
- / 0.210
0.010 / -
0.150 / 0.160
0.016 / 0.022
0.048 / 0.054
0.008 / 0.014
- / 2.070
0.590 / 0.610
0.540 / 0.552
0.090 / 0.110
0.120 / 0.140
0.630 / 0.670
/ 0.090
Dimension in mm
minimal/maximal
- / 5.33
0.25 / -
3.81 / 4.06
0.41 / 0.56
1.22 / 1.37
0.20 / 0.36
- / 52.58
14.99 / 15.49
13.72 / 14.02
2.29 / 2.79
3.05 / 3.56
0° / 15° 0° / 15°
16.00 / 17.02
- / 2.29
Rev. 1.0 February 1998
14
Page 15
MOSEL VITELIC
44L Plastic Leaded Chip Carrier (PLCC)
6
7
MSU2052/U2032
L
D
H
D
e
0
D
G
b1b
Note:
1.Dimension D & E does not include interlead flash.
2.Dimension b1 does not include dambar protrusion/
intrusion.
3.Controlling dimension:Inch
4.General appreance spec. should base on final visual
inspection spec.
E HE
C
Symbol
A
A1
A2
b1
b
C
D
E
e
GD
GE
HD
HE
L
y
θ
A2
Dimension in Inch
minimal/maximal
- / 0.185
0.020 / -
0.145 / 0.155
0.026 / 0.032
0.016 / 0.022
0.008 / 0.014
0.648 / 0.658
0.648 / 0.658
0.050 BSC
0.590 / 0.630
0.590 / 0.630
0.680 / 0.700
0.680 / 0.700
0.090 / 0.110
- / 0.004
A1
A
/
GE
y
Dimension in mm
minimal/maximal
- / 4.70
0.51 / -
3.68 / 3.94
0.66 / 0.81
0.41 / 0.56
0.20 / 0.36
16.46 / 16.71
16.46 / 16.71
1.27BSC
14.99 / 16.00
14.99 / 16.00
17.27 / 17.78
17.27 / 17.78
2.29 / 2.79
- / 0.10
/
Rev. 1.0 February 1998
15
Page 16
MOSEL VITELIC
MSU2052/U2032
44L Plastic Quad Flat Package
E2
E1
E
01
Note:
1.
Dimension D1 and E1 do not include mold
protrustion. Allowance protrusion is 0.25mm per side.
Dimensions D1 and E1 do include mold mismatch
and are determined at datum plane.
2.
Dimension b does not include dambar protrusion.
Allowance dambar protrusion shall be 0.08 mm total
in excess of the b dimension at maximum material
condition. Dambar cannot be located on the lower
radius or the lead foot.
D2 D1 D
seating plane
θ
C
Symbol
A
A1
A2
b
c
D
D1
D2
E
E1
E2
e
L
L1
R1
R2
S
θ
θ
1
θ
2
θ
3
C
C
L
S
A2
A1
A
L1
e
bb
Dimension in Inch
minimal/maximal
- / 0.100
0.006 / 0.014
0.071 / 0.087
0.012 / 0.018
0.004 / 0.009
0.520 BSC
0.394 BSC
0.315
0.520 BSC
0.394 BSC
0.315
0.031 BSC
0.029 / 0.041
0.063
0.005 / -
0.005 / 0.012
0.008 / 0° / 7°
0° / 10° REF
7° REF
0.0040.10
θ2
θ3
R1
Gage Plane
0.25 mm
R2
Dimension in mm
minimal/maximal
- / 2.55
0.15 / 0.35
1.80 / 2.20
0.30 / 0.45
0.09 / 0.20
13.20 BSC
10.00 BSC
8.00
13.20 BSC
10.00 BSC
8.00
0.80 BSC
0.73 / 1.03
1.60
0.13 / -
0.13 / 0.30
0.20 / as left
as left
as left
as left
Rev. 1.0 February 1998
16
Page 17
MOSEL VITELIC
MSU2052/U2032
44L Low profile Quad Flat Package
E2
E1
E
01
Note:
1.
Dimension D1 and E1 do not include mold
protrustion. Allowance protrusion is 0.25mm per side.
D1 and E1 are maximal plastic body size dimensions
including mold mismatch.
Dimension b does not include dambar protrusion.
2.
Allowance dambar protrusion shall not cause the
lead width to exceed the maximal b dimension by
more than 0.08 mm.
3.
Dambar can not be located on the lower radius or the
foot. Minimal space between protrusion and an
adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm
pitch packages.
D2 D1 D
seating plane
θ
C
Symbol
A
A1
A2
b
c
D
D1
D2
E
E1
E2
e
L
L1
R1
R2
S
θ
θ
1
θ
2
θ
3
C
C
L
S
A2
A1
A
L1
e
bb
Dimension in Inch
minimal/maximal
- / 0.063
0.002 / 0.006
0.053 / 0.057
0.012 / 0.018
0.004 / 0.008
0.472 BSC
0.393 BSC
0.315
0.472 BSC
0.393 BSC
0.315
0.031 BSC
0.018 / 0.030
0.039 REF
0.003 / -
0.003 / 0.008
0.008 / 0° / 7°
0° / 11°/13°
/13°
11°
0.0040.10
θ2
θ3
R1
Gage Plane
0.25 mm
R2
Dimension in mm
minimal/maximal
- / 1.60
0.05 / 0.15
1.35 / 1.45
0.30 / 0.45
0.09 / 0.20
12.00 BSC
10.00 BSC
8.00
12.00 BSC
10.00 BSC
8.00
0.80 BSC
0.45 / 0.75
1.00 REF
0.08 / -
0.08 / 0.20
0.20 / as left
as left
as left
as left
Rev. 1.0 February 1998
17
Page 18
MOSEL VITELIC
Bonding Information
MSU2052/U2032
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
PAD-NAME
P1.5
P1.6
P1.7
RES
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
XTAL2
XTAL1
VSS
VSS
VSS
P2.0
P2.1
P2.2
P2.3
P2.4
43 42 41 40 39 38 37 36 35 34 33
1
2
X-COORD
237
400
559
722
882
1044
1204
1366
1526
1688
1931
1931
1931
1931
1931
1931
1931
1931
1931
1931
1931
1931
Y-COORD
186
186
186
186
186
186
186
186
186
186
310
537
769
1090
1291
1442
1593
1791
2016
2243
2468
2696
IndexPAD-NAME
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
32
31
P2.5
P2.6
P2.7
#PSEN
ALE
#EA
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
VDD
VDD
P1.0
P1.1
P1.2
P1.3
P1.4
X-COORD
1688
1526
1366
1204
1044
882
722
559
400
237
168
168
168
168
168
168
168
168
168
168
168
Y-COORD
2874
2874
2874
2874
2874
2874
2874
2874
2874
2874
2595
2367
2142
1915
1717
1566
1369
1144
917
692
464
3
4
5
6
7
8
9
10
11 12 13 14 15 16 17 18 19 20 21 22
substrate should be bonded to Vss
MSU2052/U2032
2200 x 3160 (µm)
PAD SIZE : 90 x 90 (µm)
30
29
28
27
26
25
24
23
pid 252* 12/96
pid 252** 01/97
pid 252*** 02/97
pid 252A 02/98
Logo
Rev. 1.0 February 1998
18
Page 19
MOSEL VITELIC
MSU2052/U2032
To: Mosel Vitelic Inc.
886-3-578-4732 (fax #)
Attn: Sales & Marketing Department
Product Request Form
We hereby request MVI to start producing MSU2052 which is specified below.
Please send us the product code and a hardcopy of data code as well as data code file duplicated on floppy
diskette. No further confirmation is necessary.
Production will start automatically once you receive our data code and verify that the checksum is match.
Mass Production of the captioned device shall be done in accordance with the purchase order(s) issued by
us or a company specified by us. All terms and conditions are based on the development agreement and/or
contract signed between MVI and us.
Data Code Descriptions
Code Length
File Length
File Name
Checksum
Unused
Data Byte
Format
Media
Company Name :
00h filled
FFh filled
HEX format
Binary code format
EPROM
8751 chip
File on Floppy
E-mail file
Phone # :
IC descriptions
Dice form
P type = 40L-PDIP
J type = 44L-PLCC
Q type = 44L-PQFP
h
L type = 44L-LQFP
Top Marking (fill only for packaged)
Use MVI logo, date code and part number
Use my specifications as described below
Specify below fields only for customer top marking
Date code location descriptions
Use regular date code as MVI's
Leave it as blank
use right side five letters
Logo Specifications
Leave it blank
Use my specifications as attachment
Part number specified, less than 15 digits
Fax # :
U2052L16, 16 MHz low working voltage
U2052C16, 16 MHz
U2052C25, 25 MHz
U2052C40, 40 MHz
Name (Typed) :
Position Title :
Department, Section :
Signature Date :
Rev. 1.0 February 1998
Signature :
19
Page 20
MOSEL VITELIC
To: Mosel Vitelic Inc.
886-3-578-4732 (fax#)
Attn: Sales & Marketing Department
Logo Top Marking Request & spec.
We hereby request MVI to have our logo printed on top of the device package. Below is the
specification of our logo in 20:1 scale base. This logo diagram is clear enough and is able to be
shrunk directly to fit into available top marking area described on page.
MSU2052/U2032
Phone # :
Company Name :
Signature :
Name (Typed) :
Position Title :
Department, Section :
Signature Date :
Rev. 1.0 February 1998
Fax # :
20
Page 21
MOSEL VITELIC
WORLDWIDE OFFICESMSU2052/U2032
U.S.A.
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0185
HONG KONG
19 DAI FU STREET
TAIPO INDUSTRIAL ESTATE
TAIPO, NT, HONG KONG
PHONE: 852-2665-4883
FAX: 852-2664-7535
NORTHWESTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0185
NORTHEASTERN
SUITE 436
20 TRAFALGAR SQUARE
NASHUA, NH 03063
PHONE: 603-889-4393
FAX: 603-889-9347
TAIWAN
7F, NO. 102
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
1 CREATION ROAD I
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 886-3-578-3344
FAX: 886-3-579-2838
U.S. SALES OFFICES
SOUTHWESTERN
SUITE 200
5150 E. PACIFIC COAST HWY.
LONG BEACH, CA 90804
PHONE: 562-498-3314
The information in this document is subject to change without
notice.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
1/98
Printed in U.S.A.
of high quality products suitable for usual commercial applicaMOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
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