Datasheet MSM80C51F-xxxJS, MSM80C51F-xxxRS, MSM80C31F-xxxGS, MSM80C31F-xxxJS, MSM80C51F-xxxGS Datasheet (OKI)

E2E1037-19-41

¡ Semiconductor MSM80C31F/80C51F

This version: Mar. 1995

¡ Semiconductor

MSM80C31F/MSM80C51F

CMOS 8-Bit Microcontroller

GENERAL DESCRIPTION

The OKI MSM80C31F/MSM80C51F microcontroller is a low-power, 8-bit device implemented
in OKI's silicon-gate complementary metal-oxide semiconductor process technology. The
device
data RAM, 32 I/O lines, two 16-bit timer/counters, a five-source two-level interrupt
structure, a full duplex
has two software selectable modes for further power reduction — Idle and Power Down. Idle
mode freezes the CPU's in-struction execution while maintaining RAM and allowing the timers,
serial port and interrupt system to continue functions. Power Down mode saves the RAM
contents but freezes the oscillator causing all other device functions to be inoperative.

includes 4K bytes of mask programmable ROM (MSM80C51F only), 128 bytes of

serial port, and an oscillator and clock circuitry. In addition, the device

FEATURES

• Low power consumption by 2 mm silicon gate CMOS process technology

• Fully static circuit

• Internal program memory : 4K bytes (MSM80C51F)

• External program memory space : 64K bytes

• Internal data memory (RAM) : 128 bytes

• External data memory (RAM) space : 64K bytes

• I/O ports : 8-bit ¥ 4 ports

• Two 16-bit timer/counters

• Multifunctional serial port (UART)

• Five interrupt sources (Priority can be set)

• Four sets of working registers (R0-7 ¥ 4)

• Stack : Internal data memory (RAM)
128-byte area can be used arbitrarily (by SP specified)

• Two CPU power-down modes
(1) Idle mode : CPU stopped while oscillation continued.

(Software setting)

(2) PD mode : CPU and oscillation all stopped.

(Software setting)
(Setting I/O ports to floating status possible)

• Operating temperature : –40 to +85°C (@ 12 MHz, V

–20 to +70°C (@ 16 MHz, V

• 2-byte 1-machine cycle instructions : 1 msec. @ 12 MHz

0.75 msec. @ 16 MHz

• Multiplication/division instructions : 4 msec. @ 12 MHz

3 msec. @ 16 MHz

• Instruction code addressing method

Byte specification : Data addressing (direct)
Bit specification : Bit addressing

= 5 V ±20%)

CC

= 5 V ±5%)

CC

1/38

¡ Semiconductor MSM80C31F/80C51F

• Package options

40-pin plastic DIP (DIP40-P-600-2.54) : (MSM80C31F-¥¥¥RS) (MSM80C51F-¥¥¥RS)
44-pin plastic QFP (QFP44-P-910-0.80-2K) : (MSM80C31F-¥¥¥GS) (MSM80C51F-¥¥¥GS)
44-pin plastic QFJ (PLCC) (QFJ44-P-S650-1.27) : (MSM80C31F-¥¥¥JS) (MSM80C51F-¥¥¥JS)

¥¥¥ indicates the code number.

DIFFERENCES BETWEEN MSM80C31F/MSM80C51F AND MSM80C31/MSM80C51

• Operating frequency

0.5 to 16 MHz ..................... MSM80C31F-1/MSM80C51F-1

0.5 to 12 MHz ..................... MSM80C31/MSM80C51/MSM80C31F/MSM80C51F

• External clock input terminal

XTAL1 ................................. MSM80C31F(-1)/MSM80C51F(-1)

XTAL2 ................................. MSM80C31/MSM80C51

• Emulation mode
Output impedance of ALE and PSEN pins becomes about 20 kW while CPU is being reset in
MSM80C31F/MSM80C51F.

Any other functions and electrical characteristics of MSM80C31F/MSM80C51F except for
above three differences are the same as those of MSM80C31/MSM80C51.

2/38

3/38

¡ Semiconductor MSM80C31F/80C51F

BLOCK DIAGRAM

PCH

CONTROL SIGNALS

SPECIAL
FUNCTION
REGISTER

ADDRESS
DECODER

PLA

IR AIR

C-ROM

TR1

TR2ACC

ALU

BR

PSW

RAMDP

R/W AMP

128 WORDS

¥ 8 BITS

DPLDPH

PCL

ROM

4096 WORDS

¥ 8 BITS

SENSE AMP

PCLL

PCHL

PORT 2 PORT 0

PCON

OSC AND TIMING

PORT 1 PORT 3

XTAL1

XTAL2

ALE

RESET

PSEN

EA

TH1 TL1 TH0 TL0 TMOD TCON IE IP SBUF(T) SBUF(R)

INTERRUPT

TIMER/COUNTER

SERIAL IO

SCON

SIGNALSR/W

SP

ADDRESS DECODER

ADDRESS DECODER

P2.0 to P2.7

P0.0 to P0.7

P1.0 to P1.7

P3.0 to P3.7

4/38

¡ Semiconductor MSM80C31F/80C51F

CLOCK WAVEFORMS

Basic Timing Chart

ACC & RAM

S1 S2 S3 S4 S5 S6M1S1 S2 S3 S4 S5 S6M1S1 S2 S3 S4 S5 S6M2S1 S2 S3 S4 S5 S6

M1

PCL PCL PCL PCL

PCH PCH PCH PCHPCHDPH & PORT DATAPCH

,,,,,,,,,,,

,,,,,,,,,,,,,,

,,,,,,,,,,,,,,,,,

,,,,,,,,,,,,,,,,,

,,,,,,,,,,,,,,,,,,

,,,,,,,,,,,,,,,,,,

,,,,,,,,,,,,,,,,,,

,,,,,,,,,,,,,,,,,,

,,,,,,,,,,,,

PORT NEW DATA

PC+1

TM+1

PC+1

TM+1

TM+1

TM+1

PC+1PC+1PC+1

CYCLE

STEP

1
0
1
0

1
0
1
0

1
0

1
0

1
0
1
0

XTAL1

ALE

RD/WR

PORT-0

PORT-2

CPU¨PORT

PORT¨CPU

PCH

PCL

DPL&Rr

DATA STABLE

PORT OLD DATA

DATA STABLE

PSEN

PCL

Instruction decoding

Instruction execution

Instruction decoding

Instruction execution

Instruction decoding

Instruction execution

Port output/input

Instruction execution

Port output/input

Instruction execution

execution

External data memory instruction

¡ Semiconductor MSM80C31F/80C51F

PIN CONFIGURATION (TOP VIEW)

P1.0
P1.1
P1.2
P1.3
P1.4

P1.5
P1.6
P1.7

RESET

RXD/P3.0

TXD/P3.1

INT0/P3.2
INT1/P3.3

T0/P3.4
T1/P3.5

WR/P3.6

RD/P3.7

XTAL2
XTAL1

V

SS

10
11
12
13
14
15
16
17
18

19
20

1
2
3
4
5

6
7
8
9

40
39
38
37
36

35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

V

CC

P0.0
P0.1
P0.2
P0.3

P0.4
P0.5
P0.6
P0.7

EA

ALE

PSEN

P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0

40-Pin Plastic DIP

5/38

¡ Semiconductor MSM80C31F/80C51F

PIN CONFIGURATION (TOP VIEW) (continued)

P1.5
P1.6
P1.7

RESET

P3.0/RXD

NC

P3.1/TXD
P3.2/INT0
P3.3/INT1

P3.4/T0

P3.5/T1/HPDI

1
2
3
4
5
6
7
8

9
10
11

P1.4
44

12

P3.6/WR

P1.3
43

13

P3.7/RD

P1.2

P1.1

42

41

14

15

XTAL2

XTAL1

P1.0NCV
40

39

16

17

SSVSS

V

CC

38

18

P2.0

P0.0
37

19

P2.1

P0.1
36

20

P2.2

P0.2
35

21

P2.3

P0.3
34

22

P2.4

33
32
31
30
29
28
27
26
25
24
23

P0.4
P0.5
P0.6
P0.7

EA

NC
ALE

PSEN

P2.7
P2.6
P2.5

44-Pin Plastic QFP

6/38

¡ Semiconductor MSM80C31F/80C51F

)

PIN CONFIGURATION (TOP VIEW) (continued)

P0.5

P0.6

P0.4
39

38

P0.7EANC

37

36

35

34

ALE
33

PSEN

32

P2.7
31

P2.6
30

P2.5
29

P0.3
P0.2
P0.1
P0.0

V

CC

NC
P1.0
P1.1
P1.2
P1.3
P1.4

40
41
42
43
44

P2.4

28
27

P2.3

26

P2.2

25

P2.1

24

P2.0
1
2
3
4
5
6

7

8

9

10

11

12

13

14

15

16

17

P1.5

P1.6

P1.7

RESET

NC

P3.0/RXD

P3.1/TXD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

23
22
21
20
19
18

NC

V

SS

XTAL1

XTAL2

P3.7/RD

P3.6/WR

44-Pin Plastic QFJ (PLCC

7/38

¡ Semiconductor MSM80C31F/80C51F

PIN DESCRIPTION

Symbol Description

V

SS

V

CC

Port 0.0

- 0.7

Port 1.0

- 1.7

Port 2.0

- 2.7

Port 3.0

- 3.7

RESET

ALE

PSEN

EA

XTAL1
XTAL2

Ground potential
Supply voltage during Normal, Idle and Power Down operation
Port 0 is an 8-bit open-drain bidirectional I/O port. It is also the mutiplexed low-order address
and data bus during accesses to external memory.
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. It can drive CMOS inputs without
external pull-ups.
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. It outputs the high-order address
byte during accesses to external memory. It can drive CMOS inputs without external pull-ups.
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. It also provides various special

features, as shown below:

Port Pin

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

Alternate Function

RXD
TXD

INT0
INT1

T0
T1

WR
RD

(serial input port)
(serial output port)
(external interrupt)
(external interrupt)
(Timer 0 external input)
(Timer 1 external input)
(external data memory write strobe)
(external data memory read strobe)

Port 3 can drive CMOS inputs without external pull-ups.
Reset input pin. A reset is accomplished by holding the RESET pin high for at least 1ms.

even if the oscillator has been stopped. The CPU responds by executing an internal reset. An
internal pull-down resistor permits Power-On reset using only a capacitor connected to V

CC

.

This pin does not receive the power down voltage since the function has been transferred to the

pin.

V

CC

Address Latch Enable. This output latches for latching the low byte of the address during
accesses to external memory. For this purpose, ALE is activated twice every machine cycle or
at a constant rate of 1/6th the oscillator frequency, except during an external memory access at
which time one ALE pulse is skipped. ALE can drive CMOS inputs without an external pull-up.
Program Store Enable output. This output is the read strobe to external program memory.

For this purpose, PSEN is activated twice every machine cycle. (However, when executing out
of external program memory, two activations of PSEN are skipped during each access to
external data memory.) PSEN is not activated during fetches from internal program memory.
It can drive CMOS inputs without an external pull-up.

External Access input pin. When EA is held high, the CPU executes out of internal program
memory (unless the program counter exceeds 0FFFH).
When EA is held low, the CPU executes only out of external program memory.
EA must not be floated.
Crystal 1 pin. It is an input to the inverting amplifier which forms the internal oscillator.
Crystal 2 pin. It is an output of the inverting amplifier that forms the internal oscillator.

8/38

¡ Semiconductor MSM80C31F/80C51F

DATA MEMORY AND SPECIAL FUNCTION REGISTER LAYOUT DIAGRAM

7F

30

7F

2F

BIT

7

20

R7

1F

R0

18

DATA RAM

17
10

0F
08

07
00

R7
R0

R7
R0

R7
R0

USER RAM

80W ¥ 8 bits

ADDRESSABLE

RAM

BANK 3

BANK 2

BANK 1

BANK 0

78

0F0H

0E0H
0D0H
0B8H
0B0H
0A8H
0A0H

99H
98H

90H
8DH
8CH
8BH
8AH

89H

SPECIAL FUNCTION REGISTERS

0

88H

87H

83H

82H

81H

80H

BIT ADDRESSING

DATA ADDRESSING

B
ACC
PSW
IP
P3
IE
P2
SBUF
SCON
P1
TH1
TH0
TL1
TL0
TMOD
TCON
PCON
DPH
DPL
SP
P0

9/38

¡ Semiconductor MSM80C31F/80C51F

DETAILED DIAGRAM OF DATA MEMORY (RAM)

7FH
30H

2FH

2EH

2DH

2CH

2BH

2AH

29H

28H

27H

26H

25H

7F

77

6F

67

5F

57

4F

47

3F

37

2F

7E

76

6E

66

5E

56

4E

46

3E

36

2E

USER DATA RAM

7D

75

6D

65

5D

55

4D

45

3D

35

2D

7C

74

6C

64

5C

54

4C

44

3C

34

2C

7B

73

6B

63

5B

53

4B

43

3B

33

2B

7A

72

6A

62

5A

52

4A

42

3A

32

2A

79

71

69

61

59

51

49

41

39

31

29

78

70

68

60

58

50

48

40

38

30

28

127

48
47

46

45

44

43

42

41

40

39

38

37

BIT ADDRESSING

DATA ADDRESSING

INDIRECT ADDRESSING

24H

23H

22H

21H

20H
1FH

18H
17H

10H
0FH

08H
07H

00H

27

1F

17

0F

07

26

1E

16

0E

06

25

1D

15

0D

05

24

1C

14

0C

04

Bank 3

Bank 2

Bank 1

Bank 0

23

1B

13

0B

03

22

1A

12

0A

02

21

19

11

09

01

20

18

10

08

00

36

35

34

33

32
31

24
23

16
15

8

REGISTER ADDRESSING

7

0

10/38

¡ Semiconductor MSM80C31F/80C51F

DETAILED DIAGRAM OF SPECIAL FUNCITON REGISTERS

Special

Function
Data
Address

0F0H B

(MSB) Bit Address (LSB)

F7 F6 F5 F4 F3 F2 F1 F0

E7 E6 E5 E4 E3 E2 E1 E00E0H ACC
CY AC F0 RS1 RS0 OV F1 P
D7 D6 D5 D4 D3 D2 D1 D00D0H PSW

PS PT1 PX1 PT0 PX0

— — — BC BB BA B9 B80B8H IP

B7 B6 B5 B4 B3 B2 B1 B00B0H P3
EA ES ET1 EX1 ET0 EX0
AF — — AC AB AA A9 A80A8H IE

Register

Symbol

A7 A6 A5 A4 A3 A2 A1 A00A0H P2

Not Bit Addressable99H SBUF

SM0 SM1 SM2 REN TB8 RB8 TI RI

9F 9E 9D 9C 9B 9A 99 9898H SCON

97 96 95 94 93 92 91 9090H P1

8DH TH1

8BH TL1
8AH TL0

89H TMOD

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

8F 8E 8D 8C 8B 8A 89 8888H TCON

82H DPL
81H SP
80H P0

87 86 85 84 83 82 81 80

Not Bit Addressable
Not Bit Addressable8CH TH0
Not Bit Addressable
Not Bit Addressable
Not Bit Addressable

Not Bit Addressable87H PCON

Not Bit Addressable83H DPH
Not Bit Addressable
Not Bit Addressable

11/38

¡ Semiconductor MSM80C31F/80C51F

INSTRUCTION LIST

List of Instruction Symbols

A : Accumulator
AB : Register pair
AC : Auxiliary carry flag
B : Arithmetic operation register
C : Carry flag
DPTR : Data pointer
PC : Program counter
Rr : Register indicator (r = 0 to 7)
SP : Stack pointer
AND : Logical product
OR : Logical sum
XOR : Exclusive-OR
+ : Addition
– : Subtraction
X : Multiplication
/ : Division
(X) : Denotes the contents of X
((X)) : Denotes the contents of address determined by the contents of X
# : Denotes the immediate data
@ : Denotes the indirect address
= : Equality
⫽ : Non-equality

¨ : Substitution
Æ : Substitution

— : Negation
< : Smaller than
> : Larger than
bit address : RAM and the special function register bit specifier address (b0 to b7)
code address : Absolute address (A0 to A15)
data : Immediate data (I0 to I7)
relative offset : Relative jump address offset value (R0 to R7)
direct address : RAM and the special function register byte specifier address (a0 to a7)

12/38

¡ Semiconductor MSM80C31F/80C51F

MSM80C31F/MSM80C51F Instruction Codes

L

H

0

0000

1

0001

2

0010

3

0011

4

0100

5

0101

6

0110

7

0111

8

1000

9

1001

A

1010

B

1011

C

1100

D

1101

E

1110

F

1111

0

0000

NOP

JBC bit,

rel

JB bit,

rel

JNB bit,

rel

JC
rel

JNC rel

JZ rel

JNZ rel

SJMP rel

MOV DPTR,

#data 16

ORL C, /bit

ANL C, /bit

PUSH

direct

POP

direct

MOVX A,

@DPTR

MOVX

@DPTR, A

1

0001

AJMP

address 11

(Page 0)

ACALL

address 11

(Page 0)

AJMP

address 11

(Page 1)

ACALL

address 11

(Page 1)

AJMP

address 11

(Page 2)

ACALL

address 11

(Page 2)

AJMP

address 11

(Page 3)

ACALL

address 11

(Page 3)

AJMP

address 11

(Page 4)

ACALL

address 11

(Page 4)

AJMP

address 11

(Page 5)

ACALL

address 11

(Page 5)

AJMP

address 11

(Page 6)

ACALL

address 11

(Page 6)

AJMP

address 11

(Page 7)

ACALL

address 11

(Page 7)

2

0010

LJMP

address 16

LCALL

adress 16

RET RL A

RETI RLC A

ORL

direct, A

ANL

direct, A

XRL

direct, A

ORL C,

bit

ANL C,

bit

MOV bit,CMOVC A,

MOV C,

bit

CPL bit CPL C

CLR bit CLR C SWAP A

SETB bit SETB C DA A

MOVX A,

@R0

MOVX

@R0, A

3

0011

RR A INC A

RRC A DEC A

ORL

direct,

#data

ANL

direct,

#data

XRL

direct,

#data

JMP

@A+DPTR

MOVC A,

@A+PC

@A+DPTR

INC DPTR MUL AB

MOVX A,

@R1

MOVX

@R1, A

0100

ADD A,

#data

ADDC A,

#data

ORL A,

#data

ANL A,

#data

XRL A,

#data

MOV A,

#data

DIV AB

SUBB A,

#data

CJNE A,

#data

rel

CLR A

CPL A

4

5

0101

INC

direct

DEC

direct

ADD A,

direct

ADDC A,

direct

ORL A,

direct

ANL A,

direct

XRL A,

direct

MOV
direct
#data

MOV

direct1,

direct2

SUBB A,

direct

CJNE A,

direct,

rel

XCH A,

direct
DJNZ

direct,

rel

MOV A,

direct

MOV

direct, A

6

0110

INC @R0 INC @R1

DEC @R0 DEC @R1

ADD A,

@R0

ADDC A,

@R0

ORL A,

@R0

ANL A,

@R0

XRL A,

@R0

MOV @R0,

#data

MOV

direct,

@R0

SUBB A,

@R0

MOV @R0,

direct

CJNE @R0

#data,

rel

XCH A,

@R0

XCHD A,

@R0

MOV A,

@R0

MOV

@R0, A

7

0111

ADD A,

@R1

ADDC A,

@R1

ORL A,

@R1

ANL A,

@R1

XRL A,

@R1

MOV @R1,

#data

MOV

direct,

@R1

SUBB A,

direct

MOV @R1,

direct

CJNE @R1,

#data, rel

XCH A,

@R1

XCHD A,

@R1

MOV A,

@R1

MOV

@R1, A

2BYTES

2CYCLES

3BYTES

MNEMONIC

4CYCLES

13/38

¡ Semiconductor MSM80C31F/80C51F

MSM80C31F/MSM80C51F Instruction Codes (continued)

L

H

0

0000

1

0001

2

0010

3

0011

4

0100

5

0101

6

0110

7

0111

8

1000

8

1000

INC R0

DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7

ADD A, R0 ADD A, R1 ADD A, R2 ADD A, R3 ADD A, R4 ADD A, R5 ADD A, R6 ADD A, R7

ADDC A, R0 ADDC A, R1 ADDC A, R2 ADDC A, R3 ADDC A, R4 ADDC A, R5 ADDC A, R6 ADDC A, R7

ORL A, R0 ORL A, R1 ORL A, R2 ORL A, R3 ORL A, R4 ORL A, R5 ORL A, R6 ORL A, R7

ANL A, R0 ANL A, R1 ANL A, R2 ANL A, R3 ANL A, R4 ANL A, R5 ANL A, R6 ANL A, R7

XRL A, R0 XRL A, R1 XRL A, R2 XRL A, R3 XRL A, R4 XRL A, R5 XRL A, R6 XRL A, R7

MOV R0,

#data

MOV

direct,

R0

9

1001

INC R1 INC R2 INC R3 INC R4 INC R5 INC R6 INC R7

MOV R1,

#data

MOV

direct,

R1

A

1010

MOV R2,

#data

MOV

direct,

R2

B

1011

MOV R3,

#data

MOV

direct,

R3

C

1100

MOV R4,

#data

MOV

direct,

R4

D

1101

MOV R5,

#data

MOV

direct,

R5

E

1110

MOV R6,

#data

MOV

direct,

R6

F

1111

MOV R7,

#data

MOV

direct,

R7

9

1001

A

1010

B

1011

C

1100

D

1101

E

1110

F

1111

SUBB A,R0SUBB A,R1SUBB A,R2SUBB A,R3SUBB A,R4SUBB A,R5SUBB A,R6SUBB A,

R7

MOV R0,

direct

CJNE R0,

#data

rel

XCH A,

R0

DJNZ R0,

rel

MOV A, R0 MOV A, R1 MOV A, R2 MOV A, R3 MOV A, R4 MOV A, R5 MOV A, R6 MOV A, R7

MOV R0, A MOV R1, A MOV R2, A MOV R3, A MOV R4, A MOV R5, A MOV R6, A MOV R7, A

MOV R1,

direct

CJNE R1,

#data

rel

XCH A,

R1

DJNZ R1,

rel

MOV R2,

direct

CJNE R2,

#data

rel

XCH A,

R2

DJNZ R2,

rel

MOV R3,

direct

CJNE R3,

#data

rel

XCH A,

R3

DJNZ R3,

rel

MOV R4,

direct

CJNE R4,

#data

rel

XCH A,

R4

DJNZ R4,

rel

MOV R5,

direct

CJNE R5,

#data

rel

XCH A,

R5

DJNE R5,

rel

MOV R6,

direct

CJNE R6,

#data

rel

XCH A,

R6

DJNE R6,

rel

MOV R7,

direct

CJNE R7,

#data

rel

XCH A,

R7

DJNE R7,

rel

14/38

¡ Semiconductor MSM80C31F/80C51F

Instruction Set Details

Type

Mnemonic

ADD A, Rr
ADD A, direct

ADD A, @Rr
ADD A, #data

ADDC A, Rr
ADDC A, direct

ADDC A, @Rr
ADDC A, #data

SUBB A, Rr
SUBB A, direct

SUBB A, @Rr
SUBB A, #data

Airthmetic operation instructions

MUL AB
DIV AB

D

7

00101r
00100101

a

7a6a5a4a3a2a1a0

0010011r
00100100

I

7I6I5I4I3I2I1I0

00111r
00110101

a

7a6a5a4a3a2a1a0

0011011r
00110100

I

7I6I5I4I3I2I1I0

10011r
10010101

a

7a6a5a4a3a2a1a0

1001011r
10010100

I

7I6I5I4I3I2I1I0

10100100
10000100

Instruction code

D6 D5 D4 D3 D1

D2 D0

2r1r0

2r1r0

2r1r0

Bytes Cycles

11
21

11

0

21

11
21

11

0

21

11
21

11

0

21

14
14

Description

(AC), (0V), (C), (A) ¨ (A)+(Rr)
(AC), (0V), (C), (A) ¨ (A)+(direct

address)
(AC), (0V), (C), (A) ¨ (A)+((Rr))

(AC), (0V), (C), (A) ¨ (A)+#data

(AC), (0V), (C), (A) ¨ (A)+(C)+(Rr)
(AC), (0V), (C), (A) ¨ (A)+(C)+

(direct address)
(AC), (0V), (C), (A) ¨ (A)+(C)+((Rr))

(AC), (0V), (C), (A) ¨ (A)+(C)+#data

(AC), (0V), (C), (A) ¨ (A)–((C))+((Rr))
(AC), (0V), (C), (A) ¨ (A)–((C)+

(direct address))
(AC), (0V), (C), (A) ¨ (A)–((C)+((Rr))

(AC), (0V), (C), (A) ¨ (A)–((C)+
#data)

(AB) ¨ (A) x (B)
(A)quotient,

(B) remainder

¨ (A)/(B)

DA A

CLR A
CPL A
PL A

instructions

PL C

Accumulation operation

11010100

11100100
11110100
00100011

00110011

11

11
11
11

11

When the contents of accumulator bits
0 thru 3 are greater than 9, or when
auxiliary carry (AC) is 1, 6 is added to
bits 0 thru 3. Bits 4 thru 7 are then
examined, and when bits 4thru 7
follwoing compensation of lower bits 0
thru 3 is greater than 9, or when carry
(C) is 1, 6 is added to bits 4 thru 7. As
a result, the cary flag can be set, but
cannot be cleared.

(A) ¨ 0
(A) ¨ (A)

Accumulator

¨¨¨¨¨¨¨¨C

70

Accumulator

C

¨¨¨¨¨¨¨¨

70

15/38

¡ Semiconductor MSM80C31F/80C51F

Instruction Set Details (continued)

Type

Mnemonic

RR A

RRC A

instructions

Accumulation operation

SWAP A
INC A
INC Rr
INC direct

INC @Rr
INC DPTR
DEC A
DEC Rr

Increment/decrement

DEC direct

DEC @Rr
ANL A, Rr
ANL A, direct

ANL A, @Rr
ANL A, #data

ANL direct, A

ANL direct,
#data

ORL A, Rr
ORL A, direct

Logical operation instructions

ORL A, @Rr
ORL A, #data

ORL direct, A

Instruction code

D6 D5 D4 D3 D1

D

7

D2 D0

00000011

00010011

11000100
00000100
00001r2r1r
00000101

a

7a6a5a4a3a2a1a0

0000011r
10100011
00010100
00011r2r1r
00010101

a

7a6a5a4a3a2a1a0

0001011r
01011r2r1r
01010101

a

7a6a5a4a3a2a1a0

0101011r
01010100

I

7I6I5I4I3I2I1I0

01010010

a

7a6a5a4a3a2a1a0

01010011

a

7a6a5a4a3a2a1a0

I7I6I5I4I3I2I1I

01001r2r1r
01000101

a

7a6a5a4a3a2a1a0

0100011r
01000100

I

7I6I5I4I3I2I1I0

01000010

a

7a6a5a4a3a2a1a0

Bytes Cycles

11

11

11
11
11

0

21

11

0

12
11
11

0

21

11

0

11

0

21

11

0

21

21

32

0

11

0

21

11

0

21

21

Description

Accumulator

ЖЖЖЖЖЖЖЖ

C

70

Accumulator

C

ЖЖЖЖЖЖЖЖ

70

(A

) ´ (A0 -3)

4 -7

(A) ¨ (A)+1
(Rr) ¨ (Rr)+1
(direct address) ¨ (direct address)+1

((Rr)) ¨ ((Rr))+1
(DPTR) ¨ (DPTR)+1
(A) ¨ (A)–1
(Rr) ¨ (Rr)–1
(direct address) ¨ (direct address)–1

((Rr)) ¨ ((Rr))–1
(A) ¨ (A) AND (Rr)
(A) ¨ (A) AND (direct address)

(A) ¨ (A) AND ((Rr))
(A) ¨ (A) AND #data

(direct address) ¨ (direct address)
AND (A)

(direct address) ¨ (direct address)
AND #data

(A) ¨ (A) OR (Rr)
(A) ¨ (A) OR (direct address)

(A) ¨ (A) OR ((Rr))
(A) ¨ (A) OR #data

(direct address) ¨ (direct address)
OR (A)

16/38

¡ Semiconductor MSM80C31F/80C51F

Instruction Set Details (continued)

Type

Mnemonic

ORL direct,
#data

D6 D5 D4 D3 D1

D

7

01000011

a

7a6a5a4a3a2a1a0

I7I6I5I4I3I2I1I
XRL A, Rr
XRL A, direct

XRL A, @Rr
XRL A, #data

XRL direct, A

Logical operation instructions

XRL direct,
#data

01101r2r1r
01100101

a

7a6a5a4a3a2a1a0

0110011r
01100100

I

7I6I5I4I3I2I1I0

01100010

a

7a6a5a4a3a2a1a0

01100011

a

7a6a5a4a3a2a1a0

I7I6I5I4I3I2I1I
MOV A, #data

MOV Rr, #data

MOV direct,
#data

01110100

I

7I6I5I4I3I2I1I0

01111r2r1r

I

7I6I5I4I3I2I1I0

01110101

a

7a6a5a4a3a2a1a0

I7I6I5I4I3I2I1I
MOV @Rr,

#data
MOV DPTR,

Immediate data setting instructions

#data 16

CLR C
SETB C
CPL C
ANL C, bit

ANL C,/bit

ORL C, bit

Carry flag operation instructions

ORL C,/bit

0111011r

I

7I6I5I4I3I2I1I0

10010000

I15I14I13I12I11I10I9I

I

7I6I5I4I3I2I1I0

11000011
11010011
10110011
10000010

b

7b6b5b4b3b2b1b0

10110000

b

7b6b5b4b3b2b1b0

01110010

b

7b6b5b4b3b2b1b0

10100000

b

7b6b5b4b3b2b1b0

Instruction code

D2 D0

Bytes Cycles

32

0

11

0

21

11

0

21

21

32

0

21

21

0

32

0

21

0

32

8

11
11
11
22

22

22

22

Description

(direct address) ¨ (direct address)
OR #data

(A) ¨ (A) XOR (Rr)
(A) ¨ (A) XOR (direct address)

(A) ¨ (A) XOR ((Rr))
(A) ¨ (A) XOR #data

(direct address) ¨ (direct address)
XOR (A)

(direct address) ¨ (direct address)
XOR #data

(A) ¨ #data

(Rr) ¨ #data

(direct address) ¨ #data

(Rr)) ¨ #data

(DPTR) ¨ #data 16

(C) ¨ 0
(C) ¨ 1
(C) ¨ (C)
(C) ¨ (C) AND (bit address)

(C) ¨ (C) AND (bit address)

(C) ¨ (C) OR (bit address)

(C) ¨ (C) OR (bit address)

17/38

¡ Semiconductor MSM80C31F/80C51F

Instruction Set Details (continued)

Type

Mnemonic

MOV C, bit

MOV bit, C

operation

Carry flag

instructions

SETB bit

CLR bit

instructions

Bit operation

CPL bit

MOV A, Rr
MOV A, direct

MOV A, @Rr
MOV Rr, A
MOV Rr,

direct
MOV direct, A

MOV direct,
Rr

Data transfer instructions

MOV direct 1,
direct 2

MOV @Rr, A
MOV @Rr,

direct
MOVC A,

@A+DPTR

Instruction code

D6 D5 D4 D3 D1

D

D

7

D0

2

10100010

b

7b6b5b4b3b2b1b0

10010010

b

7b6b5b4b3b2b1b0

11010010

b

7b6b5b4b3b2b1b0

11000010

b

7b6b5b4b3b2b1b0

10110010

b

7b6b5b4b3b2b1b0

11101r2r1r

0

11100101

a

7a6a5a4a3a2a1a0

1110011r
11111
10101

a

7a6a5a4a3a2a1a0

r2r1r
r2r1r

0

0

0

11110101

a

7a6a5a4a3a2a1a0

10001

a

7a6a5a4a3a2a1a0

10000

22222222

a

7a6a5a4a3a2a1a0
11111111

a7a6a5a4a3a2a1a

1111011r
10100

a

7a6a5a4a3a2a1a0

r2r1r

11r

11r

0

0

0

0

0

10010011

Bytes Cycles

21

22

21

21

21

11
21

11
11
22

21

22

32

11
22

12

Description

(C) ¨ (bit address)

(bit address) ¨ (C)

(bit address) ¨ 1

(bit address) ¨ 0

(bit address) ¨ (bit address)

(A) ¨ (Rr)
(A) ¨ (direct address)

(A) ¨ ((Rr))
(Rr) ¨ (A)
(Rr) ¨ (direct address)

(direct address) ¨ (A)

(direct address) ¨ (Rr)

(direct address 1) ¨ (direct address 2)

((Rr)) ¨ (A)
((Rr)) ¨ (direct address)

(A) ¨ ((A)+(DPTR))

MOVC A,

instructions

@A+PC

Constant code

XCH A, Rr
XCH A, direct

XCH A, @Rr

instructions

Data exchange

XCHD A, @Rr

10000011

11001

r2r1r

0

11000101

a

7a6a5a4a3a2a1a0

11000
11010

11r
11r

0

0

12

11
22

11
11

(PC) ¨ (PC+1)
(A) ¨ ((A)+(PC))

(A) ´ (Rr)
(A) ´ (direct address)

(A) ´ ((Rr))
(A

- 3) ´ ((Rr0 - 3))

0

18/38

¡ Semiconductor MSM80C31F/80C51F

Instruction Set Details (continued)

Type

Mnemonic

PUSH direct

POP direct

ACALL addr
11

LCALL addr
16

Subroutine instructions

RET

Instruction code

D

D6 D5 D4 D3 D1

D

7

D0

2

11000000

a7a6a5a4a3a2a1a

0

11010000

a7a6a5a4a3a2a1a

A

10A9A8

10001

A7A6A5A4A3A2A1A

0

0

00010010

A15A14A13A12A11A10A9A

A7A6A5A4A3A2A1A

8

0

00100010

Bytes Cycles

22

22

22

32

12

Description

(SP) ¨ (SP)+1
((SP)) ¨ (direct address)

(direct address) ¨ ((SP))
(SP) ¨ (SP)–1

(PC) ¨ (PC)+2
(SP) ¨ (SP)+1
((SP)) ¨ (PC

- 7)

0

(SP) ¨ (SP)+1
((SP)) ¨ (PC
(PC

- 10) ¨ A0 -

0

- 15)

8

10

(PC) ¨ (PC)+3
(SP) ¨ (SP)+1
((SP)) ¨ (PC

- 7)

0

(SP) ¨ (SP)+1
((SP)) ¨ (PC
(PC

- 10) ¨ A0 -

0

(PC

- 15) ¨ ((SP))

8

- 15)

8

10

(SP) ¨ (SP)–1
(PC

- 7) ¨ ((SP))

0

(SP) ¨ (SP)–1

RETI

AJMP addr 11

LJMP addr 16

SJMP rel

Jump instructions

JMP @A+
DPTR

00110010

A10A9A

00001

8

A7A6A5A4A3A2A1A

00000010

A15A14A13A12A11A10A9A

A7A6A5A4A3A2A1A

10000000

R7R6R5R4R3R2R1R

01110011

0

8

0

0

12

22

32

22

12

(PC

- 15) ¨ ((SP))

8

(SP) ¨ (SP)–1
(PC

- 7) ¨ ((SP))

0

(SP) ¨ (SP)–1

(PC) ¨ (PC)+2
(PC

- 10) ¨ A0 -

0

(PC

- 15) ¨ A0 -

0

10

15

(PC) ¨ (PC)+3
(SP) ¨ (SP)+1

(PC) ¨ (A)+(DPTR)

19/38

¡ Semiconductor MSM80C31F/80C51F

Instruction Set Details (continued)

Type

Mnemonic

CJNE A, direct,
rel

CJNE A, #data,
rel

CJNE Rr,
#data, rel

Branch instructions

Instruction code

D6 D5 D4 D3 D1

D

D

7

D0

2

10110101

a7a6a5a4a3a2a1a

R7R6R5R4R3R2R1R

0

0

10110100

I

7I6I5I4I3I2I1I0

R7R6R5R4R3R2R1R

10111r2r1r

I

7I6I5I4I3I2I1I0

R7R6R5R4R3R2R1R

0

0

0

Bytes Cycles

32

32

32

Description

(PC) ¨ (PC)+3
IF (A)π(direct address)
THEN

(PC) ¨ (PC)+relative offset
IF (A)<(direct address)
THEN
(C) ¨ 1

ELSE
(C) ¨ 0

(PC) ¨ (PC)+3
IF (A)π #data
THEN

(PC) ¨ (PC)+relative offset
IF (A)< #data
THEN
(C) ¨ 1

ELSE
(C) ¨ 0

(PC) ¨ (PC)+3
IF ((Rr))π #data
THEN

(PC) ¨ (PC)+relative offset
IF (Rr))< #data
THEN
(C) ¨ 1

ELSE
(C) ¨ 0

CJNE @Rr,
#data, rel

DJNZ Rr, rel

DJNZ direct,
rel

1011011r

I

7I6I5I4I3I2I1I0

R7R6R5R4R3R2R1R

11011r2r1r

R

7R6R5R4R3R2R1R0

0

0

0

11010101

a

7a6a5a4a3a2a1a0

R7R6R5R4R3R2R1R

0

32

22

32

(PC) ¨ (PC)+3
IF ((Rr))π #data
THEN

(PC) ¨ (PC)+relative offset
IF ((Rr))< #data
THEN
(C) ¨ 1

ELSE
(C) ¨ 0

(PC) ¨ (PC)+2
(Rr) ¨ (Rr)–1
IF (Rr)< 0
THEN
(PC) ¨ (PC)+relative offset

(PC) ¨ (PC)+3
(direct address) ¨ (direct address)–1
IF (direct address)π 0
THEN
(PC) ¨ (PC)+relative offset

20/38

¡ Semiconductor MSM80C31F/80C51F

Instruction Set Details (continued)

Type

Mnemonic

JZ rel

JNZ rel

JC rel

JNC rel

JB bit, rel

Branch instructions

JNB bit, rel

JBC bit, rel

Instruction code

D6 D5 D4 D3 D1

D

D

7

D0

2

01100000

R7R6R5R4R3R2R1R

0

01110000

R

7R6R5R4R3R2R1R0

01000000

R

7R6R5R4R3R2R1R0

01010000

R

7R6R5R4R3R2R1R0

00100000

b

7b6b5b4b3b2b1b0

R7R6R5R4R3R2R1R

0

00110000

b

7b6b5b4b3b2b1b0

R7R6R5R4R3R2R1R

0

00010000

b

7b6b5b4b3b2b1b0

R7R6R5R4R3R2R1R

0

Bytes Cycles

22

22

22

22

32

32

32

Description

(PC) ¨ (PC)+2
IF (A) = 0
THEN

(PC) ¨ (PC)+relative offset
(PC) ¨ (PC)+2

IF (A) π 0
THEN

(PC) ¨ (PC)+relative offset
(PC) ¨ (PC)+2

IF (C) = 1
THEN

(PC) ¨ (PC)+relative offset
(PC) ¨ (PC)+2

IF (C) = 0
THEN

(PC) ¨ (PC)+relative offset
(PC) ¨ (PC)+3

IF (bit address) = 1
THEN

(PC) ¨ (PC)+relative offset
(PC) ¨ (PC)+3

IF (bit address) = 0
THEN

(PC) ¨ (PC)+relative offset
(PC) ¨ (PC)+3

IF (bit address) = 1
THEN
(bit address) ¨ 0

(PC) ¨ (PC)+relative offset

External

memory

instructions

Other

instructions

MOVX A, @Rr
MOVX A,

@DPTR
MOVX @Rr, A

MOVX
@DPTR, A

NOP

1110000r

0

11100000

1111001r

0

11110000

00000000

12
12

12
12

11

(A) ¨ ((Rr)) EXTERNAL RAM
(A) ¨ ((DPTR)) EXTERNAL RAM

(Rr) ¨ (A) EXTERNAL RAM
((DPTP)) ¨ (A) EXTERNAL RAM

(PC) ¨ (PC)+1

21/38

¡ Semiconductor MSM80C31F/80C51F

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Rating Unit

Supply Voltage V
Voltage from Any Pin to V

SS

Storage Temperature T

CC

V

STG

I

Ta = 25°C
Ta = 25°C

—

–0.5 to +7.0 V

–0.5 to V

+7.0 V

CC

–55 to +150 °C

OPERATING RANGE

Parameter Symbol Condition Range Unit

Supply Voltage V
Memory Retention Voltage V
Oscillation Frequency f

OSC

Ambient Temperature Ta

CC

CC

See figure below

= Oscillation stop

OSC

MSM80C31F/51F

2.5 to 6 V

*1

2 to 6 Vf

DC to 16

*2
–40 to +85
–20 to +70MSM80C31F-1

MHzSee figure below

°C

*1 DC & AC characteristics in the range of 2.5 V £ VCC < 4 V will be specified by DC & AC

Characteristics 2.

*2 Specify MSM80C31F-1 when using MSM80C31F at 12 MHz to 16 MHz.

GUARANTEED OPERATING RANGE

Ta = –40 to +85°C (MSM80C31F/80C51F)

[ms]

10

5

4

Operating Range

3

2

Cycle Time (tcy)

1

Ta = –20 to +70°C (MSM80C31F-1)

1.2

3

6

MSM80C31/51
MSM80C31F/51F

12

)

OSC

Oscillation Frequency (f

0.75
MSM80C31F-1

23456

[V]

Supply Voltage (VCC)

16

22/38

¡ Semiconductor MSM80C31F/80C51F

ELECTRICAL CHARACTERISTICS

DC Characteristics 1

Parameter Symbol Condition Min. Typ. Max. Unit

Low Input Voltage V

High Input Voltage V

High Input Voltage V
Low Output Voltage
(Port 1, 2 and 3)
Low Output Voltage

V

(Port 0, ALE and PSEN)

High Output Voltage
(Port 1, 2 and 3)

High Output Voltage

V

(Port 0, ALE and PSEN)

Output Current at Low Input/

I

High Output Power Supply

IL

Output Current (Port 1, 2
and 3) at transition from
H to L

Input Leakage Current
(Floating Port 0 and EA)
RESET Pull-down Resistor R

Input Pin Capacitor C

Power Down Current I

V

V

MSM80C31F/51F V
MSM80C31F-1/51F-1 V

IL

Except XTAL1, RESET

IH

IH1

OL

OL1

OH

OH1

XTAL1, RESET and EA 0.7 V

and EA

I

OL

I

OL

I

OH

V

= 5 V ±10%

CC

I

OH

I

OH

I

= –400 mA

OH

V

= 5 V ±10%

CC

I

= –150 mA 0.75 V

OH

I

OH

VI = 0.45 V

/ I

OH

I

TL

I

RST

LI

V

IL

V

SS

Ta = 25°C, f = 1 MHz

IO

PD

5 V (except XTAL1)

V

CC

= 5 V ±20%, V

CC

= 5 V ±5%, V

CC

— –0.5 — V

0.2 V

+ 0.9 — V

CC

CC

= 1.6 mA — — V

= 3.2 mA — — V

= –60 mA

2.4 — V

= –30 mA 0.75 V
= –10 mA 0.9 V

CC

CC

2.4 — V

CC

= –40 mA 0.9 V

CC

–10 — mA

V

= 0.45 V

O

= 2.0 V — — mA

< VI < V

CC

—— mA

—2040 kW

—— pF

= 2 V — 1 mA

= 0 V, Ta = –40°C to +85°C

SS

= 0 V, Ta = –20°C to +70°C

SS

Meas-

uring

circuit

0.2 V

—V

– 0.1

CC

V

+ 0.5

CC

V

+ 0.5

CC

0.45

0.45
1

—

—V
—V

—
—

—

—V
—V

—
—

–200

2

–500

±10

125

10

50

3

2

—

4

23/38

¡ Semiconductor MSM80C31F/80C51F

DC Characteristics 2

(V

Parameter Symbol Condition Min. Typ. Max. Unit

Low Input Voltage V

High Input Voltage V

High Input Voltage V
Low Output Voltage
(Port 1, 2 and 3)
Low Output Voltage

V

(Port 0, ALE and PSEN)
High Output Voltage
(Port 1, 2 and 3)
High Output Voltage

V

(Port 0, ALE and PSEN)
Output Current at Low Input/

I

High Output Power Supply

IL

Output Current (Port 1, 2
and 3) at transition from
H to L

Input Leakage Current
(Floating Port 0 and EA)
RESET Pull-down Resistor R

Input Pin Capacitor C

Power Down Current I

V

V

IH1

OL1

OH

OH1

/ I

I

TL

I

RST

PD

IH

OL

LI

IO

IL

— –0.5 — V

Except XTAL1, RESET

and EA

XTAL1, RESET and EA 0.6V

I

= 10 mA—— V

OL

I

= 20 mA—— V

OL

I

= –5 mA 0.75 V

OH

I

= –20 mA 0.75 V

OH

VI = 0.1 V

OH

V

= 0.1 V

V

O

V

= 1.9 V — — mA

IL

< VI < V

SS

—2040 kW

Ta = 25°C, f = 1 MHz

5 V (except XTAL1)

——1 mA

CC

= 2.5 to 4.0 V, V

CC

0.25V

+ 0.9 — V

CC

+ 0.6 — V

CC

CC

CC

—— mA

—— mA

—— pF

= 0 V, Ta = –40 to +85°C)

SS

Meas-

uring

circuit

0.25V

– 0.1

CC

+ 0.5

V

CC

+ 0.5

V

CC

0.1
1

0.1

—V

—V

—

—

–100

2

–300

±10

125

10

10

3

2

—

4

24/38

¡ Semiconductor MSM80C31F/80C51F

Maximum operating power supply ICC [mA]

V

CC

2.5 V 3.0 V 4.0 V

Freq

0.7 0.9 1.60.5 MHz

1.9 2.4 4.33.0 MHz
— — 8.38 MHz
— — 12.012 MHz

Maximum IDLE power supply ICC [mA]

V

CC

Freq

2.5 V 3.0 V 4.0 V

0.3 0.4 0.60.5 MHz

0.6 0.8 1.23.0 MHz
— — 2.28 MHz
— — 3.112 MHz

25/38

¡ Semiconductor MSM80C31F/80C51F

Measuring Circuit

1

V

CC

V

IH

(*3)

INPUT

V

IL

V

SS

(*2)

OUTPUT

V A

(*1)

I

O

V

A

3

2

V

CC

INPUT

V

SS

4

OUTPUT

A

V

CC

V

IH

(*3)

INPUT

V

IL

V

SS

(*2)

OUTPUT

V A

V

CC

V

IH

(*3)

IL

V

V

INPUT

OUTPUT

SS

*1 Repeated for specified input pin.
*2 Repeated for specified output pin.
*3 Logic input for specified condition.

26/38

¡ Semiconductor MSM80C31F/80C51F

External Program Memory Access AC Characteristics 1

(V

= 5 V ±20%, VSS = 0 V, Ta = –40°C to +85°C; Load Capacitance for Port 0, ALE, and PSEN =

CC

100 pF ; Load Capacitance for all other outputs = 80 pF)

Variable Clock

Parameter Symbol

12 MHz Clock

See Guaranteed

Operating Range

Unit

XTAL1, XTAL2 Oscillation Cycle
ALE Signal Width t
Adderss Setup Time
(to ALE Falling Edge)
Adderss Hold Time
(from ALE Falling Edge)
Instruction Data Read Time
(from ALE Falling Edge)
From ALE Falling Edge to

PSEN Falling Edge
PSEN Signal Width t

Instruction Data Read Time
(from PSEN Falling Edge)
Instruction Data Hold Time
(from PSEN Rising Edge)
Bus Floating Time after Instruction
Data Read (from PSEN Rising Edge)
Address Output Time from
PSEN Rising Edge
Instruction Data Read Time
(from Address Output)
Bus Floating Time (Address
Float from PSEN Falling Edge)

t

CLCL

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

PXAV

t

AVIV

t

PLAZ

Min. Max.

——ns

126 — ns

43 — ns

Max.

—
—
—

48 — ns—1t

—4t

58 — ns—1t

215 — ns—3t

—3t

2t
1t

Min.

83.3

CLCL

CLCL

CLCL

CLCL

CLCL

– 40
– 40

– 35

– 25

– 35

CLCL

CLCL

– 100 ns233 —

– 105 ns145 —

0—ns—0

—1t

75 — ns—1t

CLCL

– 8

—5t

CLCL

CLCL

– 20 ns63 —

– 105 ns312 —

—0ns0—

27/38

¡ Semiconductor MSM80C31F/80C51F

External Program Memory Access AC Characteristics 2

(VCC = 2.5 to 4.0 V, V

= 0 V, Ta = –40°C to +85°C; Load Capacitance for Port 0, ALE, and PSEN

SS

= 100 pF ; Load Capacitance for all other outputs = 80 pF)

Parameter Symbol

XTAL1, XTAL2 Oscillation Cycle
ALE Signal Width t
Adderss Setup Time
(to ALE Falling Edge)
Adderss Hold Time
(from ALE Falling Edge)
Instruction Data Read Time
(from ALE Falling Edge)
From ALE Falling Edge to

PSEN Falling Edge
PSEN Signal Width t

Instruction Data Read Time
(from PSEN Falling Edge)
Instruction Data Hold Time
(from PSEN Rising Edge)
Bus Floating Time after Instruction
Data Read (from PSEN Rising Edge)
Address Output Time from
PSEN Rising Edge
Instruction Data Read Time
(from Address Output)
Bus Floating Time (Address
Float from PSEN Falling Edge)

t

CLCL

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

PXAV

t

AVIV

t

PLAZ

12 MHz Clock

Min. Max.

——ns

126 — ns

43 — ns

Max.

—
—
—

48 — ns—1t

—4t

58 — ns—1t

215 — ns—3t

—3t

0—ns—0

—1t

75 — ns—1t

—5t

—0ns0—

Variable Clock

See Guaranteed

Operating Range

Min.

83.3
– 40

2t

CLCL

– 40

1t

CLCL

– 35

CLCL

– 25

CLCL

– 35

CLCL

– 8

CLCL

Unit

– 100 ns233 —

CLCL

– 105 ns145 —

CLCL

– 20 ns63 —

CLCL

– 105 ns312 —

CLCL

28/38

¡ Semiconductor MSM80C31F/80C51F

External Program Memory Read Cycle

t

LHLL

ALE

PSEN

t

AVLL

A0~A7

t

t

LLAX

LLPL

t

AVIV

t

PLAZ

t

LLIV

t

PLIV

t

PLPH

t

PXIX

INSTR

IN

t

PXIZ

t

PXAV

A0~A7PORT0

PORT2

A8~A15 A8~A15 A8~A15

29/38

¡ Semiconductor MSM80C31F/80C51F

External Data Memory Access AC Characteristics 1

(V

= 5 V ±20%, VSS = 0 V, Ta = –40°C to +85°C; load capacitance for Port 0, ALE, and PSEN =

CC

100 pF ; load capacitance for all other outputs = 80 pF)

Variable Clock

Parameter Symbol

12 MHz Clock

See Guaranteed

Operating Range

Unit

XTAL1, XTAL2 Oscillation Cycle
ALE Single Width t
Adderss Setup Time
(to ALE Falling Edge)
Adderss Hold Time
(from ALE Falling Edge)

RD Single Width t
WR Single Width t

RAM Data Read Time
(from RD Single Falling Edge)
RAM Data Read Hold Time
(from RD Single Rising Edge)
Data Bus Floating Time
(from RD Single Rising Edge)
RAM Data Read Time
(from ALE Single Falling Edge)
RAM Data Read Time
(from Address Output)
RD/WR Output Time from
ALE Falling Edge
RD/WR Output Time from
Address Output
RD Output Time from Data Output
Time from Data Output to
WR Rising Edge
Data Hold Time (WR Rising Edge)
Time from RD Output to
Address Float
Time from RD/WR Rising
Edge to ALE Rising Edge

t

CLCL

LHLL

t

AVLL

t

LLAX

RLRH

WLWH

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

QVWX

t

QVWH

t

WHQX

t

RLAZ

t

WHLH

Min. Max.

——ns

126 — ns

43 — ns

48 — ns—1t

400 — ns—6t
400 — ns—6t

—5t

Max.

—
—
—

2t
1t

Min.

62.5

CLCL

CLCL

CLCL

CLCL

CLCL

– 40
– 40

– 35

– 100
– 100

CLCL

– 165 ns251 —

0—ns—0

—2t

—8t

—9t

200 3t

203 — ns—4t

23 — ns—1t

433 — ns—7t

33 — ns—1t

CLCL

CLCL

CLCL

CLCL

CLCL

– 50

– 130

– 60

– 150

– 50

CLCL

CLCL

CLCL

CLCL

– 70 ns96 —

– 150 ns516 —

– 165 ns585 —

+ 50 ns300 3t

—0ns0—

43 1t

CLCL

– 40

CLCL

+ 50 ns133 1t

30/38

¡ Semiconductor MSM80C31F/80C51F

External Data Memory Access AC Characteristics 2

(VCC = 2.5 to 4.0 V, V

= 0 V, Ta = –40°C to +85°C; load capacitance for Port 0, ALE, and PSEN =

SS

100 pF ; load capacitance for all other outputs = 80 pF)

Parameter Symbol

XTAL1, XTAL2 Oscillation Cycle
ALE Single Width t
Adderss Setup Time
(to ALE Falling Edge)
Adderss Hold Time
(from ALE Falling Edge)

RD Single Width t
WR Single Width t

RAM Data Read Time
(from RD Single Falling Edge)
RAM Data Read Hold Time
(from RD Single Rising Edge)
Data Bus Floating Time
(from RD Single Rising Edge)
RAM Data Read Time
(from ALE Single Falling Edge)
RAM Data Read Time
(from Address Output)
RD/WR Output Time from
ALE Falling Edge
RD/WR Output Time from
Address Output
RD Output Time from Data Output
Time from Data Output to
WR Rising Edge
Data Hold Time (WR Rising Edge)
Time from RD Output to
Address Float
Time from RD/WR Rising
Edge to ALE Rising Edge

t

CLCL

LHLL

t

AVLL

t

LLAX

RLRH

WLWH

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

QVWX

t

QVWH

t

WHQX

t

RLAZ

t

WHLH

12 MHz Clock

Min. Max.

——ns

126 — ns

43 — ns

48 — ns—1t

400 — ns—6t
400 — ns—6t

—5t

0—ns—0

—2t

—8t

—9t

150 3t

203 — ns—4t

23 — ns—1t

433 — ns—7t

33 — ns—1t
—0ns0—

43 1t

Max.

—
—
—

Variable Clock

See Guaranteed

Operating Range

Min.

62.5
– 40

2t

CLCL

– 40

1t

CLCL

– 35

CLCL

– 100

CLCL

– 100

CLCL

– 100

CLCL

– 130

CLCL

– 60

CLCL

– 150

CLCL

– 50

CLCL

– 40

CLCL

Unit

– 165 ns251 —

CLCL

– 70 ns96 —

CLCL

– 150 ns516 —

CLCL

– 165 ns585 —

CLCL

+ 50 ns300 3t

CLCL

+ 100 ns183 1t

CLCL

31/38

¡ Semiconductor MSM80C31F/80C51F

External Data Memory Read Cycle

t

t

RHDX

WHLH

t

RHDZ

ALE

PSEN

RD

t

LHLL

t

AVLL

t

LLWL

t

LLAXtRLAZ

t

LLDV

t

RLDV

t

RLRH

PORT 0

PORT 2

INSTR

IN

PCH A8~A15 PCH P2.0~P2.7 DATA A8~A15 DPHor A8~A15 PCH

A0~A7

PCL

External Data Memory Write Cycle

ALE

PSEN

A0~A7

Rr or DPL

t

LHLL

t

AVWL

t

LLWL

t

AVDV

t

WLWH

t

WHLH

A0~A7

PCL

WR

PORT 0

PORT 2

INSTR

IN

A8~A15

PCH

t

QVWH

DATA (ACC)

t

WHQX

A0~A7

PCL

A0~A7

PCL

t

AVLL

t

LLAX

A0~A7

Rr or DPL

t

AVWL

t

QVWX

A8~A15 PCH P2.0~P2.7 DATA A8~A15 DPHor A8~A15 PCH

32/38

¡ Semiconductor MSM80C31F/80C51F

Serial Port Timing (I/O Expansion Mode) AC Characteristics 1

Parameter Min.

Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid

MACHINE
CYCLE

ALE

SHIFT
CLOCK

OUTPUT
DATA

0

12345678

t

t

QVXH

01234567

XLXL

t

XHQX

(Ta = –40°C to +85°C ; V

Symbol

t

XLXL

t

QVXH

t

XHQX

t

XHDX

t

XHDV

10t

2t

12t

CLCL

CLCL

CLCL

– 133

– 117

0

—

= 5 V ±20% ; V

CC

Max.

—
—
—
—

10t

CLCL

– 133

SS

= 0 V)

Unit

ns
ns
ns
ns
ns

INPUT
DATA

t

XHDV

VALID VALID VALID VALID VALID VALID VALID VALID

t

XHDX

33/38

¡ Semiconductor MSM80C31F/80C51F

Serial Port Timing (I/O Expansion Mode) AC Characteristics 2

Parameter Min.

Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid

MACHINE
CYCLE

ALE

SHIFT
CLOCK

OUTPUT
DATA

0

12345678

t

t

QVXH

01234567

XLXL

t

XHQX

(Ta = –40°C to +85°C ; V

Symbol

t

XLXL

t

QVXH

t

XHQX

t

XHDX

t

XHDV

10t

2t

12t

CLCL

CLCL

CLCL

– 133

– 117

0

—

=2.5 to 4.0 V ; V

C C

Max.

10t

CLCL

—
—
—
—

– 133

SS

= 0 V)

Unit

ns
ns
ns
ns
ns

INPUT
DATA

t

XHDV

VALID VALID VALID VALID VALID VALID VALID VALID

t

XHDX

34/38

¡ Semiconductor MSM80C31F/80C51F

AC Characteristics Measuring Conditions

Input/output signal

V

OH

V

IH

V

IH

V

OH

TEST POINT

V

V

OL

IL

V

IL

V

OL

* The input signals in AC test mode are either VOH (logic "1") or VOL (logic "0") input signals

where logic "1" corresponds to a CPU output signal waveform measuring point in excess of
VIH, and logic "0" to a point below VIL.

Floating

Floating

V

OH

V

OL

V

IH

V

IL

V

IH

V

IL

* The port 0 floating interval is measured from the time the port 0 pin voltage drops below V

V

OH

V

OL

IH

after sinking to GND at 2.4 mA when switching to floating status from a "1" output, and from
the time the port 0 pin voltage exceeds VIL after connecting to a 400 mA source when
switching to floating status from a "0" output.

XTAL1 External Clock Input Waveform Conditions

Parameter

External Clock Frequency 1/t
High Time t
Low Time t
Rise Time t
Fall Time t

Symbol

CLCL

CHCX

CLCX

CLCH

CHCL

See Guaranteed Operating Range

Min. Max. Unit

DC 16 MHz
20 — ns
20 — ns
—20ns
—20ns

External clock waveform

– 0.5

V

CC

0.45 V

0.7V

CC

0.2VCC – 0.1
t

CHCX

t

CHCL

t

CLCX

Variable Clock

t

CLCH

t

CLCL

35/38

¡ Semiconductor MSM80C31F/80C51F

PACKAGE DIMENSIONS

(Unit : mm)

DIP40-P-600-2.54

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

6.10 TYP.

36/38

¡ Semiconductor MSM80C31F/80C51F

(Unit : mm)

QFP44-P-910-0.80-2K

Mirror finish

Package material
Lead frame material
Pin treatment
Solder plate thickness

Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

0.41 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

37/38

¡ Semiconductor MSM80C31F/80C51F

(Unit : mm)

QFJ44-P-S650-1.27

Mirror finish

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
Cu alloy
Solder plating
5 mm or more

2.00 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

38/38

E2Y0002-29-11

NOTICE

1. The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.

2. The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.

3. When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.

4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or

unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.

5. Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.

6. The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.

7. Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.

8. No part of the contents cotained herein may be reprinted or reproduced without our prior
permission.

9. MS-DOS is a registered trademark of Microsoft Corporation.

Copyright 1995 Oki Electric Industry Co., Ltd.

Printed in Japan