Page 1
E2L0037-17-Y1
¡ Semiconductor MSM548331
¡ Semiconductor
This version: Jan. 1998
Previous version: Dec. 1996
MSM548331
222,720-Word ¥ 12-Bit Field Memory
DESCRIPTION
The MSM548331 is a 2.7-Mbit, 768 bits ¥ 290 lines, Field Memory. Access is done line by line. The line
address must be set each time a line is changed.
More than two MSM548331s can be cascaded directly without any delay devices between them.
Cascading MSM548331s provides larger capacity and longer delay.
X serial address input enables random initial address setting of serial access in a page. Other than the
random address setting, MSM548331 has several types of address set modes such as line hold,
address jump to initial address and line increment.
Self refresh function releases the MSM548331 from being applied external refresh control clocks even
though it contains dynamic type memory cells. MSM548331 has write mask function or input enable
function (IE), and read-data skipping function or output enable function (OE).
The MSM548331 is especially designed for digital TVs and VTRs for consumer use and video
cameras.
The MSM548331 is not designed for high end use in such applications as medical systems,
professional graphics systems which require long term picture storage, data storage systems and
others.
FEATURES
• 768 ¥ 290 ¥ 12-bit configuration
• Line by line access
• X serial address inputs for random serial initial bit address
• Asynchronous operation
• Serial read and write cycle times
Read cycle: 30 ns
Write cycle: 30 ns
• Low operating supply voltage: 3.3 V ±0.3 V
• Self-refresh
• Various address reset mode for picture processing
• Write mask function (Input enable control)
• Data skipping function (Output enable control)
• Package:
44-pin 400 mil plastic TSOP (Type II)
(TSOPII44-P-400-0.80-K) (Product : MSM548331TS-K)
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¡ Semiconductor MSM548331
PIN CONFIGURATION (TOP VIEW)
V
SS
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
RCLK
RXAD
RADE/RX
RE
OE
DO0
DO1
V
CC
DO2
DO3
V
SS
DO4
DO5
1
2
3
4
5
6
7
8
9
10
44
DIN6
43
DIN7
42
DIN8
41
DIN9
40
DIN10
39
DIN11
38
WCLK
37
WXAD
36
WADE/RX
35
WR/TR
11RR 34 WE
12RXINC 33 WXINC
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
IE
DO11
DO10
V
CC
DO9
DO8
V
SS
DO7
DO6
V
CC
44-Pin Plastic TSOP (
(K Type)
II)
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¡ Semiconductor MSM548331
Pin Name
RCLK Read Port, Serial Read ClockRead Port, X Serial Address Strobes
RE Read Port, Read Enable
DO0 - 11 Read Port, Data Output—
RR —Read Port, Address Reset Mode Enable
RXINC —Read Port, X Address Increment
RADE/RX —
RXAD —Read Port, X Serial Address Data
OE Output Enable—
WCLK Write Port, Serial Write ClockWrite Port, X Serial Address Strobes
WE Write Port, Write Enable
DIN0 - 11 Write Port, Input Data—
WR/TR Write Port, Write Data Transfer
WXINC —Write Port, X Address Increment
WADE/RX —
WXAD —Write Port, X Serial Address Data
IE Input Enable—
V
CC
V
SS
Read Port, X Address Input Enable
Read Port, X Address Reset
Write Port, Address Reset Mode Enable
Write Port, X Address Input Enable
Write Port, X Address Reset
—
—
Power Supply Voltage (3.3 V)
Function
Serial Read/Write CycleAddress Setting Cycle
Ground (0 V)
Note: Same power supply voltage level must be provided to every VCC pin.
Same ground voltage level must be provided to every VSS pin.
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¡ Semiconductor MSM548331
4/23
BLOCK DIAGRAM
WCLK
Refresh
Counter
Write Buffer
Write Register
Memory Cell Array
768 ¥ 290 ¥ 12 bits
Read Register
D
OUT
Buffer
RCLK RE OE
12
DIN0 to DIN11
DO0 to DO11
12
WE WCLK IE
Memory
Controller
Read
Address Control
Write
Address Control
RCLK
WADE/RX
RADE/RX
WXAD
RXAD
WR/TR
RR
WXINC
RXINC
V
BB
Generator
X-Address
Decoder
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¡ Semiconductor MSM548331
PIN FUNCTION
READ RELATED
RCLK : Read Clock
RCLK is the read control clock input. Synchronized with RCLK's rising edge, serial read access from
read ports is executed when both RE and OE are high.
The internal counter for the serial read address is incremented automatically on the rising edge of
RCLK. In a read address set cycle, all the read address bits which were input from RXAD pin are
stored into internal address registers synchronized with RCLK. In this address set cycle, RADE/RX
must be held high and RR must be held low.
In the read address reset cycle, various read address reset modes can be set synchronously with
RCLK. These reset cycles work to replace complicated serial address control which requires many
RCLK clocks with a simple reset cycle control requiring only a single RCLK cycle. It greatly facilitates
memory access.
RE : Read Enable
RE is a read enable clock input. RE enables or disables both internal read address pointers and dataout buffers. When RE is high, the internal read address pointer is incremented synchronously with
RCLK. When RE is low, even if the RCLK is input, the internal read address pointer is not
incremented.
OE : Output Enable
OE is an output enable clock input. OE enables or disables data-outs. OE high level enables the
outputs. The internal read address pointer is always incremented by cycling RCLK regardless of OE
level.
DO0-11 : Data-Outs
DO0-11 are serial data-outs. Data is output synchronously with RCLK when OE is high. The output
enable/disable operation through OE input is performed synchronously with OE and asynchronously
with RCLK.
RR : Read Reset
RR is a read reset control input. Read address reset modes are defined when RR level is high
according to the "FUNCTION TABLE for read".
RXINC : Read X Address Increment
RXINC is a read X address (or line address) increment control input. In the read address reset cycle,
defined by RR high, the X address (or line address) is incremented by 1 when RXINC is pulled high
with RADE/RX low.
RADE/RX : Read Address Enable/Read X Address Reset Logic Function
RADE/RX is a dual function control input. RADE, one of the two functions of RADE/RX, is a read
address enable input. In the read address set cycle, defined by RR high, X address (or line address)
input from the RXAD pin are latched into internal read X address register synchronously with RCLK.
RX, the second function of RADE/RX, works as an element to set read X address (or line address)
reset mode. In an address reset mode cycle, defined by RR high, read X address is reset to 0 when
RADE/RX is pulled high with RXINC low.
RXAD : Read X Address
RXAD is a read X address (or line address) input. RXAD specifies the line address. 9 bits of read X
address data are input serially from RXAD.
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¡ Semiconductor MSM548331
WRITE RELATED
WCLK : Write Clock
WCLK is a write control clock input. Synchronized with WCLK's rising edge, serial write access into
write ports is executed when WE is high and IE is high.
According to WCLK clocks, the internal counter for the serial address is incremented automatically.
In a write address set cycle, all the write addresses which were input from WXAD are stored into
internal address registers synchronously with WCLK. In this address set cycle, WADE/RX must be
held high and WR/TR must be held low.
In the write address reset cycle, various write address reset modes can be set synchronously with
WCLK. These reset cycles replace complicated serial address control with simple reset cycle control
which requires only one WCLK cycle. It greatly facilitates memory access.
WE : Write Enable
WE is a write enable clock input. WE enables or disables both internal write address pointers and
data-in buffers. When WE is high, the internal write address pointer is incremented synchronously
with WCLK. When WE is low, even if WCLK is input, the internal write address pointer is not
incremented.
DIN0-11 : Data-Ins
DIN0-11 are serial data-ins. Corresponding data-in-buffers are masked by IE.
WR/TR : Write Reset/Write Transfer
WR/TR is a write reset control input. Write address reset modes are defined when WR/TR level is
high according to the "FUNCTION TABLE for write".
When the write operation on a line is terminated, be sure to perform a write transfer operation by
WR/TR in order to store the written data in the write register to corresponding memory cells.
WXINC : Write X Address Increment
WXINC is a write X address (or line address) increment control input. In the write address reset cycle,
defined by WR/TR high, the write X address (or line address) is incremented when WXINC and
WADE/RX are high.
WADE/RX : Write Address Enable/Write X Address Reset Logic Function
WADE/RX is a dual functional control input. WADE, one of the two functions of WADE/RX, is a
write address enable input. In the write address reset cycle, defined by WR/TR high, X address (or
line address) input from WXAD is latched into internal write X address register synchronously with
WCLK.
WXAD : Write X Address
WXAD is a write X address (or line address) input. WXAD specifies line address. 9 bits of write X
address data are input serially from WXAD.
IE : Input Enable
IE is an input enable which controls the write operation. When IE is high, the input operation is
enabled. When IE is low, the write operation is masked. When WE signal is high, and IE low, the
internal serial write address pointer is incremented on the rising edge of WCLK without actual write
operations. This function facilitates picture in picture function in a TV system.
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¡ Semiconductor MSM548331
OPERATION MODE
Write
1. Write operation
Before the write operation begins, X address (or line address) must be input to set the initial
bit address for the following serial write access. When WE and IE are high, a set of serial 12bit -width write data on DIN0-11 is written into write registers attached to the DRAM memory
arrays temporarily on the rising edge of WCLK.
Following 12-bit-width serial input data is written into the memory locations in the write
register designated by an internal write address pointer which is advanced by WCLK. This
enables continuous serial write on a line. When write clock WCLK and read clock RCLK are
tied together and are controlled by a common clock or CLK, more than two MSM548331s can
be cascaded directly without any delay devices between the MSM548331s because the read
timing is delayed by one CLK cycle to the write timing. When the write operation on a line is
terminated, be sure to perform a write transfer operation by WR/TR in order to store the
written data in the write registers to the corresponding memory cells in the DRAM memory
arrays.
2. Write address pointer increment operation
The write address pointer is incremented synchronously with WCLK when WE is high.
When WE and IE are high, the write operation is enabled.
If IE level goes low while WCLK is active, the write operation is halted but the write address
pointer will continue to advance. That is, IE enables a write mask function. When WE goes
low, the write address pointer stops without WCLK.
Read
1. Read operation
Before the read operation begins, the X address (or line address) must be input for setting
initial bit address for the following serial read access.
When both RE and OE are high, a set of serial 12-bit-width read data on DO0-11 pins is read
from read registers attached to DRAM memory arrays on the rising edge of RCLK.
Each access time is specified by the rising edges of RCLK.
Relationship between the WE and IE input levels,
Write Address pointer, and data input status
WCLK Rise
WE
H
H
L
IE
H
L
—
Internal Write
Address Pointer
Incremented
Stopped
Data Input
Inputted
Not Inputted
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¡ Semiconductor MSM548331
2. Read address pointer increment operation
The read address pointer is incremented synchronized with RCLK when OE level is high.
Relationship between the RE and OE input levels,
Read Address pointer, and data output status
RCLK Rise
RE
H
H
L
L L Hi-Z
OE
H
L
H
Internal Read
Address Pointer
Incremented
Stopped
Data Output
Outputted
Hi-Z
Outputted
When each read address pointer reaches the last address of a line, it stops at the last address
and no address increment occurs.
Initial Address Setting (Write/Read Independent)
Any read operations are prohibited in the read initial address set period. Similarly, any write
operations are prohibited in the write initial address set period. Note that read initial address set and
write initial address set can occur independently. Similarly, read access can be achieved independently
from write initial address set period and write access can be achieved independently from read initial
address set cycles.
1. Write address setting
WADE/RX enables initial read address inputs. When WADE/RX is high, 9 bits of serial X
address (or line address) are input from WXAD.
The operations above enable selection of specific lines randomly and enables the start of serial
write access synchronized with write clock WCLK. Address for each line must be input
between each line access. In other words, MSM548331's write is achieved in a "line by line"
manner. Any write operations are prohibited in the initial write address set periods.
Serial write input enable time t
must be kept for starting a serial write just after the initial
SWE
write address set period.
2. Read address setting
RADE/RX enables initial read address inputs.
When RADE/RX is high, 9 bits of serial X address (or line address) are input from RXAD.
The operations above enable selection of specific lines randomly and enables the start of serial
read access synchronized with read clocks, RCLK. Address for each line must be input
between each line access. In other words, MSM548331's read operation is achieved in "line by
line" manner.
Any read operations are prohibited in the initial read address set periods. Serial read
operations are prohibited while RADE/RX is high. Serial read port enable time t
must be
SRE
kept for starting a serial read just after the initial read address set period.
Initial Address Reset Modes (Write/Read Independent)
The initial address reset modes replace complicated read or write initial address settings with simple
reset cycles. Initial address reset modes are selected by RR high during read and WR/TR high during
write. As in normal read or write address settings, any read operations are prohibited in the read
address reset cycles. Similarly, any write operations are prohibited in the initial write address reset
cycles. Note that read initial address reset and write initial address reset can occur independently.
Similarly, read access can be achieved independently from write initial address reset cycles and write
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¡ Semiconductor MSM548331
access can be achieved independently from read initial address reset cycles.
Input addresses are stored into address registers which are connected with address counter which
controls address pointer operation. In the serial access operation, the input address into the address
registers are kept.
Serial write data input enable time t
and serial read port read enable time t
SWE
must be kept for
SRE
starting serial read or write just after the initial read or write address reset cycles.
Refer to the "FUNCTION TABLE" shown later.
1. Line hold operation (read only)
By the "Line hold operation" logic which is composed by a combination of control inputs' level,
access is executed starting from the first word on the current line.
2. Original address reset operation
By the "Original address reset" logic, the address counter is reset to (0,0). After the reset mode,
serial access starts from the address (0,0) .
The address counter is reset by this reset mode but the address register, which stored input
address in the previous address reset cycle or address set cycle, is not reset. The non-initialized
address can be used as a preset address in "address jump reset" mode.
3. Line increment operation
By the "Line increment operation" logic, the X address counter is incremented by one from the
current X address. That is, serial access from the Y = (0) on the next line is enabled.
4. Address jump operation
By the "Address jump operation" logic, a jump may be caused to the initialized line address.
Note :During one reset setting cycle, a plurality of resets cannot be set.
Power ON
Power must be applied to RCLK, RE, OE, WCLK, WE and IE input signals to pull them "Low" before
or when the VCC supply is turned on.
After power-up, the device is designed to begin proper operation in at least 200 ms after VCC has
reached the specified voltage. After 200 ms, a minimum of one line dummy write operation and read
operation is required according to the address setting mode, because the read and write address
pointers are not valid after power-up.
New Data Read Access
In order to read out "new data', the delay between the beginning of a write address setting cycle and
read address setting cycle must be at least two lines.
Old Data Read Access
In order to read out "old data", the delay between the beginning of a write address setting cycle and
read address setting cycle must be more than 0 but less than a half line.
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¡ Semiconductor MSM548331
FUNCTION TABLE
1. Write
Mode No.
Address Reset
Mode
Address Setting
Mode
Description of
Operation
1 Write Transfer H L L
2 Reset H L H
3 Line Increment H H L
4 Address Jump H H H
— First Address Setting L L H
WR/TR WXINC WADE/RX Internal Address Pointer
Note :For write, Line hold is not provided.
2. Read
Mode No.
Description of
Operation
X address cleared to (0, 0)
X address increment to (Xn +
1, 0)
X address jump to (Xi, 0)
X address set
RR RXINC RADE/RX Internal Address Pointer
Address Reset
Mode
Address Setting
Mode
1 Line Hold H L L
2 Reset H L H
3 Line Increment H H L
4 Adress Jump H H H
— First Address Setting L L H
X address holde to (Xn, 0)
X address cleared to (0, 0)
X address increment to (Xn +
1, 0)
X address jump to (Xi, 0)
X address set
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¡ Semiconductor MSM548331
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Symbol Condition Rating
Pin Voltage V
Short Circuit Output Current I
Power Dissipation P
Operating Temperature T
Storage Temperature
T
OS
D
opr
T
stg
Recommended Operating Conditions
Parameter Symbol Min.
Power Supply Voltage V
Power Supply Voltage V
"H" Input Voltage V
"L" Input Voltage V
CC
SS
IH
IL
Ta = 25°C, with respect to V
Ta = 25°C 50 mA
Ta = 25°C 1 W
— 0 to 70°C
— –55 to 150°C
Typ.
3.0
0
2.1
–0.5
3.3
V
0
CC
0
SS
Max.
V
CC
3.6
0
+ 0.3
0.8
–0.5 to 4.6 V
(Ta = 0 to 70°C)
Unit
V
V
V
V
DC Characteristics
Parameter Symbol Condition
"H" Output Voltage V
"L" Output Voltage V
Input Leakage Current I
Output Leakage Current I
Power Supply Current
(During Operation)
Power Supply Voltage
(During Standby)
Capacitance
Parameter Symbol
Input Capacitance C
Output Capacitance C
I
I
OH
OL
LI
LO
CC1
CC2
(V
= 3.0 to 3.6 V, Ta = 0 to 70°C)
CC
IOH = –0.1 mA
IOL = 0.1 mA
0 < VI < V
CC
Min.
2.2
—
–10
Max.
—
0.6
10
Unit
V
V
mA
Other input voltage 0 V
0 < VO < V
CC
min. cycle
Input pin = VIL/V
-50
IH
–10
—
—mA
10
50
10
mA
mA
(Ta = 25°C, f = 1 MHz)
Max.
I
O
7
7
Unit
pF
pF
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¡ Semiconductor MSM548331
AC Characteristics (1/2)
Parameter
WCLK Cycle Time
WCLK "H" Pulse Width
WCLK "L" Pulse Width
Serial Write Address Input Active Setup Time
Serial Write Address Input Active Hold Time
Serial Write Address Input Inactive Hold Time
Serial Write Address Input Inactive Setup Time
Write Transfer Instruction Setup Time
Write Transfer Instruction Hold Time
Write Transfer Instruction Inactive Hold Time
Write Transfer Instruction Inactive Setup Time
Serial Write X Address Setup Time
Serial Write X Address Hold Time
Serial Write Data Input Enable Time
Write Instruction Setup Time
Write Instruction Hold Time
Write Instruction Inactive Hold Time
Write Instruction Inactive Setup Time
Input Data Setup Time
Input Data Hold Time
WR/TR-WCLK Active Setup Time
WR/TR-WCLK Active Hold Time
WR/TR-WCLK Inactive Hold Time
WR/TR-WCLK Inactive Setup Time
WXINC-WCLK Active Setup Time
WXINC-WCLK Active Hold Time
WXINC-WCLK Inactive Hold Time
WXINC-WCLK Inactive Setup Time
WADE/RX-WCLK Active Setup Time
WADE/RX-WCLK Active Hold Time
WADE/RX-WCLK Inactive Hold Time
WADE/RX-WCLK Inactive Setup Time
IE Enable Setup Time
IE Enable Hold Time
IE Disable Setup Time
IE Disable Hold Time
Measurement Conditions: (V
Symbol
t
WCLK
WWCLH
WWCLL
WAS
WAH
WADH
WADS
WTRS
WTRH
WTDH
WTDS
WXAS
WXAH
SWE
WES
WEH
WEDH
WEDS
DS
DH
WRS
WRH
WRDH
WRDS
WINS
WINH
WINDH
WINDS
WRXS
WRXH
WRXDH
WRXDS
IES
IEH
IEDS
IEDH
= 3.3 V ±0.3 V, Ta = 0 to 70°C)
CC
Min.
30
13
13
5
7
7
7
5
7
7
7
5
7
3000
5
7
7
7
5
12
5
7
7
7
5
7
7
7
5
7
7
7
5
7
7
7
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
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¡ Semiconductor MSM548331
AC Characteristics (2/2)
Measurement Conditions: (VCC = 3.3 V ±0.3 V, Ta = 0 to 70°C)
RCLK Cycle Time
RCLK "H" Pulse Width
RCLK "L" Pulse Width
WRCLH
WRCLL
Serial Read Address Input Active Setup Time
Serial Read Address Input Active Hold Time
Serial Read Address Input Inactive Hold Time
t
Serial Read Address Input Inactive Setup Time
Serial Read X Address Setup Time
Serial Read X Address Hold Time
RE Enable Setup Time
RE Enable Hold Time
RE Disable Hold Time
RE Disable Setup Time
Read Port Read Enable Time
Read Port Read Data Hold Time
Access Time from RCLK
Read Data Hold Time from OE
Access Time from OE
RR-RCLK Active Setup Time
RR-RCLK Active Hold Time
RR-RCLK Inactive Hold Time
RR-RCLK Inactive Setup Time
RXINC-RCLK Active Setup Time
RXINC-RCLK Active Hold Time
RXINC-RCLK Inactive Hold Time
RXINC-RCLK Inactive Setup Time
RINDH
RINDS
RADE/RX-RCLK Active Setup Time
RADE/RX-RCLK Active Hold Time
RADE/RX-RCLK Inactive Setup Time
RADE/RX-RCLK Inactive Hold Time
RRXDS
RRXDH
Transition Time (Rise and Fall) nst
RCLK
t
RAS
t
RAH
RADH
RADS
RXAS
RXAH
RES
REH
REDH
REDS
SRE
OH
AC
DDOE
DEOE
RRS
RRH
RRDH
RRDS
RINS
RINH
RRXS
RRXH
T
Min.
30
13
13
5
7
7
7
5
7
5
7
7
7
3000
12
—
2
—
5
7
7
7
5
7
7
7
5
7
7
7
2
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30
—
20
—
—
—
—
—
—
—
—
—
—
—
—
30
UnitSymbolParameter
nst
nst
nst
ns
ns
ns
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
nst
Note : Measurement conditions
Input pulse level : VIH = 2.1 V, VIL = 0.8 V
Input timing reference level : VIH = 2.1 V, VIL = 0.8 V
Output timing reference level : VOH = 2.2 V, VOL = 0.6 V
Input rise/fall time : 2 ns
Load condition : C L = 30 pF (Oscilloscope and tool capacity included)
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¡ Semiconductor MSM548331
14/23
TIMING WAVEFORM
Write Cycle (Address Setting Cycle)
WCLK
t
WCLK
t
WWCLL
t
WWCLH
t
WADH
t
WAS
t
WAHtWADS
Valid
A7
Valid
A1
Valid
A0
Valid
A8
Valid Valid
Low
Low
t
WXAS
t
WXAH
t
WEDH
t
WES
t
IEDH
t
IES
WADE/RX
WXAD
WE
IE
WR/TR
WXINC
DIN0 - 11
t
DS
t
DH
t
DS
t
DH
t
SWE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
t
WXAH
t
WXAS
t
WXAH
t
WXAS
t
WXAH
t
WXAS
Page 15
¡ Semiconductor MSM548331
Write Cycle (WE Control)
WCLK
WADE/RX
IE
WR/TR
WXINC
WE
DIN0 - 11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Valid
D(N-3)
Valid
D(N-2)
Valid
D(N)
t
WEDH
t
WCLK
t
WES
N CYCLE(N-1)CYCLE(N-2)CYCLE (N+2) CYCLE(N+1) CYCLE
t
t
WEH
WEDS
Valid
D(N-1)
Valid
D(N+1)
Low
High
Low
Low
Valid
D(N+2)
Note : In the WE =" L" cycle, the write address pointer is not incremented and no DIN data is written.
Write Cycle (IE Control)
t
WCLK
Low
High
Low
Low
WCLK
WADE/RX
WE
WR/TR
WXINC
IE
—
—
—
—
—
—
—
—
—
—
—
—
N CYCLE(N-1)CYCLE(N-2)CYCLE (N+3) CYCLE(N+2) CYCLE
t
IEHtIEDStIEDHtIES
DIN0 - 11
—
—
Valid
D(N-3)
Valid
D(N-2)
Valid
D(N-1)
Valid
D(N)
Valid
D(N+2)
Valid
D(N+3)
Note : In the IE = "L" cycle, the write address pointer is incremented, though no DIN data is written
and the memory data is held.
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Page 16
¡ Semiconductor MSM548331
Write Cycle (Write Transfer)
N CYCLE(N-1)CYCLE(N-2)CYCLE
t
WCLK
—
WCLK
—
—
WADE/RX
—
—
t
WTRStWTRH
t
WTDH
t
WTDS
Low
WR/TR
—
—
WXINC
—
t
WEH
t
WEDS
Low
—
WE
—
DIN0 - 11
—
—
Valid
D(N-3)
Valid
D(N-2)
Valid
D(N-1)
Valid
D(N)
Note : When finishing the write operation on a line, be sure to perform a write transfer operation
because the write data on the line is stored in the memory cell.
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Page 17
¡ Semiconductor MSM548331
17/23
Read Cycle (Address Setting Cycle)
RCLK
,
,
t
RCLK
t
WRCLL
t
WRCLH
t
RADH
t
RAS
t
RAHtRADS
Valid
B7
Valid
B1
Valid
B0
Valid
B8
Valid Valid
Low
Low
High-Z
t
RXAS
t
RXAH
t
REDH
t
RES
RADE/RX
RXAD
RE
RR
RXINC
DO0 - 11
t
AC
t
OH
t
SRE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
t
RXAH
t
RXAS
t
RXAH
t
RXAS
t
RXAH
t
RXAS
Page 18
¡ Semiconductor MSM548331
Read Cycle (RE Control)
RCLK
RADE/RX
RR
RXINC
RE
DO0 - 11
OE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Valid
D(N-3)
N CYCLE(N-1)CYCLE(N-2)CYCLE (N+2) CYCLE(N+1) CYCLE
t
RCLK
Low
Low
Low
t
REHtREDStREDHtRES
t
OH
Valid
D(N-2)
Valid
D(N-1)
Valid
D(N)
t
AC
Valid
D(N+1)
Valid
D(N+2)
High
Note :In the cycle of RE = "L", the read address pointer is not incremented and the data at the address
is output continuously.
Read Cycle (OE Control)
t
DDOE
t
RCLK
High-Z
t
DEOEtAC
Valid
D(N+2)
Low
Low
Low
Valid
D(N+3)
RCLK
RADE/RX
RR
RXINC
OE
DO0 - 11
—
—
—
—
—
—
—
—
—
—
—
—
Valid
D(N-3)
N CYCLE(N-1)CYCLE(N-2)CYCLE (N+3) CYCLE(N+2) CYCLE
t
OH
Valid
D(N-2)
Valid
D(N-1)
Valid
D(N)
—
RE
High
—
Note : In the cycle of OE = "L", the read address pointer is incremented and the output enters the high
impedance state.
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Page 19
¡ Semiconductor MSM548331
Write Reset Mode
t
WCLK
t
WWCLL
—
WCLK
WADE/RX
WR/TR
WXINC
WE
DIN0 - 11
—
—
—
—
—
—
—
—
—
—
—
t
WWCLH
t
WRXDH
t
WRDH
t
t
WRXS
t
WRStWRH
WRXH
t
WRXDS
t
WRDS
t
SWE
t
WEDH
t
WES
t
DS
t
t
DS
DH
Valid Valid
Low
t
DH
Note :Both the line address and word address are reset to 0.
Write Line Increment Mode
t
WCLK
t
WWCLL
—
WCLK
WADE/RX
WR/TR
WXINC
WE
DIN0 - 11
—
—
—
—
—
—
—
—
—
—
—
t
WWCLH
t
WRDH
t
WINDH
t
t
t
WRS
WINStWINH
WRH
t
WRDS
t
WINDS
t
SWE
t
WEDH
t
WES
t
DS
t
t
DS
DH
Valid Valid
t
DH
Note :The line address is incremented by 1 and the word address is reset to 0.
19/23
Page 20
¡ Semiconductor MSM548331
Write Address Jump Mode
t
WCLK
t
WWCLL
—
WCLK
WADE/RX
WR/TR
WXINC
WE
DIN0 - 11
—
—
—
—
—
—
—
—
—
—
—
t
WWCLH
t
WRXDH
t
WRDH
t
WINDH
t
t
t
WRS
WRXH
t
WRH
WRXS
t
WINStWINH
t
WRXDS
t
WRDS
t
WINDS
t
SWE
t
WEDH
t
WES
t
DS
t
t
DS
DH
Valid Valid
t
DH
Note :The line address is reset to the initialized addresses and the word address is reset to 0.
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Page 21
¡ Semiconductor MSM548331
Read Line Hold Mode
t
RCLK
t
WRCLL
—
RCLK
RADE/RX
RR
RXINC
RE
DO0 - 11
—
—
—
—
—
—
—
—
—
—
—
t
WRCLH
t
RRDH
t
RRStRRH
t
RRDS
t
SRE
t
REDH
t
RES
Low
Low
t
AC
t
OH
Valid Valid
—
OE
—
Note :The line address is held and the word address is reset to 0.
Read Reset Mode
t
RCLK
t
WRCLL
—
RCLK
RADE/RX
RR
RXINC
RE
DO0 - 11
—
—
—
—
—
—
—
—
—
—
—
t
WRCLH
t
RRXDH
t
RRDH
t
RRXS
t
RRStRRH
t
RRXH
t
RRXDS
t
RRDS
t
SRE
t
REDH
t
RES
High
Low
t
AC
t
OH
Valid Valid
—
OE
—
Note :Both the line address and word address are reset to 0.
High
21/23
Page 22
¡ Semiconductor MSM548331
Read Line Increment Mode
t
RCLK
t
WRCLL
—
RCLK
RADE/RX
RR
RXINC
RE
DO0 - 11
—
—
—
—
—
—
—
—
—
—
—
t
WRCLH
t
RRDH
t
RINDH
t
t
t
RRS
RINStRINH
RRH
t
RRDS
t
RINDS
t
SRE
t
REDH
t
RES
Low
t
AC
t
OH
Valid Valid
—
OE
—
Note :The line address is incremented by 1 and the word address is reset to 0.
Read Address Jump Mode
t
RCLK
t
WRCLL
—
RCLK
RADE/RX
RR
RXINC
RE
DO0 - 11
—
—
—
—
—
—
—
—
—
—
—
t
WRCLH
t
RRXDH
t
RRDH
t
RINDH
t
t
RRXS
t
RRS
t
RINStRINH
RRXH
t
RRH
t
RRXDS
t
RRDS
t
RINDS
t
SRE
t
REDH
t
RES
t
AC
Valid Valid
High
t
OH
—
OE
High
—
Note :The line address is reset to the initialized addresses and the word address is reset to 0.
22/23
Page 23
¡ Semiconductor MSM548331
PACKAGE DIMENSIONS
(Unit : mm)
TSOPII44-P-400-0.80-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.54 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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