Datasheet MSM5299CGS-K, MSM5299CGS-BK Datasheet (OKI)

E2B0021-27-Y2

¡ Semiconductor

This version: Nov. 1997

Previous version: Mar. 1996

MSM5299C¡ Semiconductor

MSM5299C

80-DOT LCD SEGMENT DRIVER

GENERAL DESCRIPTION

The MSM5299C is a dot matrix LCD segment driver LSI which is fabricated using CMOS low
power metal gate technology. This LSI consists of an 80-bit bidirectional shift register, 80-bit
latch, 80-bit level shifter, and 80-bit 4-level driver.
It receives the 4-bit parallel display data transferred from a microcomputer or an LCD controller
LSI such as MSM6255, then outputs the LCD driving waveform to the LCD.
This LSI is improved with respect to timing between load and clock in the switching character­istics of MSM5299A. (tLC = 200ns Æ 63ns)
However, note that the timing regulations for the load signal leading edge are added.

FEATURES

• Logic supply voltage : 4.5 to 5.5V

• LCD driving voltage : 8 to 28V

• Applicable LCD duty : 1/64 to 1/256

• LCD Output : 80

• 4-bit parallel data processing has improved the transfer speed to 1/4 that of the conventional
serial transfer, thereby achieving low power consumption

• Can be interfaced with the LCD controller LSI MSM6255

• Applicable common driver : MSM5298A (68 outputs)

• Package options :
100-pin plastic QFP (QFP100-P-1420-0.65-K) (Product name : MSM5299CGS-K)
100-pin plastic QFP (QFP100-P-1420-0.65-BK) (Product name : MSM5299CGS-BK)

1/11

BLOCK DIAGRAM

MSM5299C¡ Semiconductor

V

V

V

V

EE

DF

DISP OFF

LOAD

O1O

2

1

3

O79O

80

80-Bit 4-Level Driver

V

4

DD

V

EE

80-Bit Level Shifter

V

DD

80-Bit Latch (Edge Trigger D-F/F)

V

SS

D
D
D
D

CP

EL

0

1

2

3

4 x 20-Bit Bidirectional Shift Register

SHIFT CP

SHL

V

DD

V

SS

CONTROL

CIRCUIT

ER

2/11

PIN CONFIGURATION (TOP VIEW)

MSM5299C¡ Semiconductor

50

9998979695949392919089

100

1

O

51

O

2

52

O

3

53

O

4

54

O

5

55

O

6

56

O

7

57

8

O

58

9

O

59

O

10

60

11

O

61

12

O

62

13

O

63

O

14

64

O

15

65

16

O

66

17

O

67

18

O

68

O

19

69

O

20

70

21

O

71

22

O

72

23

O

73

O

24

74

O

25 56

75

O

26

76

O

27

77

O

28

78

O

29

79

O

30

80

46

O48O49O

O47O

43

45

42

O

O

O44O

O41O40O39O

38

88

O37O36O

878685

35

34

O

O33O32O

838281

31

80

O

30

O

79

29

78

O

28

O

77

27

O

76

26

75

O

25

O

74

24

O

73

23

O

72

22

O

71

21

O

70

20

69

O

19

O

68

18

67

O

17

O

66

16

O

65

15

64

O

14

O

63

13

62

O

12

O

61

11

O

60

10

59

O

9

O

58

8

57

O

7

O

6

55

O

5

54

O

4

53

O

3

52

O

2

51

O

1

31323334353637383940414243

ER

NC

EE

V

V4V3V

1

NC

DF

DD

V

SHL

444546

1

3

SS

D2D

D

V

D

0

484950

47 84

CP

NC

EL

LOAD

DISP OFF

NC : No connection

100-Pin Plastic QFP

Note : The abbreviated part number "M5299C" is imprinted on the package surface.

3/11

MSM5299C¡ Semiconductor

ABSOLUTE MAXIMUM RATINGS

Parameter

Supply Voltage (1)

Supply Voltage (2)

Input Voltage

Storage Temperature

*1 V

DD≥V1>V3>V4>VEE

Symbol Condition Rating Unit

V

DD

V

LCD

V

STG

I

Ta = 25°C, VDD–V

RECOMMENDED OPERATING CONDITIONS

Parameter

Supply Voltage (1)

Supply Voltage (2)

Operating Temperature

*1 V

DD≥V1>V3>V4>VEE

Symbol Condition Range Unit

V

DD

V

LCD

T

op

Ta = 25°C

Ta = 25°C

—

—

V

DD–VEE

—

EE

*1

*1

–0.3 to +6

0 to 30

–0.3 to V

–55 to +150T

4.5 to 5.5

8 to 28

–20 to +85

DD

+0.3

(V

(V

SS

SS

= 0V)

V

V

V

°C

= 0V)

V

V

°C

4/11

ELECTRICAL CHARACTERISTICS

DC Characteristics

MSM5299C¡ Semiconductor

= 5V ± 10%, Ta = –20 to +85°C)

(V

DD

Parameter Symbol Condition

*1

"H" Input Voltage

V

IH

*1

"L" Input Voltage

V

IL

*1

"H" Input Current

I

IH

= VDD, VDD = 5.5V

V

IH

*1

L" Input Current

I

IL

= 0V, VDD = 5.5V

V

IL

*2

"H" Output Voltage

V

OH

I

= –0.2mA, VDD = 4.5V

O

*2

"L" Output Voltage

ON Resistance

Stand-by Current

Supply Current (1)

Supply Current (2)

V

OL

R

ON

I

DDSBY

I

DD1

I

I

= 0.2mA, VDD = 4.5V

O

V

V

*4

V

–

DD

VO

V

–

N

f

= 1MHz, V

CP

V

V

–

DD

f

= 1MHz, V

CP

V

V

–

DD

f

= 1MHz, V

CP

V

V

–

DD

EE

EE

EE

EE

23V

=

=

0.25V,

26

=

26

=

26V,

=

—

—

DD

no load

V,

DD

no load

V,

DD

no load

V

DD

= 5.5V

= 5.5V

= 5.5V

= 4.5V

*3

*5

*6

*7

Min. Typ. UnitMax.

0.8V

V

DD

V

—

—

—

—

—

—

—

DD

SS

– 0.4

—

—

—

—

—

—

—

—

—

—

0.2V

V

DD

1

–1

—

0.4

4

200

3

±100

DD

V

V

mA

mA

V

V

kW

mA

mA

mA

Input Capacitance

C

I

f = 1MHz

—

5

—

pF

*1 Applicable to LOAD, CP, D0 to D3, EL, ER, SHL, DF, DISP OFF pins
*2 Applicable to EL, ER pins.

*3 VN = VDD to V

EE, V4

15

13

= (VDD – VEE), V3 = (VDD – VEE), VDD = V

2

15

1

*4 Applicable to O1 to O80 pins.
*5 Display data 1010, fDF = 40 Hz, current that flows from VDD to VSS when the display data is

not clocked in.

*6 Display data 1010, fDF = 40 Hz, current that flows from VDD to VSS when the display data is

clocked in.

*7 Display data 1010, fDF = 40 Hz, current that flows to each of the V1, V3 and V4 pins.

5/11

Switching Characteristics

Parameter

Clock Frequency

Clock, Load Pulse Width

Clock Pulse Rise/Fall Time

Data Setup Time

Data Hold Time

Clock Æ Load Time

Load Setup Time

Load Setup Time

Load Æ Clock Time

Propagation Delay Time
ER, EL Setup Time

Symbol

f

CP

t

W

tr, t

f

t

DSU

t

DHD

t

CL

t

LSU1

t

LSU2

t

LC

t

PHL

t

ESU

= 5V ± 10%, Ta = –20 to +75°C, CL = 15pF)

(V

DD

Condition Min. Typ.

DUTY=50% — —

— 100 —

Max.

3.4

—

———50ns

—50—

—80—

—63—

—90—

—90—

—63—

———

—70—

—

—

—

—

—

—

224

—

MSM5299C¡ Semiconductor

Unit

MHz

ns

ns

ns

ns

ns

ns

ns

ns

ns

CP

- D

D

0

3

LOAD

CP

LOAD

ER, EL (Output)

0.8V

t

r

0.2V

0.8V

t

f

0.8V

DD

DD

0.2V

DD

DD

t

W

t

LC

DD

t

DD

t

DSU

0.2V

0.2V

DD

DD

DD

f

0.2V
t

0.8V

0.2V

t

DHD

r

DD

DD
DD

0.8V

t

W

t

LSU1

t

LSU2

DD

t

W

t

W

0.8V

0.8V

t

CL

1 2 19 20

0.8V

0.2V

0.2V

t

DD

PHL

DD

DD

0.8V

DD

EL, ER (Input)

t

ESU

0.2V

DD

6/11

FUNCTIONAL DESCRIPTION

Pin Functional Description

• ER, EL

MSM5299C¡ Semiconductor

Pin Input/Output

ER

EL

Input

Output

SHL

L

Input pin to ENABLE F/F of MSM5299C.
Output pin of ENABLE F/F. EL is connected to next MSM5299C's
ER when MSM5299Cs are connected in series (cascade

Description

connection).

EL

ER

Input

Output

Input pin to ENABLE F/F of MSM5299C.
Output pin of ENABLE F/F. ER is connected to next MSM5299C's

H

EL when MSM5299Cs are connected in series (cascade

connection).

When a single MSM5299C device is used, ER (EL) should be set at "L" level.

When a cascade connection is required, set the first MSM5299C's ER (EL) pin at "L" level and
connect the next MSM5299C's EL (ER) pin to the further next MSM5299C's ER (EL) pin.

•CP

Clock pulse input pin for the 4-bit parallel shift register. The data is shifted to the 4-bit parallel
shift register at the falling edge of the clock pulse.

• SHL

ER and EL can be used as either an input pin or an output pin based on the H/L condition of
SHL. The shift direction of each data (D0 to D3), the Input/Output condition of ER and EL
and the H/L condition of SHL are described in the table below.

SHL

L

H

ER

Input

Output

EL

Output

Input

Shift direction

D

0

D

1

D

2

D

3

D

0

D

1

D

2

D

3

O

1

O

2

O

3

O

4

O

80

O

79

O

78

O

77

end data

O

5

O

6

O

7

O

8

O

76

O

75

O

74

O

73

O

77

O

78

O

79

O

80

O

4

O

3

O

2

O

1

start data

7/11

MSM5299C¡ Semiconductor

•D0, D1, D2, D

3

Display data input pins for 4¥20-bit shift register. The display data is clocked into these pins.
The combinations of D0 to D3, DF signal level, display data output level and the display on
the LCD panel are described in the table below.

D0 - D

L

H

L

H

3

DF

L

L

H

H

Liquid crystal drive output

EE

)

3

)

1

)

4

)

Non-select level (V

Select level (V

Non-select level (V

Select level (V

Liquid crystal dispaly

OFF

ON

OFF

ON

• LOAD

The signal for latching the shift register contents is input to this pin. The display data stored
in the shift register is latched at the falling edge of the LOAD pulse.

•DF

Alternate signal input pin for LCD driving. Frame inversion signal is input to this pin.

•VDD, V

SS

Supply voltage pins. VDD should be 4.5 to 5.5V. VSS is a ground pin (VSS = 0V).

•V1, V3, V4, V

EE

Bias supply voltage pin to drive the LCD. Bias voltage to drive the LCD is supplied from an
external source.

8/11

MSM5299C¡ Semiconductor

•O1 to O

80

Display data output pins which correspond to the respective latch contents. One of V1, V3,
V4 and VEE is selected as a display driving voltage source based on the combination of the
latched data level and DF signal. (Refer to the Truth Table).
The outputs O1 to O80 are connected to the segment side of the LCD panel.

• DISP OFF

Input pin for controlling the outputs of O1 to O80. V1 level is output from O1 to O80 pins during
"L" level input. Refer to the Truth Table.

Truth Table

DF

L

L

H

H

X

Latched data DISP OFF Driver output level (O

L

H

L

H

X

H

H

H

H

L

V

3

V

1

V

4

V

EE

V

1

1-O80

)

NOTES ON USE

Note the following when turning power on and off :
The LCD drivers of this IC require a high voltage. For this reason, if a high voltage is applied to
the LCD drivers with the logic power supply floating, excess current flows. This may damage
the IC. Be sure to carry out the follwing power-on and power-off sequences :

When turning power on :
First VDD ON, next VEE, V4, V3, V1 ON. Or both ON at the same time.
When turning power off :
First VEE, V4, V3, V1 OFF, next VDD OFF. Or both OFF at the same time.

9/11

PACKAGE DIMENSIONS

QFP100-P-1420-0.65-K

Mirror finish

MSM5299C¡ Semiconductor

(Unit : mm)

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

1.29 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

10/11

QFP100-P-1420-0.65-BK

Mirror finish

MSM5299C¡ Semiconductor

(Unit : mm)

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

1.29 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

11/11