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MSM5298AGS-K
Datasheet (OKI)
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Datasheet MSM5298AGS-K, MSM5298AGS-BK Datasheet (OKI)

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Page 1
E2B0028-27-Y2
¡ Semiconductor
This version: Nov. 1997
Previous version: Mar. 1996
MSM5298A¡ Semiconductor
MSM5298A
68-DOT COMMON DRIVER
GENERAL DESCRIPTION
The MSM5298A is a dot matrix LCD common driver LSI which is fabricated using low power CMOS metal gate technology. This LSI consists of 68-bit bidirectional shift register, 68-bit level shifter and 68-bit 4-level driver. This LSI has 68 output pins to be connected to the LCD. By connecting two or more MSM5298As in series, this LSI is applicable to a wide LCD panel.
• Supply voltage : 4.5 to 5.5V
• LCD driving voltage : 8 to 28V
• Applicable LCD duty : 1/64 to 1/256
• Applicable segment driver : MSM5299A (80 outputs), MSM5299C (80 outputs)
• Package options: 80-pin plastic QFP (QFP80-P-1420-0.80-K) (Product name : MSM5298AGS-K) 80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name : MSM5298AGS-BK)
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Page 2
BLOCK DIAGRAM
MSM5298A¡ Semiconductor
V
V
V
V
DF
DISP OFF
SHL IO CP
O
1O2
1
2
5
EE
68-Bit 4-Level Driver
O67O
68
V
DD
V
EE
68-Bit Level Shifter
V
DD
V
SS
1
68-Bit Bidirectional Shift Register
IO
68
V
DD
V
SS
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Page 3
PIN CONFIGURATION (TOP VIEW)
MSM5298A¡ Semiconductor
43
39
O41O42O
O40O
36
38
35
O
O
O37O
O34O33O32O
31
80797877767574737271706968
1
O
44
O
2
45
3
O
46
4
O
47
O
5
48
6
O
49
7
O
50
8
O
51
9
O
52
10
O
53
11
O
54
12
O
55
13
O
56
14
O
57
15
O
58
16
O
59
17
O
60
18
O
61
19
O
62
20
O
63
21
O
64
22
O
65
23
O
66
24
O
67
O30O29O
676665
28
O
64
27
O
63
26
62
O
25
O
61
24
O
60
23
O
59
22
O
58
21
O
57
20
O
56
19
O
55
18
O
54
17
53
O
16
O
52
15
51
O
14
O
50
13
O
49
12
48
O
11
O
47
10
46
O
9
O
45
8
O
44
7
43
O
6
O
42
5
41
O
4
CP
383940
1
O1O2O
IO
3
25
26
27
28
29
30
31323334353637
5
2
68
68
EE
V
O
IO
1
V
V
V
SS
DD
V
SHL
DF
V
DISPOFF
80-Pin Plastic QFP
Note: The abbreviated part number "M5298A" is imprinted on the package surface.
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Page 4
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Condition Rating Unit
MSM5298A¡ Semiconductor
= 0 V)
(V
SS
Supply Voltage (1) V
Supply Voltage (2) V
Input Voltage
Storage Temperature T
*1 V
DD≥V1>V2>V5>VEE
DD
LCD
V
STG
I
Ta = 25°C –0.3 to +6 V
Ta = 25°C, VDD–V
Ta = 25°C –0.3 to V
— –55 to +150 °C
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol
Supply Voltage (1)
Supply Voltage (2)
Operating Temperature
*1 V
DD≥V1>V2>V5>VEE
V
DD
V
LCD
T
op
Condition
—
V
V
–
DD
EE
— –20 to +85
ELECTRICAL CHARACTERISTICS
1
*
EE
1
*
0 to +30 V
+0.3 V
DD
(V
Range
4.5 to 5.5
8 to 28
Unit
V
V
= 0 V)
SS
°C
DC Characteristics
(V
= 5V±10%, Ta = –20 to +85°C)
DD
Parameter Symbol Condition Min. Typ. Max. Unit
*1
V
IH
*1
V
IL
*1
I
IH
I
IL
V
OH
V
OL
R
ON
I
DD
C
I
*1
*2
*2
*4
V
VI= 0V, V
I
I
V
|V
f
V
f
= VDD, V
I
= –0.4mA, V
O
= 0.4mA, V
O
– V
DD
– VO|
N
=
CP
– V
DD
1MHz
=
— 0.8V
—V
DD
DD
23V, V
=
EE
0.25V
=
14kHz, V
23V, No load
=
EE
= 5.5V
= 5.5V
DD
= 4.5V
DD
= 5.5V
DD
= 4.5V
=
DD
4.5V
—— 1
——–1
VDD – 0.4 — — V"H" Output Voltage
— — 0.4 V"L" Output Voltage
— 1.5 3 k
*3
— — 100
—5—pFInput Capacitance
SS
DD
—VDDV"H" Input Voltage
— 0.2V
*1 Applicable to CP, IO1, IO68, SHL, DF, DISP OFF. *2 Applicable to IO1, IO68. *3 VN = VDD to VEE, V2 = (VDD – VEE), V5 = (VDD – VEE), VDD = V *4 Applicable to O1 to O68.
1
15
14 15
DD
V"L" Input Voltage
mA"H" Input Current
mA"L" Input Current
WON Resistance
mASupply Current
1
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Page 5
Switching Characteristics
Parameter Symbol Condition Min. Typ. Max. Unit
"H" , "L" Propagation
Delay Time
Data Setup Time
(IO68)ÆCP
IO
1
Data Hold Time
CPÆIO
(IO68)
1
t
PLH
t
PHL
f
CP
t
W(CP
t
SETUP
t
HOLD
t
(CP)
r
t
(CP)
f
MSM5298A¡ Semiconductor
(V
= 5V±10%, Ta = –20 to +85°C, C
DD
— — — 250 ns
— — — 1 MHzClock Frequency
)
—
—
—
125 — — nsClock Pulse Width
100 — — ns
100 — — ns
—
——50nsClock Pulse Rise/Fall Time
= 15pF)
L
CP
IO
IO
(IO68)
1
(IO1)
68
0.8V
DD
t
W(CP
t
SETUP
)
0.8V
DD
0.8V
0.2V
DD
DD
t
f(CP
0.2V
0.8V
0.2V
DD
DD
t t
)
DD
PLH PHL
t
HOLD
0.8V
0.2V
DD
DD
0.8V
0.2V
t
r(CP
)
DD
DD
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Page 6
MSM5298A¡ Semiconductor
FUNCTIONAL DESCRIPTION
Pin Functional Description
• IO1, IO68, SHL
IO1 and IO68 are 68-bit bidirectional shift register input/output pins. The shifting direction is selected by the SHL pin. Refer to the table below.
SHL
LO
Shifting
direction
1
Æ O
68
IO
68
1
Input/
output
Input
DescriptionIO1/IO
The scanning data from the LCD controller LSI is input into IO
synchronized with the clock pulse.*
1
1
Shift register contents output pin. The data which is
IO
68
Output
input into IO
is output from IO68 with 68 bit's
1
delay, synchronized with the clock pulse.
The scanning data from the LCD controller LSI is input into IO
synchronized with the clock pulse.*
68
1
HO
Æ O
68
IO
68
1
Input
Shift register contents output pin. The data which is
IO
1
Output
input into IO
is output from IO1 with 68 bit's delay,
68
synchronized with the clock pulse.
*1 The combination of the scanning data, IO1 or IO68, and the LCD driving output, O1 to O68,
is shown in the table below.
IO1, IO
68
"H" Select level (V
LCD driving output
, VEE)
1
"L" Non-select level (V
, V5)
2
• CP
Clock pulse input pin for 68-bit bidirectional shift register. The data is shifted to 68-bit bidirectional shift register at the falling edge of the clock pulse.
• DF
Alternate signal input pin for LCD driving.
• VDD, V
SS
Supply voltage pins. VDD should be 4.5 to 5.5V. VSS is a ground pin. (VSS = 0V).
• DISP OFF
Control input pin for display data output level (O1 to O68). V1 level is output from O1 to O pin during "L" level input. Refer to Truth Table.
68
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Page 7
MSM5298A¡ Semiconductor
• V1, V2, V5, V
EE
Bias supply voltage pins to drive the LCD. The V1 pin can be separated from the VDD pin.
• O1 - O
68
Display data output pins which correspond to each bit of the 68-bit bidirectional shift register. One of the four levels, V1, V2, V5 and VEE, is selected based on the combination of the latched data level and DF signal. (Refer to Truth Table.) Connect these outputs to the common side of the LCD panel.
Truth Table
DF Shift register data DISP OFF Driver output level (O1 to O68)
LL H V
LH H V
HL H V
HH H V
XX L V
2
EE
5
1
1
X : Don't care
NOTES ON USE (when turning the power ON or OFF)
The LCD drivers of this IC require a high voltage. For this reason, if a high voltage is applied to the LCD drivers with the logic power supply floating, excess current flows. This may damage the IC. Be sure to follow the sequence below when turning the power ON or OFF. Power ON : Logic circuits ON Æ LCD drivers ON, or both ON at a time Power OFF : LCD drivers OFF Æ logic circuits OFF, or both OFF at a time
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Page 8
PACKAGE DIMENSIONS
QFP80-P-1420-0.80-K
Mirror finish
MSM5298A¡ Semiconductor
(Unit : mm)
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more
1.27 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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Page 9
QFP80-P-1420-0.80-BK
Mirror finish
MSM5298A¡ Semiconductor
(Unit : mm)
Package material Lead frame material Pin treatment Solder plate thickness
Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more
1.27 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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