Datasheet MSM51V18165B-50TS-K, MSM51V18165BSL-70JS, MSM51V18165BSL-70TS-K, MSM51V18165BSL-60JS, MSM51V18165B-70TS-K Datasheet (OKI)

409

¡ Semiconductor MSM51V18165B/BSL

DESCRIPTION

The MSM51V18165B/BSL is a 1,048,576-word ¥ 16-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM51V18165B/BSL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ double-layer metal CMOS process. The MSM51V18165B/BSL is available in a 42-pin plastic SOJ or 50/44-pin plastic TSOP. The MSM51V18165BSL (the self-refresh version) is specially designed for lower-power applications.

FEATURES

• 1,048,576-word ¥ 16-bit configuration

• Single 3.3 V power supply, ±0.3 V tolerance

• Input : LVTTL compatible, low input capacitance

• Output : LVTTL compatible, 3-state

• Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (SL version)

• Fast page mode with EDO, read modify write capability

• CAS before RAS refresh, hidden refresh, RAS-only refresh capability

• CAS before RAS self-refresh capability (SL version)

• Package options: 42-pin 400 mil plastic SOJ (SOJ42-P-400-1.27)

(Product : MSM51V18165B/BSL-xxJS)

50/44-pin 400 mil plastic TSOP

(TSOPII50/44-P-400-0.80-K) (Product : MSM51V18165B/BSL-xxTS-K)

xx indicates speed rank.

PRODUCT FAMILY

¡ Semiconductor

MSM51V18165B/BSL

1,048,576-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO

MSM51V18165B/BSL-70

70 ns

124 ns

84 ns

504 mW

684 mW

Family

Access Time (Max.)

Cycle Time

(Min.)

Standby (Max.)

Power Dissipation

MSM51V18165B/BSL-50

t

RAC

50 ns

35 ns

t

AA

25 ns

20 ns

t

CAC

13 ns

20 ns

t

OEA

13 ns

MSM51V18165B/BSL-60

60 ns

104 ns 576 mW

30 ns 15 ns 15 ns

Operating (Max.)

1.8 mW/

0.72 mW (SL version)

E2G0087-17-41

410

MSM51V18165B/BSL ¡ Semiconductor

PIN CONFIGURATION (TOP VIEW)

A9

A8

A7

A6

A5

A4

NC

A0

A1

A2

A3

1

2

3

4

5

6

7

8

9

10

11

12

13

21 22

30

31

32

33

34

35

36

37

38

39

40

41

42V

CC

DQ1

DQ2

DQ3

DQ4

V

CC

DQ5

DQ6

DQ7

DQ8

NC

WE

V

CC

V

SS

UCAS

LCAS

NC

DQ9

DQ10

DQ11

DQ12

V

SS

DQ13

DQ14

DQ15

DQ16

V

SS

14 29RAS OE

15 28NC A9

16 27NC A8

17 26A0 A7

18 25A1 A6

19 24A2 A5

20 23A3 A4

1

2

3

4

5

6

7

8

9

10

11

25 26

40

41

42

43

44

45

46

47

48

49

50V

CC

DQ1

DQ2

DQ3

DQ4

V

CC

DQ5

DQ6

DQ7

DQ8

NC

V

CC

V

SS

NC

DQ9

DQ10

DQ11

DQ12

V

SS

DQ13

DQ14

DQ15

DQ16

V

SS

15 36NC NC 16 35NC LCAS 17 34WE UCAS 18 33RAS OE

19 32

20 31

21 30

22 29

23 28

24 27

42-Pin Plastic SOJ

50/44-Pin Plastic TSOP

(K Type)

Note : The same power supply voltage must be provided to every VCC pin, and the same GND

voltage level must be provided to every VSS pin.

Pin Name

A0 - A9 Address Input

RAS Row Address Strobe

LCAS Lower Byte Column Address Strobe

DQ1 - DQ16 Data Input/Data Output

OE Output Enable

WE Write Enable

V

CC

Power Supply (3.3 V)

V

SS

Ground (0 V)

UCAS Upper Byte Column Address Strobe

NC No Connection

Function

411

¡ Semiconductor MSM51V18165B/BSL

BLOCK DIAGRAM

Timing

Generator

Refresh

Control Clock

Column

Address

Buffers

Internal Address Counter

Row

Address

Buffers

Row Decoders

Word

Drivers

Memory

Cells

Sense Amplifiers

Column Decoders

I/O

Controller

I/O

Controller

I/O

Selector

Input

Buffers

Output

Buffers

Output

Buffers

Input

Buffers

On Chip

V

BB

Generator

V

CC

DQ1 - DQ8

DQ9 - DQ16

UCAS

WE

A0

-

A9

10

16

8

16

88

8

10

OE

RAS

LCAS

V

SS

10

FUNCTION TABLE

Function Mode

RAS

H

L

Input Pin

LCAS

*

H

L

UCAS

H

WE

H

L

OE

L

H

L

H

L

H

L

H

L

*

H

Lower Byte Read

Upper Byte Read

Word Read

Refresh

Standby

Lower Byte Write

DQ Pin

DQ1 - DQ8

High-Z

D

OUT

D

IN

DQ9 - DQ16

High-Z

D

OUT

Don't Care

High-Z

D

OUT

D

OUT

Don't Care

D

IN

Upper Byte Write

LLLL H

D

IN

D

IN

Word Write

HLLL H

High-Z High-Z

—

H

*: "H" or "L"

412

MSM51V18165B/BSL ¡ Semiconductor

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Recommended Operating Conditions

Capacitance

*: Ta = 25°C

Voltage on Any Pin Relative to V

SS

Short Circuit Output Current

Power Dissipation

Operating Temperature

Storage Temperature

V

T

Symbol

I

OS

P

D

*

T

opr

T

stg

–0.5 to 4.6

50

1

0 to 70

–55 to 150

Rating

mA

W

°C

Parameter

V

Unit

Power Supply Voltage

Input High Voltage

Input Low Voltage

V

CC

Symbol

V

SS

V

IH

V

IL

3.3

0

—

Typ.Parameter

3.0

0

2.0

–0.3

Min.

3.6

0

V

CC

+ 0.3

0.8

Max.

(Ta = 0°C to 70°C)

V

Unit

V

Input Capacitance (A0 - A9)

Input Capacitance

Output Capacitance (DQ1 - DQ16)

C

IN1

Symbol

C

IN2

C

I/O

5

7

Max.

pF

Unit

pF

Parameter

(V

CC

= 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz)

—

Typ.

(RAS, LCAS, UCAS, WE, OE)

413

¡ Semiconductor MSM51V18165B/BSL

DC Characteristics

Parameter

Symbol

Condition

MSM51V18165

B/BSL-50

MSM51V18165

B/BSL-60

MSM51V18165

B/BSL-70

(VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C)

IOH = –2.0 mAOutput High Voltage

IOL = 2.0 mAOutput Low Voltage

0 V £ VI £ VCC + 0.3 V;

All other pins notInput Leakage Current

under test = 0 V

DQ disable

Output Leakage Current

0 V £ VO £ V

CC

RAS, CAS cycling,

Average Power

t

RC

= Min.

Supply Current

(Operating)

RAS, CAS = V

IH

Power Supply

RAS, CAS

Current (Standby)

RAS cycling,Average Power CAS = V

IH

,Supply Current

tRC = Min.(RAS-only Refresh) RAS = V

IH

,

Power Supply

CAS = V

IL

,

Current (Standby)

DQ = enable

Average Power

CAS before RAS

Supply Current (CAS before RAS Refresh)

Average Power

RAS £ 0.2 V,Supply Current CAS £ 0.2 V(CAS before RAS

V

OH

V

OL

I

LI

I

LO

I

CC1

I

CC2

I

CC3

I

CC5

I

CC6

I

CCS

≥ VCC –0.2 V

Min. Max. Min. Max. Min. Max.

Unit Note

RAS cycling,

2.4

0

–10

—

V

CC

0.4

10

190

2

0.5

190

300

5

2.4

0

–10

—

V

CC

0.4

10

160

2

0.5

160

300

5

2.4

0

–10

—

V

CC

0.4

10

140

2

0.5

140

300

5

— 200 — 200 — 200

V

mA

1, 2

1, 5

1

mA 1, 5

tRC = 125 ms,Average Power CAS before RAS,Supply Current

t

RAS

£ 1 ms(Battery Backup)

I

CC10

— 300 — 300 — 300 mA

1, 4,

RAS = VIL,Average Power CAS cycling,Supply Current

t

HPC

= Min.(Fast Page Mode)

I

CC7

— 190 — 160 — 140 mA 1, 3

5

Self-Refresh)

Notes : 1. ICC Max. is specified as ICC for output open condition.

2. The address can be changed once or less while RAS = VIL.

3. The address can be changed once or less while CAS = VIH.

4. VCC – 0.2 V £ VIH £ VCC + 0.3 V, –0.3 V £ VIL £ 0.2 V.

5. SL version.

414

MSM51V18165B/BSL ¡ Semiconductor

AC Characteristics (1/2)

Parameter

MSM51V18165

B/BSL-60

MSM51V18165

B/BSL-70

MSM51V18165

B/BSL-50

(VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3

Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write

Cycle Time Access Time from RAS Access Time from CAS

Access Time from Column Address Access Time from CAS Precharge

CAS to Data Output Buffer Turn-off Delay Time

Transition Time

RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode with EDO) RAS Hold Time

CAS Pulse Width CAS Hold Time

RAS to CAS Delay Time RAS to Column Address Delay Time

CAS to RAS Precharge Time

Row Address Set-up Time

Row Address Hold Time

Column Address Set-up Time

Column Address Hold Time

Column Address to RAS Lead Time

Access Time from OE

OE to Data Output Buffer Turn-off Delay Time

Refresh Period

RAS Hold Time referenced to OE

Unit

Min. Max. Min. Max.

RAS Hold Time from CAS Precharge

Symbol

t

RC

t

RWC

t

HPC

t

HPRWC

t

RAC

t

CAC

t

AA

t

CPA

t

CEZ

t

T

t

RP

t

RAS

t

RASP

t

RSH

t

CAS

t

CSH

t

RCD

t

RAD

t

CRP

t

ASR

t

RAH

t

ASC

t

CAH

t

RAL

t

OEA

t

OEZ

t

REF

t

ROH

t

RHCP

Note

Min. Max.

Output Low Impedance Time from CAS t

CLZ

CAS Precharge Time (Fast Page Mode with EDO)

t

CP

4, 5, 6

4, 5

4, 6

4, 13

7, 8

15

5 6

13

12

4

7

4

3

16

ns ns ns

ns

ns ns

ns

ns ns

ns

ns ns

ns

ms

ns

84

110

20

58

—

— —

0

1

30

50

7

35

11

9

5

0

7

0

7

25

—

0

—

7

30

— — —

—

50

13

25 30

—

13

50

—

10,000

100,000

—

10,000

—

37 25

—

— —

13

16

—

124 160

30

78

—

— —

0

1

50

70

13

10

13

45

14 12

5

0

10

0

13 35

—

0

—

13

40

— — —

—

70

20

35 40

—

20

50

—

10,000

100,000

—

10,000

—

50 35

—

— —

20

16

—

104 135

25

68

—

— —

0

1

40

60

10

40

14 12

5

0

10

0

10 30

—

0

—

10

35

— — —

—

60

15

30 35

—

15

50

—

10,000

100,000

—

10,000

—

45 30

—

— —

15

16

—

Refresh Period (SL version)

t

REF

ms— 128 — 128— 128

Data Output Hold After CAS Low

WE to Data Output Buffer Turn-off Delay Time

RAS to Data Output Buffer Turn-off Delay Time

t

DOH

t

WEZ

t

REZ

7, 8

7

ns

5— 5—5—

OE Hold Time from CAS (DQ Disable) t

CHO

ns5— 5—5—

0

13

0

20

0

15

13

415

¡ Semiconductor MSM51V18165B/BSL

AC Characteristics (2/2)

MSM51V18165

B/BSL-60

MSM51V18165

B/BSL-70

MSM51V18165

B/BSL-50

Write Command Pulse Width

Write Command to CAS Lead Time

Write Command to RAS Lead Time

Data-in Set-up Time

CAS to WE Delay Time

RAS to WE Delay Time

Column Address to WE Delay Time

RAS to CAS Hold Time (CAS before RAS)

CAS Active Delay Time from RAS Precharge

Data-in Hold Time

Write Command Hold Time

OE Command Hold Time

OE to Data-in Delay Time

(VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3

Write Command Set-up Time

t

WP

t

CWL

t

RWL

t

DS

t

CWD

t

RWD

t

AWD

t

CHR

t

RPC

t

DH

t

WCH

t

OEH

t

OED

t

WCS

Min. Max.

Parameter

Symbol

Unit Note

Min. Max. Min. Max.

RAS to CAS Set-up Time (CAS before RAS)t

CSR

CAS Precharge WE Delay Time t

CPWD

14

11, 12

10

12 13

12

11, 12

12

10, 12

10

0

34

79

49

5

10

5

10

15

0

54

—

— —

—

ns

ns ns

ns

7

0

30

67

42

5

10

5

7

13

0

47

—

— —

—

10

13

0

44

94

59

5

10

5

13

20

0

64

—

— —

—

RAS Pulse Width

t

RASS

16100 — ms100 — 100 —

(CAS before RAS Self-Refresh) RAS Precharge Time

t

RPS

16110 — ns90 — 130 —

(CAS before RAS Self-Refresh) CAS Hold Time

t

CHS

16–50 — ns–50 — –50 —

(CAS before RAS Self-Refresh)

Read Command Set-up Time

Read Command Hold Time Read Command Hold Time referenced to RAS

t

RCS

t

RCH

t

RRH

12

9, 12

9

ns

0

—

0

—

0

—

WE Pulse Width (DQ Disable) t

WPE

10 — ns7 — 10 —

OE Command Hold Time

t

OCH

10 — ns7 — 10 —

OE Precharge Time

t

OEP

10 — ns7 — 10 —

416

MSM51V18165B/BSL ¡ Semiconductor

Notes: 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight

initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.

2. The AC characteristics assume tT = 2 ns.

3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL.

4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100 pF.

The output timing reference levels are VOH = 2.0 V and VOL = 0.8 V.

5. Operation within the t

RCD

(Max.) limit ensures that t

RAC

(Max.) can be met.

t

RCD

(Max.) is specified as a reference point only. If t

RCD

is greater than the specified

t

RCD

(Max.) limit, then the access time is controlled by t

CAC

.

6. Operation within the t

RAD

(Max.) limit ensures that t

RAC

(Max.) can be met.

t

RAD

(Max.) is specified as a reference point only. If t

RAD

is greater than the specified

t

RAD

(Max.) limit, then the access time is controlled by tAA.

7. t

CEZ

(Max.), t

REZ

(Max.), t

WEZ

(Max.) and t

OEZ

(Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels.

8. t

CEZ

and t

REZ

must be satisfied for open circuit condition.

9. t

RCH

or t

RRH

must be satisfied for a read cycle.

10. t

WCS

, t

CWD

, t

RWD

, t

AWD

and t

CPWD

are not restrictive operating parameters. They are

included in the data sheet as electrical characteristics only. If t

WCS

≥ t

WCS

(Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If t

CWD

≥ t

CWD

(Min.) , t

RWD

≥ t

RWD

(Min.),

t

AWD

≥ t

AWD

(Min.) and t

CPWD

≥ t

CPWD

(Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate.

11. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle.

12. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier.

13. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later.

14. t

CWL

should be satisfied by both UCAS and LCAS.

15. tCP is determined by the time both UCAS and LCAS are high.

16. Only SL version.

See ADDENDUM Q for AC Timing Waveforms

Datasheet MSM51V18165B-50TS-K, MSM51V18165BSL-70JS, MSM51V18165BSL-70TS-K, MSM51V18165BSL-60JS, MSM51V18165B-70TS-K Datasheet (OKI)

Specifications and Main Features

Frequently Asked Questions

User Manual