Datasheet MSM518222-40JS, MSM518222-25ZS, MSM518222-30GS-K, MSM518222-30JS, MSM518222-30ZS Datasheet (OKI)
...Page 1
E2L0033-17-Y1
¡ Semiconductor MSM518222
¡ Semiconductor
This version: Jan. 1998
Previous version: Dec. 1996
MSM518222
262,214-Word ¥ 8-Bit Field Memory
DESCRIPTION
The OKI MSM518222 is a high performance 2-Mbit, 256K ¥ 8-bit, Field Memory. It is designed for
high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies
and Multi-media systems. The 2-Mbit capacity fits one field of a conventional NTSC TV screen. Two
cascaded MSM518222s make one frame of the screen: two or more MSM518222s can be cascaded
directly without any delay devices between them. (Cascading provides larger storage depth or a
longer delay).
Each of the 8-bit planes has separate serial write and read ports. These employ independent control
clocks to support asynchronous read and write operations. Different clock rates are also supported,
which allow alternate data rates between write and read data streams.
The MSM518222 provides high speed FIFO, First-In First-Out, operation without external refreshing:
it refreshes its DRAM storage cells automatically, so that it appears fully static to the users.
Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial
access operation, so that serial read and/or write control clock can be halted high or low for any
duration as long as the power is on. Internal conflicts of memory access and refreshing operations
are prevented by special arbitration logic.
The MSM518222's function is simple and similar to a digital delay device whose delay-bit-length is
easily set by reset timing. The delay length, and the number of read delay clocks between write and
read, is determined by externally controlled write and read reset timings.
Additional SRAM serial registers, or line buffers for the initial access of 256 ¥ 8-bit enable high speed
first-bit-access with no clock delay just after the write or read reset timings.
The MSM518222 is similar in operation and functionality to OKI 1-Mbit Field Memory MSM514221B,
with the addition of cascade capability. (As for MSM514221B operation compatible 2-Mbit Field
Memory, OKI has the MSM518221 which is a sister device of MSM518222).
Additionally, the MSM518222 has a write mask function or input enable function (IE), and read-data
skipping function or output enable function (OE). The differences between write enable (WE) and
input enable (IE), and between read enable (RE) and output enable (OE) are that WE and RE can stop
serial write/read address increments, but IE and OE cannot stop the increment, when write/read
clocking is continuously applied to MSM518222. The input enable (IE) function allows the user to
write into selected locations of the memory only, leaving the rest of the memory contents unchanged.
This facilitates data processing to display a "picture in picture" on a TV screen.
1/16
Page 2
¡ Semiconductor MSM518222
FEATURES
• Single power supply : 5 V ±10%
• 512 Rows ¥ 512 Columns ¥ 8 bits
• Fast FIFO (First-In First-Out) operation
• High speed asynchronous serial access
Read/write cycle time 25 ns/30 ns/40 ns
Access time 25 ns/25 ns/30 ns
• Direct cascading capability
• Write mask function (Input enable control)
• Data skipping function (Output enable control)
• Self refresh (No refresh control is required)
• Package options :
28-pin 400 mil plastic ZIP (ZIP28-P-400-1.27) (Product : MSM518222-xxZS)
28-pin 400 mil plastic SOJ (SOJ28-P-400-1.27) (Product : MSM518222-xxJS)
28-pin 430 mil plastic SOP (SOP28-P-430-1.27-K) (Product : MSM518222-xxGS-K)
xx indicates speed rank.
PRODUCT FAMILY
Family Access Time (Max.) Cycle Time (Min.) Package
MSM518222-25ZS 25 ns25 ns
MSM518222-30ZS 30 ns25 ns 400 mil 28-pin ZIP
MSM518222-40ZS 40 ns30 ns
MSM518222-25JS
MSM518222-30JS 30 ns25 ns 400 mil 28-pin SOJ
MSM518222-40JS 40 ns30 ns
MSM518222-30GS-K 30 ns25 ns
MSM518222-40GS-K 40 ns30 ns
25 ns25 ns
430 mil 28-pin SOP
2/16
Page 3
¡ Semiconductor MSM518222
PIN CONFIGURATION (TOP VIEW)
WE
D
IN
DIN2
V
DIN5
D
IN
SWCK
NC
OE
D
OUT
D
OUT
D
OUT
D
OUT
RSTR
1
3
0
5
7
CC
9
7
11
13
15
17
19
6
21
4
23
3
25
1
27
10
12
14
16
18
20
22
24
26
28
2
4
6
8
IE
1
D
IN
DIN3
4
D
IN
6
D
IN
RSTW
NC
RE
D
OUT
D
OUT
V
SS
D
OUT
D
OUT
SRCK
DIN4
1
D
5
2
IN
6
D
3
IN
D
7
4
IN
RSTW
5
623
SWCK
722
NC
RE
821
OE
9
D
10
7
OUT
11
D
6
OUT
7
5
12
5
D
OUT
13
D
4
OUT
14 15
V
SS
28
27
26
25
24
20
19
18
17
16
V
CC
DIN3
2
D
IN
D
1
IN
0
D
IN
IE
WE
NC
SRCK
RSTR
D
OUT
D
OUT
D
OUT
D
OUT
1
4
D
IN
5
D
2
IN
3
D
6
IN
7
4
D
IN
RSTW
5
SWCK
6
NC
RE
8
OE
9
D
10
7
OUT
0
1
2
3
11
D
6
OUT
12
D
5
OUT
13
4
D
OUT
V
14 15
SS
28
27
26
25
24
23
227
21
20
19
18
17
16
V
CC
DIN3
D
IN
D
IN
D
IN
IE
WE
NC
SRCK
RSTR
D
OUT
D
OUT
D
OUT
D
OUT
2
0
28-Pin Plastic SOJ
28-Pin Plastic SOP
2
1
0
0
1
2
3
28-Pin Plastic ZIP
Pin Name Function
SWCK
SRCK
RSTW
RSTR
D
IN
D
OUT
WE
RE
IE
OE
0 - 7
V
CC
V
SS
0 - 7
Serial Write Clock
Serial Read Clock
Write Enable
Read Enable
Input Enable
Output Enable
Write Reset Clock
Read Reset Clock
Data Input
Data Output
Power Supply (5 V)
Ground (0 V)
NC No Connection
3/16
Page 4
D
(¥ 8)
OUT
OE
RE
RSTR SRCK
BLOCK DIAGRAM
¡ Semiconductor MSM518222
Data-out
Buffer (¥ 8)
71 Word
Sub-Register (¥ 8)
71 Word
Sub-Register (¥ 8)
Data-in
Buffer (¥ 8)
Serial
Read
Controller
512 Word Serial Read Register (¥ 8)
Read Line Buffer
Low-Half (¥ 8)
Read Line Buffer
High-Half (¥ 8)
256 (¥ 8)
256K (¥ 8)
Memory
Array
256 (¥ 8)
Write Line Buffer
Low-Half (¥ 8)
Write Line Buffer
High-Half (¥ 8)
512 Word Serial Write Register (¥ 8)
Serial
Write
Controller
256 (¥ 8)
256 (¥ 8)
X
Decoder
Read/Write
and Refresh
Controller
Clock
Oscillator
V
Generator
BB
4/16
D
(¥ 8)
IN
IE WE RSTW SWCK
Page 5
¡ Semiconductor MSM518222
OPERATION
Write Operation
The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is
accomplished by cycling SWCK, and holding WE high after the write address pointer reset operation
or RSTW.
Each write operation, which begins after RSTW, must contain at least 80 active write cycles, i.e.
SWCK cycles while WE is high. To transfer the last data to the DRAM array, which at that time
is stored in the serial data registers attached to the DRAM array, an RSTW operation is required
after the last SWCK cycle.
Note that every write timing of MSM518222 is delayed by one clock compared with read timings for
easy cascading without any interface delay devices.
Write Reset : RSTW
The first positive transition of SWCK after RSTW becomes high resets the write address counters to
zero. RSTW setup and hold times are referenced to the rising edge of SWCK. Because the write reset
function is solely controlled by the SWCK rising edge after the high level of RSTW, the states of WE
and IE are ignored in the write reset cycle.
Before RSTW may be brought high again for a further reset operation, it must be low for at least two
SWCK cycles.
Data Inputs : DIN0 - 7
Write Clock : SWCK
The SWCK latches the input data on chip when WE is high, and also increments the internal write
address pointer. Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK.
Write Enable : WE
WE is used for data write enable/disable control. WE high level enables the input, and WE low level
disables the input and holds the internal write address pointer. There are no WE disable time (low)
and WE enable time (high) restrictions, because the MSM518222 is in fully static operation as long
as the power is on. Note that WE setup and hold times are referenced to the rising edge of SWCK.
Input Enable : IE
IE is used to enable/disable writing into memory. IE high level enables writing. The internal write
address pointer is always incremented by cycling SWCK regardless of the IE level. Note that IE setup
and hold times are referenced to the rising edge of SWCK.
5/16
Page 6
¡ Semiconductor MSM518222
Read Operation
The read operation is controlled by three clocks, SRCK, RSTR, and RE. Read operation is
accomplished by cycling SRCK, and holding RE high after the read address pointer reset operation
or RSTR.
Each read operation, which begins after RSTR, must contain at least 80 active read cycles, i.e.
SRCK cycles while RE is high.
Read Reset : RSTR
The first positive transition of SRCK after RSTR becomes high resets the read address counters to
zero. RSTR setup and hold times are referenced to the rising edge of SRCK. Because the read reset
function is solely controlled by the SRCK rising edge after the high level of RSTR, the states of RE and
OE are ignored in the read reset cycle.
Before RSTR may be brought high again for a further reset operation, it must be low for at least *two
SRCK cycles.
Data Out : D
OUT
0 - 7
Read Clock : SRCK
Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high
during a read operation. The SRCK input increments the internal read address pointer when RE is
high.
The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data
out is the same polarity as data in. The output becomes valid after the access time interval tAC that
begins with the rising edge of SRCK. *There are no output valid time restrictions on MSM518222.
Read Enable : RE
The function of RE is to gate the SRCK clock for incrementing the read pointer. When RE is high
before the rising edge of SRCK, the read pointer is incremented. When RE is low, the read pointer
is not incremented. RE setup times (t
RENS
and t
) and RE hold times (t
RDSS
RENH
and t
RDSH
) are
referenced to the rising edge of the SRCK clock.
Output Enable : OE
OE is used to enable/disable the outputs. OE high level enables the outputs. The internal read
address pointer is always incremented by cycling SRCK regardless of the OE level. Note that OE
setup and hold times are referenced to the rising edge of SRCK.
6/16
Page 7
¡ Semiconductor MSM518222
Power-up and Initialization
On power-up, the device is designed to begin proper operation after at least 100 ms after VCC has
stabilized to a value within the range of recommended operating conditions. After this 100 ms
stabilization interval, the following initialization sequence must be performed.
Because the read and write address counters are not valid after power-up, a minimum of 80 dummy
write operations (SWCK cycles) and read operations (SRCK cycles) must be performed, followed by
an RSTW operation and an RSTR operation, to properly initialize the write and the read address
pointer. Dummy write cycles/RSTW and dummy read cycles/RSTR may occur simultaneously.
If these dummy read and write operations start while VCC and/or the substrate voltage has not
stabilized, it is necessary to perform an RSTR operation plus a minimum of 80 SRCK cycles plus
another RSTR operation, and an RSTW operation plus a minimum of 80 SRCK cycles plus another
RSTW operation to properly initialize read and write address pointers.
Old/New Data Access
There must be a minimum delay of 600 SWCK cycles between writing into memory and reading out
from memory. If reading from the first field starts with an RSTR operation, before the start of writing
the second field (before the next RSTW operation), then the data just written will be read out.
The start of reading out the first field of data may be delayed past the beginning of writing in the
second field of data for as many as 70 SWCK cycles. If the RSTR operation for the first field read-out
occurs less than 70 SWCK cycles after the RSTW operation for the second field write-in, then the
internal buffering of the device assures that the first field will still be read out. The first field of data
that is read out while the second field of data is written is called "old data".
In order to read out"new data", i.e., the second field written in, the delay between an RSTW operation
and an RSTR operation must be at least 600 SRCK cycles. If the delay between RSTW and RSTR
operations is more than 71 but less than 600 cycles, then the data read out will be undetermined. It
may be "old data" or "new" data, or a combination of old and new data. Such a timing should be
avoided.
Cascade Operation
The MSM518222 is designed to allow easy cascading of multiple memory devices. This provides
higher storage depth, or a longer delay than can be achieved with only one memory device.
7/16
Page 8
¡ Semiconductor MSM518222
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Symbol Condition Rating
Input Output Voltage
Output Current
Power Dissipation
Operating Temperature
Storage Temperature
V
T
I
OS
P
D
T
opr
T
stg
at Ta = 25°C, V
Ta = 25°C
Ta = 25°C
—
—
SS
Recommended Operating Conditions
Parameter Symbol Min. UnitTyp. Max.
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
V
CC
V
SS
V
IH
V
IL
4.5
0
2.4
–1.0
5.0
V
0
CC
0
DC Characteristics
Parameter Symbol Condition Min.
Input Leakage Current
Output Leakage Current
Output "H" Level Voltage
Output "L" Level Voltage
Operating Current
Standby Current
I
0 < VI < V
LI
I
LO
V
OH
V
OL
I
1
Minimum Cycle Time, Output Open
CC
I
CC2
+ 1, Other Pins Tested at V = 0 V
CC
0 < VO < V
I
= –1 mA
OH
I
OL
Input Pin = V
= 2 mA
CC
-25
-30
-40
/ V
IH
IL
–1.0 to 7.0
0 to 70
–55 to 150
–10
–10
2.4
—
—
—
—
—
50
1
5.5
0
VCC + 1
0.8
Max. Unit
10
10
—
0.4
60
50
40
5
Unit
V
mA
W
°C
°C
V
V
V
V
mA
mA
V
V
mA
mA
Capacitance
Input Capacitance (D
Output Capacitance (D
Parameter Unit
, SWCK, SRCK, RSTW, RSTR, WE, RE, IE, OE)
IN
)
OUT
(Ta = 25°C, f = 1 MHz)
Symbol Max.
C
I
C
O
7
7
pF
pF
8/16
Page 9
¡ Semiconductor MSM518222
AC Characteristics
t
AC
DS
DH
SRC
t
T
MSM518222-25
—
6
6
9
9
5
6
0
5
0
5
0
5
0
5—
5
5—
5
5
0
10
9
9
0
5
0
5
0
5
0
5
5
5
5
5
0
10RSTR Hold Time 10 10 ns—
25SWCK Cycle Time 30 40 ns—
25SRCK Cycle Time 30 40 ns—
3
Parameter
Symbol Unit
Access Time from SRCK
D
Hold Time from SRCK
OUT
Enable Time from SRCK
D
OUT
SWCK "H" Pulse Width
SWCK "L" Pulse Width
Input Data Setup Time
Input Data Hold Time
WE Enable Setup Time
WE Enable Hold Time
WE Disable Setup Time
WE Disable Hold Time
IE Enable Setup Time
IE Enable Hold Time
IE Disable Setup Time
IE Disable Hold Time
WE "H" Pulse Width
WE "L" Pulse Width
IE "H" Pulse Width
IE "L" Pulse Width
RSTW Setup Time
RSTW Hold Time
SRCK "H" Pulse Width
SRCK "L" Pulse Width
RE Enable Setup Time
RE Enable Hold Time
RE Disable Setup Time
RE Disable Hold Time
OE Enable Setup Time
OE Enable Hold Time
OE Disable Setup Time
OE Disable Hold Time
RE "H" Pulse Width
RE "L" Pulse Width
OE "H" Pulse Width
OE "L" Pulse Width
RSTR Setup Time
t
DDCK
t
DECK
t
WSWH
t
WSWL
t
t
t
WENS
t
WENH
t
WDSS
t
WDSH
t
IENS
t
IENH
t
IDSS
t
IDSH
t
WWEH
t
WWEL
t
WIEH
t
WIEL
t
RSTWS
t
RSTWH
t
WSRH
t
WSRL
t
RENS
t
RENH
t
RDSS
t
RDSH
t
OENS
t
OENH
t
ODSS
t
ODSH
t
WREH
t
WREL
t
WOEH
t
WOEL
t
RSTRS
t
RSTRH
t
SWC
t
Transition Time (Rise and Fall) 3 3 ns30
(VCC = 5 V ±10%, Ta = 0°C to 70°C)
MSM518222-30 MSM518222-40
Max.Min.
25
—
25
—
—
—
—
—
—
—
—
—
—
—
—
12
12
25
6
6
—
25
—
—
5
6
0
5
0
5
0
5
0
—
—
—
—
—
—
—
—
—
—
6
6
17
17
5
6
0
5
0
5
0
5
0
Max.Min.Max.Min.
30
—
25
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5—5—ns
—
10
—
10
—
ns
10 — 10 — ns
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
10
10
12
12
10
10
10
10
—
—
0
—
—
—
—
0
5
0
5
0
5
—
—
—
—
—
—
—
5
—
—
—
—
—
0
—
10
10
10
17
17
10
10
10
10
—
—
0
—
—
—
—
0
5
0
5
0
5
0
5
—
—
—
—
—
—
—
—
—
—
—
—
0
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns0
ns
ns
ns
ns
ns
ns
——
——
——
30 30
9/16
Page 10
¡ Semiconductor MSM518222
Notes: 1. Input signal reference levels for the parameter measurement are VIH = 3.0 V and V
= 0 V. The transition time tT is defined to be a transition time that signal transfers
between VIH = 3.0 V and VIL = 0 V.
2. AC measurements assume tT = 3 ns.
3. Read address must have more than a 600 address delay than write address in every
cycle when asynchronous read/write is performed.
4. Read must have more than a 600 address delay than write in order to read the data
written in a current series of write cycles which has been started at last write reset
cycle: this is called "new data read".
When read has less than a 70 address delay than write, the read data are the data
written in a previous series of write cycles which had been written before the last
write reset cycle: this is called "old data read".
5. When the read address delay is between more than 71 and less than 599, read data
will be undetermined. However, normal write is achieved in this address condition.
6. Outputs are measured with a load equivalent to 1 TTL load and 30 pF.
Output reference levels are VOH = 2.4 V and VOL = 0.8 V.
IL
10/16
Page 11
¡ Semiconductor MSM518222
TIMING WAVEFORM
Write Cycle Timing (Write Reset)
n cycle 0 cycle 1 cycle 2 cycle
V
SWCK
RSTW
D
IN
t
t
t
t
T
t
DS
RSTWS
t
DH
RSTWH
WSWH
t
SWC
t
WSWL
n-1 n 0 1 2
V
V
V
V
V
IH
IL
IH
IL
IH
IL
WE
IE
Write Cycle Timing (Write Enable)
n cycle Disable cycle Disable cycle n+1 cycle
SWCK
WE
D
t
WENH
t
WWEL
IN
n-1 n n+1
t
WDSH
t
WWEH
t
WDSS
t
WENS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
IE
RSTW
V
V
V
V
11/16
IH
IL
IH
IL
Page 12
¡ Semiconductor MSM518222
Write Cycle Timing (Input Enable)
n cycle
n+1 cycle n+2 cycle n+3 cycle
SWCK
t
IENH
IE
t
WIEL
D
IN
n-1 n n+3
WE
RSTW
Read Cycle Timing (Read Reset)
t
IDSH
t
WIEH
t
IDSS
t
IENS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
SRCK
RSTR
D
OUT
RE
OE
n cycle 0 cycle 1 cycle 2 cycle
t
t
t
t
T
RSTRS
t
AC
RSTRH
WSRH
t
DDCK
t
SRC
t
WSRL
n-1n012
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
12/16
Page 13
¡ Semiconductor MSM518222
Read Cycle Timing (Read Enable)
n cycle Disable cycle Disable cycle n+1 cycle
SRCK
V
V
IH
IL
t
RENH
t
RDSH
RE
t
t
WREL
D
OUT
n-1 n n+1
WREH
OE
RSTR
Read Cycle Timing (Output Enable)
n cycle n+1 cycle n+2 cycle n+3 cycle
SRCK
t
RDSS
t
RENS
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
OE
D
OUT
RE
RSTR
t
OENH
t
WOEN
t
ODSH
t
WOEH
n-1 n n+3Hi-Z
t
ODSS
t
OENS
t
DECK
V
V
V
V
V
V
V
V
13/16
IH
IL
OH
OL
IH
IL
IH
IL
Page 14
¡ Semiconductor MSM518222
PACKAGE DIMENSIONS
(Unit : mm)
ZIP28-P-400-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.85 TYP.
14/16
Page 15
¡ Semiconductor MSM518222
(Unit : mm)
SOJ28-P-400-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.30 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
15/16
Page 16
¡ Semiconductor MSM518222
(Unit : mm)
SOP28-P-430-1.27-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.75 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
16/16
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