Datasheet MSM514260E-60JS, MSM514260E-60TS-K, MSM514260E-70JS, MSM514260E-70TS-K Datasheet (OKI)

Semiconductor

This version:Aug.2000

MSM514260E

262,144-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE

DESCRIPTION

The MSM514260E is a 262,144-word × 16-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS technology.
The MSM514260E achieves high integration, high-speed operation, and low-power consumption because Oki
manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM514260E
is available in a 40-pin plastic SOJ, 44/40-pin plastic TSOP.

FEATURES

• 262,144-word × 16-bit configuration

• Single 5V power supply, ±10% tolerance

• Input : TTL compatible, low input capacitance

• Output : TTL compatible, 3-state

• Refresh : 512 cycles/8 ms

• Fast page mode, read modify write capability

• CAS before RAS refresh, hidden refresh, RAS-only refresh capability

• Package options:

40-pin 400mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM514260E-xxJS)
44/40-pin 400mil plastic TSOP (TSOPII44/40-P-400-0.80-K) (Product : MSM514260E-xxTS-K)

xx : indicates speed rank.

PRODUCT FAMILY

Family

MSM514260E

Access Time (Max.) Power Dissipation

t

RAC

60ns 30ns 15ns 15ns 110ns 633mW
70ns 35ns 20ns 20ns 130ns 578mW

t

AA

t

CAC

t

OEA

Cycle Time

(Min.)

Operating (Max.) Standby (Max.)

5.5mW

1/14

PIN CONFIGRATION (TOP VIEW)

40-Pin Plastic SOJ

(K Type)

WE

WE

MSM514260E

1

V

CC

2

DQ1

3

DQ2

4

DQ3

5

DQ4

6

V

CC

7

DQ5

8

DQ6

9

DQ7

10

DQ8

11

NC

12

NC

13
14

RAS

15

NC

16

A0

17

A1

18

A2

19

A3

20 21

V

CC

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

V

SS

DQ16
DQ15
DQ14
DQ13
V

SS

DQ12
DQ11
DQ10
DQ9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
V

SS

1

V

CC

2

DQ1

3

DQ2

4

DQ3

5

DQ4

6

V

CC

7

DQ5

8

DQ6

9

DQ7

10

DQ8

NC1413
NC

15
16

RAS

17

NC

18

A0

19

A1

20

A2

21

A3

22 23

V

CC

44/40-Pin Plastic TSOP

44
43
42
41
40
39
38
37
36
35

32
31
30

28
27
26
25
24

V

SS

DQ16
DQ15
DQ14
DQ13
V

SS

DQ12
DQ11
DQ10
DQ9

NC
LCAS
UCAS
OE29
A8
A7
A6
A5
A4
V

SS

Pin Name Function

A0 − A8

RAS

LCAS

UCAS

Lower Byte Column Address Strobe
Upper Byte Column Address Strobe

Address Input

Row Address Strobe

DQ1 - DQ16 Data Input/Data Output

OE

WE

V
V

CC

SS

Output Enable

Write Enable

Power Supply (5V)

Ground (0V)

NC No Connection

Note : The same power supply voltage must be provided to every VCC pin, and the same

GND voltage level must be provided to every VSS pin.

2/14

BLOCK DIAGRAM

A0 - A8

8888888168

16

999

9

Column

Internal

Counter

Row

Buffers

DQ1 - DQ8

DQ9 - DQ16

OEWERAS

LCAS

UCAS

VCCV

Timing

Generator

I/O

Controller

I/O

Controller

MSM514260E

Output
Buffers

Address

Buffers

Address

Address

SS

FUNCTION TABLE

Input Pin DQ Pin

RAS LCAS UCAS WE OE

Refresh

Control Clock

Row

Deco-

ders

On Chip

VBB Generator

Word

Drivers

Column Decoders

Sense Amplifiers

Memory

Cells

I/O

Selector

DQ1-DQ8 DQ9-DQ16

Input

Buffers

Input

Buffers

Output
Buffers

Function Mode

H * * * * High-Z High-Z Standby

L H H * * High-Z High-Z Refresh
L L H H L
L H L H L High-Z
L L L H L
L L H L H
L H L L H Don’t Care
L L L L H

D

D

OUT

OUT

D

D

IN

IN

High-Z Lower Byte Read

D
D

OUT
OUT

Upper Byte Read

Word Read

Don’t Care Lower Byte Write

D

IN

D

IN

Upper Byte Write

Word Write

L L L H H High-Z High-Z

* : “H” or “L”



3/14

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Parameter Symbol Rating Unit

MSM514260E

Voltage on Any Pin Relative to V
Voltage VCC supply Relative to V

SS

SS

VIN, V

Short Circuit Output Current
Power Dissipation
Operating Temperature
Storage Temperature

*: Ta = 25°C

Recommended Operating Conditions

Parameter Symbol Min. Typ. Max. Unit

V

Power Supply Voltage

Input High Voltage
Input Low Voltage

V

V
V

CC
SS

IH

IL

OUT

V

CC

I

OS

P

D*

T

opr

T

stg

−0.5 to VCC + 0.5

−0.5 to 7.0

50 mA

1 W

0 to 70 °C

−55 to 150

(Ta = 0°C to 70°C)

4.5 5.0 5.5 V
0 0 0 V

2.4

−0.5



*2



V

CC

*1

+ 0.5

0.8 V

V
V

°C

V

Notes: *1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with

respect to the point at which VCC is applied).

*2. The input voltage is VSS − 2.0V when the pulse width is less than 20ns (the pulse width respect to

the point at which VSS is applied).

Capacitance

(VCC = 5V ± 10%, Ta = 25°C, f=1MHz)

Parameter Symbol Typ. Max. Unit

Input Capacitance (A0 – A8)
Input Capacitance

(RAS, LCAS, UCAS, WE, OE)
Output Capacitance (DQ1 – DQ16)

C
C

C

IN1

IN2

I/O







5 pF

7 pF

7 pF

4/14

DC Characteristics

MSM514260E

(VCC = 5V ± 10%, Ta = 0°C to 70°C)

Parameter

Output High Voltage
Output Low Voltage

Input Leakage Current

Output Leakage Current

Average Power Supply Current
(Operating)

Power Supply Current
(Standby)

Average Power Supply Current
(RAS-only Refresh)

Symbol

V

OH

V

OL

I

LI

I

LO

I

CC1

I

CC2

I

CC3

Condition

IOH = −5.0mA
IOL = 4.2mA

0V ≤ VI ≤ 6.5V ;
All other pins not

under test = 0V
DQ disable

0V ≤ VO ≤ VCC

RAS, CAS cycling,
tRC = Min.

RAS, CAS = V

IH

RAS, CAS ≥
VCC – 0.2V

RAS cycling,
CAS = VIH,

tRC = Min.

MSM514260

E-60

Min.

Max

2.4 V

CC

MSM514260

E-70

Min.

2.4 V

Max

CC

0 0.4 0 0.4 V

−10

−10









10

10

115

2

1

115

−10

−10









10

10

105 mA 1,2

2

1

105 mA 1,2

Unit Note

V

µA

µA

mA 1

Power Supply Current
(Standby)

I

CC5

CAS = VIL,
DQ = enable

RAS = VIH,

Average Power Supply Current
(CAS before RAS Refresh)

I

CC6

RAS = cycling,
CAS before RAS

RAS = VIL,

Average Power Supply Current
(Fast Page Mode)

I

CC7

CAS cycling,
tPC = Min.

Notes: 1. ICC Max. is specified as ICC for output open condition.

2. The address can be changed once or less while RAS = VIL.

3. The address can be changed once or less while CAS = VIH.







5

115

115







5 mA 1

105 mA 1,2

105 mA 1,3

5/14

AC Characteristic (1/2)

MSM514260E

(VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3

Parameter Symbol

Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write Cycle Time
Access Time from RAS
Access Time from CAS
Access Time from Column Address
Access Time from CAS Precharge
Access Time from OE
Output Low Impedance Time from CAS

CAS to Data Output Buffer Turn-off Delay Time
OE to Data Output Buffer Turn-off Delay Time

Transition Time
Refresh Period

RAS Precharge Time
RAS Pulse Width
RAS Pulse Width (Fast Page Mode)
RAS Hold Time
RAS Hold Time referenced to OE
CAS Precharge Time (Fast Page Mode)
CAS Pulse Width
CAS Hold Time
CAS to RAS Precharge Time
RAS Hold Time from CAS Precharge
RAS to CAS Delay Time
RAS to Column Address Delay Time

Row Address Set-up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time

t

RC

t

RWC

t

PC

t

PRWC

t

RAC

t

CAC

t

AA

t

CPA

t

OEA

t

CLZ

t

OFF

t

OEZ

t

T

t

REF

t

RP

t

RAS

t

RASP

t

RSH

t

ROH

t

CP

t

CAS

t

CSH

t

CRP

t

RHCP

t

RCD

t

RAD

t

ASR

t

RAH

t

ASC

t

CAH

MSM514260

E-60

MSM514260

E-70

Unit Note

Min. Max. Min. Max.

110
155

40
85







0






60
15
30
35
15



130
185

45

100







0






ns
ns
ns

ns
70 ns 4,5,6
20 ns 4,5
35 ns 4,6
40 ns 4,12
20 ns 4



ns 4

0 15 0 15 ns 7
0 15 0 15 ns 7
3 50 3 50 ns 3



40



8



50

8 ms



ns

60 10,000 70 10,000 ns
60 100,000 70 100,000 ns
15
15
10





20
20
10





ns

ns

ns 14

15 10,000 20 10,000 ns
60

5

35





70

5

40





ns

ns 12

ns 12

20 45 20 50 ns 5
15 30 15 35 ns 6

0

10

0

10






0

10

0

15






ns

ns

ns 11

ns 11

6/14

AC Characteristic (2/2)

MSM514260E

(VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3

Parameter

Column Address to RAS Lead Time
Read Command Set-up Time
Read Command Hold Time

Read Command Hold Time referenced to RAS
Write Command Set-up Time
Write Command Hold Time
Write Command Pulse Width

OE Command Hold Time
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Set-up Time
Data-in Hold Time

OE to Data-in Delay Time
CAS to WE Delay Time
Column Address to WE Delay Time
RAS to WE Delay Time
CAS Precharge WE Delay Time
CAS Active Delay Time from RAS Precharge
RAS to CAS Set-up Time (CAS before RAS)
RAS to CAS Hold Time (CAS before RAS)

Symbol

t

RAL

t

RCS

t

RCH

t

RRH

t

WCS

t

WCH

t

WP

t

OEH

t

RWL

t

CWL

t

DS

t

DH

t

OED

t

CWD

t

AWD

t

RWD

t

CPWD

t

RPC

t

CSR

t

CHR

MSM514260

E-60

MSM514260

E-70

Min. Max. Min. Max.

30

0
0
0

0
10
10
15
15
15

0
10
15
40
55
85
60

5
10
10






















35

0
0
0

0
15
10
20
20
20

0
15
20
50
65

100

70

5
10
10






















Unit Note

ns
ns 11
ns 8,11
ns 8
ns 9,11
ns 11
ns
ns
ns
ns 13
ns 10,11
ns 10,11
ns
ns 9
ns 9
ns 9
ns 9
ns 11
ns 11
ns 12

7/14

MSM514260E

Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization

cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.

2. The AC characteristics assume tT = 5ns.

3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times
(tT) are measured between VIH and VIL.

4. This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF.

5. Operation within the t
t

(Max.) is specified as a reference point only. If t

RCD

limit, then the access time is controlled by t

6. Operation within the t
t

(Max.) is specified as a reference point only. If t

RAD

(Max.) limit ensures that t

RCD

(Max.) limit ensures that t

RAD

CAC

(Max.) can be met.

RAC

is greater than the specified t

RCD

RCD

.

(Max.) can be met.

RAC

is greater than the specified t

RAD

RAD

limit, then the access time is controlled by tAA.

7. t

(Max.) and t

OFF

(Max.) define the time at which the output achieved the open circuit

OEZ

condition and are not referenced to output voltage levels.

8. t

9. t

RCH

WCS

or t

, t

must be satisfied for a read cycle.

RRH

, t

, t

CWD

RWD

AWD

and t

CPWD

are not restrictive operating parameters. They are included in

the data sheet as electrical characteristics only. If t

WCS

≥ t

(Min.), then the cycle is an early

WCS

write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle.
If t

CWD

≥ t

CWD

(Min.), t

RWD

≥ t

RWD

(Min.), t

AWD

≥ t

(Min.) and t

AWD

CPWD

≥ t

CPWD

(Min.), then

the cycle is a read modify write cycle and data out will contain data read from the selected cell; if
neither of the above sets of conditions is satisfied, then the condition of the data out (at access time)
is indeterminate.

(Max.)

(Max.)

10. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle,
and to the WE leading edge in an OE control write cycle, or a read modify write cycle.

11. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is
earlier.

12. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later.

13. t

should be satisfied by both UCAS and LCAS.

CWL

14. tCP is determined by the time both UCAS and LCAS are high.

8/14

Timing Chart

WCStWCHtCWLtASRtRAHtASCtCRPtRPtRCtRAS

DHtRWL

CSHtCRPtRCDtRSHtCAS

CAHtRADtRALtDStWP

IHVIL

IHVIL

IHVIL

WE

IHVIL

IHVIL

IHVIL

OFFtCLZtCACtOEAtASCtRRHtRAHtASRtRADtRALtCRPtCAHtCRPtRCDtRC

RAStRPtCSHtRSHtCAS

RACtAAtRCStROH

RCHtOEZ

IHVIL

IHVIL

IHVIL

WE

IHVIL

IHVIL

OHVOL

• Read Cycle

MSM514260E

RAS

CAS

Address

OE

DQ

V

t

V

V

Row

Column

V

t

V

t

V

Open

Valid Data-out

t

• Write Cycle (Early Write)

V

RAS

CAS

V

V

Address

V

V

OE

Row

“H” or “L”

t

t

Column

t

DQ

t

V

Valid Data-in

Open

“H” or “L”

9/14

• Read Modify Write Cycle

DHtDStOEZtCLZtOEDtAAtOEHtRWDtCWDtCWLtRWLtCAHtASCtASRtRAHtRADtCRPtRCDtRSHtCAStCRPtCAC

Data-out

CSH

RACtOEAtRCStAWDtWPtRWCtRAStRP

IHVIL

IHVIL

IHVIL

WE

IHVIL

IHVIL

I/OHVI/OL

Data-in

V

RAS

V

CAS

MSM514260E

t

Address

OE

DQ

V

Row

Column

V

V

t

V

Valid

Valid

t

“H” or “L”

10/14

• Fast Page Mode Read Cycle

WPtRWLtWCHtCWLtWPtCWLtWCHtWPtWCHtCSHtRALtCRPtDHtDStDHtDStDHtDS

Data-in

WCStWCStWCStASCtCAHtASCtCAHtRADtASRtASCtRAHtRCDtCRPtCAStCAStRSHtCPtCAStRPtRHPC

Data-in

Data-in

CAHtCPtPC

IHVIL

IHVIL

IHVIL

WE

IHVIL

IHVILtRASP

CWL

Note: OE = “H” or “L”

PCtCAStOEZtCACtOFFtCACtCLZtOEAtCSHtCACtOEZtRRHtRACtOEAtRALtASCtCAHtRCStRCHtCPAtAAtAAtRCHtRCStCAHtASCtRAHtRADtRCStASRtASCtCPtCAStRSHtRASPtCAStCPtRCDtCRPtCLZtCAH

CPAtRP

IHVIL

IHVIL

IHVIL

WE

IHVIL

IHVIL

OHVOLtRHCP

CRPtRCHtAAtOEAtOFFtOEZ

CLZtOFF

MSM514260E

RAS

CAS

Address

OE

DQ

V

t

t

V

V

Row Column Column Column

V

V

t

t

V

Valid

Data-out

Valid

Data-out

Valid

Data-out

• Fast Page Mode Write Cycle (Early Write)

RAS

V

V

CAS

Address

V

Row Column Column Column

V

“H” or “L”

t

t

t

t

DQ

V

Valid

Valid

Valid

“H” or “L”

11/14

• Fast Page Mode Read Modify Write Cycle

Note: WE, OE = “H” or “L”

ASRtRAHtCRPtRPCtRPtRAStRCtOFF

IHVIL

IHVILVIHVIL

OHVOL

AAtDHtDStROHtCPWDtRWLtCWLtRCS

WPtCPWD

CWDtCWLtCWDtAWDtRALtCAHtCRPtCPtCAStCLZtCAStASCtASCtOEDtDHtOEZtOEDtCACtOEDtDHtOEZtOEAtAWD

WPtDStAAtDS

RPtRAHtRSHtASRtRADtCAH

CSHtCAStRACtRASPtOEZtRCStCACtPRWC

RCStCACtCLZtCLZtWPtCWLtAWDtRCDtCPAtCPtOEAtAAtCPAtOEAtPWDtCWDtCAHtASC

IHVIL

IHVIL

IHVIL

WE

IHVIL

IHVIL

I/OHVI/OL

MSM514260E

RAS

CAS

Address

OE

V

t

V

t

V

Row

Column

t

Column

t

Column

V

t

t

t

V

V

DQ

• RAS-only Refresh Cycle

V

RAS

CAS

V

Address

V

DQ

Out

In

Note: Out = Valid Data-out, In = Valid Data-in

In InOut Out

“H” or “L”

t

Row

Open

“H” or “L”

12/14

• CAS before RAS Refresh Cycle

OFFtRPCtRPtRCtRAStCHRtCSRtRPtCPtRPCVIHVIL

IHVILVOHVOL

Note: WE, OE, Address = “H” or “L”

OFFtRACtCLZtOEZtROHtOEAtCACtRRHtAAtRALtRCStCAHtRAHtASRtASC

RADtRPtRAStRCtRPtCHRtRAStRSHtRCDtCRPtRC

IHVIL

IHVIL

IHVIL

WE

IHVIL

IHVIL

OHVOL

Valid Data-out

RAS

MSM514260E

CAS

V

DQ

• Hidden Refresh Read Cycle

V

RAS

V

CAS

Address

V

Row

t

Open

“H” or “L”

t

Column

OE

DQ

V

t

V

V

Open

“H” or “L”

13/14

Hidden Refresh Write Cycle

DStDHtWCHtRALtWPtWCStCAHtRAHtASRtASC

RADtRPtRAStRCtRPtCHRtRAStRSHtRCDtCRPtRC

IHVIL

IHVIL

IHVIL

WE

IHVIL

IHVIL

IHVIL

Valid Data-in

MSM514260E

RAS

CAS

Address

OE

DQ

V

V

t

V

Row

Column

V

V

t

V

“H” or “L”

14/14

NOTICE

1. The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.

2. The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit and assembly designs.

3. When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.

OKI assumes no responsibility or liability whatsoever for any failure or unusual or

4.

unexpected operation resulting from misuse, neglect, improper installation, repair, alteration

or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.

5.

Neither indemnity against nor license of a third party's industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party's right which may result from the use thereof.

6.

The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to:traffic control, automotive, safety, aerospace,
nuclear power control, and medical, including lift support and maintenance.

7. Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.

8. No part of the contents contained herein may be reprinted or reproduced without our prior
permission.

Copyright 1997 OKI ELECTRIC INDUSTRY CO.,LTD.