Page 1
E2L0031-17-Y1
¡ Semiconductor MSM514223B
¡ Semiconductor
This version: Jan. 1998
Previous version: Dec. 1996
MSM514223B
262,263-Word ¥ 4-Bit Field Memory
DESCRIRTION
The OKI MSM514223B is a high performance 1-Mbit, 256K ¥ 4-bit, Field Memory. It is designed
for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital
movies and Multi-media systems. It is a FRAM for wide or low end use as general commodity
TVs and VTRs, exclusively. The MSM514223B is not designed for the other use or high end use
in medical systems, professional graphics systems which require long term picture, and data
storage systems and others. The 1-Mbit capacity fits one field of a conventional NTSC TV screen
and cascaded two MSM514223Bs make one frame of the screen: more than two MSM514223Bs
can be cascaded directly without any delay devices among the MSM514223Bs. (Cascading of
MSM514223B provides larger storage depth or a longer delay).
Each of the 4-bit planes has separate serial write and read ports that employ independent control
clocks to support asynchronous read and write operations. Different clock rates are also
supported that allow alternate data rates between write and read data streams.
The MSM514223B provides high speed FIFO, First-In First-Out, operation without external
refreshing: it refreshes its DRAM storage cells automatically, so that it appears fully static to the
users.
Moreover, fully static type memory cells and decoders for serial access enable refresh free serial
access operation, so that serial read and/or write control clock can be halted high or low for any
duration as long as the power is on. Internal conflicts of memory access and refreshing
operations are prevented by special arbitration logic.
The MSM514223B's function is simple, and similar to a digital delay device whose delay-bitlength is easily set by reset timing. The delay length, number of read delay clocks between write
and read, is determined by externally controlled write and read reset timings.
Additional SRAM serial registers, or line buffers for the initial access of 256 ¥ 4-bit enable high
speed first-bit-access with no clock delay just after the write or read reset timings.
The MSM514223B is similar in operation and functionality to OKI 1-Mbit Field Memory
MSM514221B besides direct cascade capability. (As for MSM514221B operation compatible 2Mbit Field Memory, OKI has MSM518221 as a sister device of MSM518222).
Additionally, the MSM514223B has write mask function or input enable function (IE), and readdata skipping function or output enable function (OE). The differences between write enable
(WE) and input enable (IE), and between read enable (RE) and output enable (OE) are that WE
and RE can stop serial write/read address increments but IE and OE can not stop the increment
when write/read clocking is continuously applied to MSM514223B. The input enable (IE)
function allows the user to write into selected locations of the memory only, leaving the rest of
the memory contents unchanged. This facilitate data processing to display a "picture in picture"
on a TV screen.
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¡ Semiconductor MSM514223B
FEATURES
• Single power supply: 5 V ±10%
• 512 Rows ¥ 512 Column ¥ 4 bits
• Fast FIFO (First-in First-out) operation
• High speed asynchronous serial access
Read/Write cycle time 30 ns/40 ns/60 ns
Access time 25 ns/30 ns/50 ns
• Direct cascading capability
• Write mask function (Input enable control)
• Data skipping function (Output enable control)
• Self refresh (No refresh control is required)
• Package:
18-pin 300 mil plastic DIP (DIP18-P-300-2.54-W1) (Product : MSM514223B-xxRS)
xx indicates speed rank.
PRODUCT FAMILY
Family Cycle Time (Min.)Access Time (Max.) Package
MSM514223B-30RS 30 ns25 ns
MSM514223B-40RS 40 ns30 ns 300 mil 18-pin DIP
MSM514223B-60RS 60 ns50 ns
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¡ Semiconductor MSM514223B
PIN CONFIGURATION (TOP VIEW)
IE
RSTW
SWCK
DIN0
DIN1
DIN2
DIN3
SS
1
2WE
3
4
5
6
7
8
9V
18
17
16
15
14
13
12
11
10 D
V
CC
OE
RE
RSTR
SRCK
D
OUT
D
OUT
D
OUT
OUT
0
1
2
3
18-Pin Plastic DIP
Pin Name Function
SWCK Serial Write Clock
SRCK Serial Read Clock
WE Write Enable
RE Read Enable
IE Input Enable
OE Output Enable
RSTW Write Reset Clock
RSTR Read Reset Clock
0 - 3 Data Input
D
IN
D
0 - 3 Data Output
OUT
V
CC
V
SS
Power Supply (5 V)
Ground (0 V)
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¡ Semiconductor MSM514223B
BLOCK DIAGRAM
D
(¥ 4)
OUT
Data-Out
Buffer (¥ 4)
120 Word
Sub-Register (¥ 4)
120 Word
Sub-Register (¥ 4)
OE
Serial Read Controller
512 Word Serial Read Register (¥ 4)
Read Line Buffer
Low-Half (¥ 4)
Write Line Buffer
Low-Half (¥ 4)
RE RSTR SRCK
Read Line Buffer
High-Half (¥ 4)
256 (¥ 4) 256 (¥ 4)
256K (¥ 4)
Memory
Array
256 (¥ 4) 256 (¥ 4)
Write Line Buffer
High-Half (¥ 4)
Decoder
X
Read/Write
and Refresh
Controller
Clock
Oscillator
Data-In
Buffer (¥ 4)
DIN (¥ 4)
512 Word Serial Write Register (¥ 4)
Serial Write Controller
WE RSTW SWCKIE
V
BB
Generator
4/14
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¡ Semiconductor MSM514223B
OPERATION
Write Operation
The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is
accomplished by cycling SWCK, and holding WE high after the write address pointer reset
operation or RSTW.
Each write operation, which begins after RSTW, must contain at least 130 active write cycles, i.e.
SWCK cycles while WE is high. To transfer the last data to the DRAM array, which at that time
is stored in the serial data registers attached to the DRAM array, an RSTW operation is required
after the last SWCK cycle.
Note that every write timing of MSM514223B is delayed by one clock compared with read
timings for easy cascading without any interface delay devices.
Write Reset : RSTW
The first positive transition of SWCK after RSTW becomes high resets the write address counters
to zero. RSTW setup and hold times are referenced to the rising edge of SWCK. Because the write
reset function is solely controlled by the SWCK rising edge after the high level of RSTW, the states
of WE and IE are ignored in the write reset cycle.
Before RSTW may be brought high again for a further reset operation, it must be low for at least
two SWCK cycles.
Data Inputs : DIN0 - 3
Write Clock : SWCK
The SWCK latches the input data on chip when WE is high, and also increments the internal write
address pointer. Data-in setup time tDS, and hold time tDH are referenced to the rising edge of
SWCK.
Write Enable : WE
WE is used for data write enable/disable control. WE high level enables the input, and WE low
level disables the input and holds the internal write address pointer. There are no WE disable
time (low) and WE enable time (high) restrictions, because the MSM514223B is in fully static
operation as long as the power is on. Note that WE setup and hold times are referenced to the
rising edge of SWCK.
Input Enable : IE
IE is used to enable/disable writing into memory. IE high level enables writing. The internal
write address pointer is always incremented by cycling SWCK regardless of the IE level. Note
that IE setup and hold times are referenced to the rising edge of SWCK.
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¡ Semiconductor MSM514223B
Read Operation
The read operation is controlled by three clocks, SRCK, RSTR, and RE. Read operation is
accomplished by cycling SRCK, and holding RE high after the read address pointer reset
operation or RSTR.
Each read operation, which begins after RSTR, must contain at least 130 active read cycles, i.e.
SRCK cycles while RE is high.
Read Reset : RSTR
The first positive transition of SRCK after RSTR becomes high resets the read address counters
to zero. RSTR setup and hold times are referenced to the rising edge of SRCK. Because the read
reset function is solely controlled by the SRCK rising edge after the high level of RSTR, the states
of RE and OE are ignored in the read reset cycle.
Before RSTR may be brought high again for a further reset operation, it must be low for at least
two SRCK cycles.
Data Out : D
OUT
0 - 3
Read Clock : SRCK
Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high
during a read operation. The SRCK input increments the internal read address pointer when RE
is high.
The three-state output buffer provides direct TTL compatibility ( no pullup resistor required).
Data out is the same polarity as data in. The output becomes valid after the access time interval
tAC that begins with the rising edge of SRCK. There are no output valid time restriction on
MSM514223B.
Read Enable : RE
The function of RE is to gate of the SRCK clock for incrementing the read pointer. When RE is
high before the rising edge of SRCK, the read pointer is incremented. When RE is low, the read
pointer is not incremented. RE setup times (t
t
) are referenced to the rising edge of the SRCK clock.
RDSH
RENS
and t
) and RE hold times (t
RDSS
RENH
and
Output Enable : OE
OE is used to enable/disable the outputs. OE high level enables the outputs. The internal read
address pointer is always incremented by cycling SRCK regardless of the OE level. Note that OE
setup and hold times are referenced to the rising edge of SRCK.
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¡ Semiconductor MSM514223B
Power-up and Initialization
On power-up, the device is designed to begin proper operation after at least 100 ms after V
CC
has
stabilized to a value within the range of recommended operating conditions. After this 100 ms
stabilization interval, the following initialization sequence must be performed.
Because the read and write address counters are not valid after power-up, a minimum of 130
dummy write operations (SWCK cycles) and read operations (SRCK cycles) must be performed,
followed by an RSTW operation and an RSTR operation, to properly initialize the write and the
read address pointer. Dummy write cycles/RSTW and dummy read cycles/RSTR may occur
simultaneously.
If these dummy read and write operations start while VCC and/or the substrate voltage has not
stabilized, it is necessary to perform an RSTR operation plus a minimum of 130 SRCK cycles plus
another RSTR operation, and an RSTW operation plus a minimum of 130 SRCK cycles plus
another RSTW operation to properly initialize read and write address pointers.
Old/New Data Access
There must be a minimum delay of 600 SWCK cycles between writing into memory and reading
out from memory. If reading from the first field starts with an RSTR operation, before the start
of writing the second field (before the next RSTW operation), then the data just written will be
read out.
The start of reading out the first field of data may be delayed past the beginning of writing in the
second field of data for as many as 119 SWCK cycles. If the RSTR operation for the first field readout occurs less than 119 SWCK cycles after the RSTW operation for the second field write-in, then
the internal buffering of the device assures that the first field will still be read out. The first field
of data that is read out while the second field of data is written is called “old data”.
In order to read out “new data”, i.e., the second field written in, the delay between an RSTW
operation and an RSTR operation must be at least 600 SRCK cycles. If the delay between RSTW
and RSTR operations is more than 120 but less than 600 cycles, then the data read out will be
undetermined. It may be “old data” or “new” data, or a combination of old and new data. Such
a timing should be avoided.
Cascade Operation
The MSM514223B is designed to allow easy cascading of multiple memory devices. This
provides higher storage depth, or a longer delay than can be achieved with only one memory
device.
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¡ Semiconductor MSM514223B
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Symbol Condition Rating
Input Output Voltage
Output Current
Power Dissipation
Operating Temperature
Storage Temperature
V
T
I
OS
P
D
T
opr
T
stg
Recommended Operating Conditions
Parameter Symbol Min. UnitTyp. Max.
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
V
CC
V
SS
V
IH
V
IL
4.5
2.4
–1.0
DC Characteristics
Parameter Symbol Condition Min.
Input Leakage Current
Output Leakage Current
Output "H" Level Voltage
Output "L" Level Voltage
Operating Current
Standby Current
V
V
I
I
I
I
LO
OH
CC1
CC2
0 < VI < V
LI
OL
CC
Minimum Cycle Time, Output Open
at Ta = 25°C, V
SS
Ta = 25°C
Ta = 25°C
—
—
5.0
0
0
V
CC
0
+ 1, Other Pins Tested at V = 0 V
0 < VO < V
I
OH
I
OL
CC
= –5 mA
= 4.2 mA
-30
-40
-60
Input Pin = V
IH
/ V
IL
–1.0 to 7.0
0 to 70
–55 to 150
VCC + 1
–10
–10
2.4
—
—
—
—
—
50
1
5.5
0
0.8
Max. Unit
10
10
—
0.4
50
45
35
10
Unit
V
mA
W
°C
°C
V
V
V
V
mA
mA
V
V
mA
mA
Capacitance
Input Capacitance (D
Output Capacitance (D
Parameter Unit
, SWCK, SRCK, RSTW, RSTR, WE, RE, IE, OE)
IN
)
OUT
(Ta = 25°C, f = 1 MHz)
Symbol Max.
C
I
C
O
7
7
pF
pF
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¡ Semiconductor MSM514223B
AC Characteristics
Parameter Symbol Unit
Access Time from SRCK
Hold Time from SRCK
D
OUT
D
Enable Time from SRCK
OUT
SWCK "H" Pulse Width
SWCK "L" Pulse Width
Input Data Setup Time
Input Data Hold Time
WE Enable Setup Time
WE Enable Hold Time
WE Disable Setup Time
WE Disable Hold Time
IE Enable Setup Time
IE Enable Hold Time
IE Disable Setup Time
IE Disable Hold Time
WE "H" Pulse Width
WE "L" Pulse Width
IE "H" Pulse Width
IE "L" Pulse Width
RSTW Setup Time
RSTW Hold Time
SRCK "H" Pulse Width
SRCK "L" Pulse Width
RE Enable Setup Time
RE Enable Hold Time
RE Disable Setup Time
RE Disable Hold Time
OE Enable Setup Time
OE Enable Hold Time
OE Disable Setup Time
OE Disable Hold Time
RE "H" Pulse Width
RE "L" Pulse Width
OE "H" Pulse Width
OE "L" Pulse Width
RSTR Setup Time
RSTR Hold Time
SWCK Cycle Time
SRCK Cycle Time
Transition Time (Rise and Fall)
t
AC
t
DDCK
t
DECK
t
WSWH
t
WSWL
t
DS
t
DH
t
WENS
t
WENH
t
WDSS
t
WDSH
t
IENS
t
IENH
t
IDSS
t
IDSH
t
WWEH
t
WWEL
t
WIEH
t
WIEL
t
RSTWS
t
RSTWH
t
WSRH
t
WSRL
t
RENS
t
RENH
t
RDSS
t
RDSH
t
OENS
t
OENH
t
ODSS
t
ODSH
t
WREH
t
WREL
t
WOEH
t
WOEL
t
RSTRS
t
RSTRH
t
SWC
t
SRC
t
T
MSM514223B-30
Min. Max.
—
6
6
12
12
5
6
0
5
0
5
0
5
0
5
5
5
5
5
0
10
12
12
0
5
0
5
0
5
0
5
5
5
5
5
0
10
30
30
3
25
—
25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30
= 5 V ±10%, Ta = 0°C to 70°C)
(V
CC
MSM514223B-40
Min. Max.
—
6
6
17
17
5
6
0
5
0
5
0
5
0
5
10
10
10
10
0
10
17
17
0
5
0
5
0
5
0
5
10
10
10
10
0
10
40
40
3
30
—
25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30
MSM514223B-60
Min. Max.
—
6
6
17
17
5
6
0
5
0
5
0
5
0
5
10
10
10
10
0
10
17
17
0
5
0
5
0
5
0
5
10
10
10
10
0
10
60
60
3
50
—
25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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¡ Semiconductor MSM514223B
Notes: 1. Input signal reference levels for the parameter measurement are VIH = 2.4 V and V
= 0.8 V. The transition time tT is defined to be a transition time that signal transfers
between VIH = 2.4 V and VIL = 0.8 V.
2. AC measurements assume tT = 3 ns.
3. Read address must have more than a 600 address delay than write address in every
cycle when asynchronous read/write is performed.
4. Read must have more than a 600 address delay than write in order to read the data
written in a current series of write cycles which has been started at last write reset
cycle: this is called "new data read".
When read has less than a 119 address delay than write, the read data are the data
written in a previous series of write cycles which had been written before at last write
reset cycle: this is called "old data read".
5. When the read address delay is between more than 120 and less than 599, read data
will be undetermined. However, normal write is achieved in this address condition.
6. Outputs are measured with a load equivalent to 2 TTL loads and 30 pF.
Output reference levels are VOH = 2.4 V and VOL = 0.8 V.
IL
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¡ Semiconductor MSM514223B
TIMING WAVEFORM
Write Cycle Timing (Write Reset)
SWCK
RSTW
D
WE
IE
n Cycle 0 Cycle 1 Cycle
t
t
t
t
T
t
DS
IN
RSTWS
t
DH
n – 1 n
RSTWH
WSWHtWSWL
t
SWC
012
2 Cycle
– V
– V
– V
– V
– V
– V
– V
– V
– V
– V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
Write Cycle Timing (Write Enable)
n Cycle Disable Cycle Disable Cycle n + 1 Cycle
SWCK
n
t
t
WWEH
WE
D
IE
RSTW
t
WENH
t
WWEL
IN
n – 1
WDSH
t
WDSS
t
WENS
n + 1
– V
– V
– V
– V
– V
– V
– V
– V
– V
– V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
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¡ Semiconductor MSM514223B
Write Cycle Timing (Input Enable)
n Cycle n + 1 Cycle n + 2 Cycle n + 3 Cycle
SWCK
– V
– V
IH
IL
t
IENH
IE
t
WIEL
D
IN
n – 1
n
WE
RSTW
Read Cycle Timing (Read Reset)
t
IDSH
t
WIEH
t
IDSS
t
IENS
n + 3
– V
– V
– V
– V
– V
– V
– V
– V
IH
IL
IH
IL
IH
IL
IH
IL
SRCK
RSTR
D
OUT
RE
OE
n Cycle 0 Cycle 1 Cycle
t
t
T
RSTRS
t
AC
n – 1 n
t
RSTRH
2 Cycle
t
WSRHtWSRL
t
SRC
t
DDCK
012
– V
– V
– V
– V
– V
– V
– V
– V
– V
– V
IH
IL
IH
IL
OH
OL
IH
IL
IH
IL
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Page 13
¡ Semiconductor MSM514223B
Read Cycle Timing (Read Enable)
SRCK
RE
D
OUT
OE
RSTR
n Cycle
t
RENH
t
WREL
n – 1 n + 1
Disable Cycle Disable Cycle n + 1 Cycle
t
RDSH
t
WREH
t
RDSS
t
RENS
n
– V
– V
– V
– V
– V
– V
– V
– V
– V
– V
IH
IL
IH
IL
OH
OL
IH
IL
IH
IL
Read Cycle Timing (Output Enable)
SRCK
OE
D
OUT
RE
RSTR
n Cycle
t
OENH
t
WOEN
n – 1 n + 3
n + 1 Cycle n + 2 Cycle n + 3 Cycle
t
ODSH
t
WOEH
n Hi-Z
t
ODSS
t
OENS
t
DECK
– V
– V
– V
– V
– V
– V
– V
– V
– V
– V
IH
IL
IH
IL
OH
OL
IH
IL
IH
IL
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Page 14
¡ Semiconductor MSM514223B
PACKAGE DIMENSIONS
(Unit : mm)
DIP18-P-300-2.54-W1
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.35 TYP.
14/14
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