Datasheet MSM5117400B-70TS-K, MSM5117400B-70TS-L, MSM5117400B-60TS-K, MSM5117400B-50TS-L, MSM5117400B-70SJ Datasheet (OKI)

215

¡ Semiconductor MSM5117400B

16M

DESCRIPTION

The MSM5117400B is a 4,194,304-word ¥ 4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS
technology. The MSM5117400B achieves high integration, high-speed operation, and low-power
consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer
metal CMOS process. The MSM5117400B is available in a 26/24-pin plastic SOJ or 26/24-pin plastic
TSOP.

FEATURES

• 4,194,304-word ¥ 4-bit configuration

• Single 5 V power supply, ±10% tolerance

• Input : TTL compatible, low input capacitance

• Output : TTL compatible, 3-state

• Refresh : 2048 cycles/32 ms

• Fast page mode, read modify write capability

• CAS before RAS refresh, hidden refresh, RAS-only refresh capability

• Multi-bit test mode capability

• Package options:
26/24-pin 300 mil plastic SOJ (SOJ26/24-P-300-1.27) (Product : MSM5117400B-xxSJ)
26/24-pin 300 mil plastic TSOP

(TSOPII26/24-P-300-1.27-K)

(Product : MSM5117400B-xxTS-K)

(TSOPII26/24-P-300-1.27-L)

(Product : MSM5117400B-xxTS-L)
xx indicates speed rank.

PRODUCT FAMILY

¡ Semiconductor

MSM5117400B

4,194,304-Word ¥ 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE

MSM5117400B-70

70 ns

130 ns

90 ns

550 mW

660 mW

Family

Access Time (Max.)

Cycle Time

(Min.)

Standby (Max.)

Power Dissipation

MSM5117400B-50

t

RAC

50 ns

35 ns

t

AA

25 ns

20 ns

t

CAC

13 ns

20 ns

t

OEA

13 ns

MSM5117400B-60

60 ns

110 ns 605 mW

30 ns 15 ns 15 ns

Operating (Max.)

5.5 mW

E2G0035-17-41

216

MSM5117400B ¡ Semiconductor

16M

PIN CONFIGURATION (TOP VIEW)

26/24-Pin Plastic SOJ 26/24-Pin Plastic TSOP

(K Type)

26/24-Pin Plastic TSOP

(L Type)

Pin Name Function

A0 - A10

Address Input

RAS Row Address Strobe
CAS Column Address Strobe

DQ1 - DQ4 Data Input/Data Output

OE Output Enable

WE Write Enable

V

CC

Power Supply (5 V)

V

SS

Ground (0 V)

3

4

5

9

10

11

12

13

DQ2

A0

A1

A2

A3

V

CC

24

23

22

18

17

16

15

14

DQ3

A7

A6

A5

A4

V

SS

2DQ1 25 DQ4

1

V

CC

26 V

SS

3

4

5

9

10

11

12

13

24

23

22

18

17

16

15

14

2

25

1

26

24

23

22

18

17

16

15

14

3

4

5

9

10

11

12

13

25

2

26

1

6NC 21 A9 21 21 6

8A10 19 A8 19 19 8

6

8

DQ2

A0

A1

A2

A3

V

CC

DQ1

V

CC

NC

A10

DQ3

A7

A6

A5

A4

V

SS

DQ4

V

SS

A9

A8

DQ3

A7

A6

A5

A4

V

SS

DQ4

V

SS

A9

A8

DQ2

A0

A1

A2

A3

V

CC

DQ1

V

CC

NC

A10

WE CAS WE CAS CAS WE

RAS OE RAS OE OE RAS

NC No Connection

Note : The same power supply voltage must be provided to every VCC pin, and the same GND

voltage level must be provided to every VSS pin.

217

¡ Semiconductor MSM5117400B

16M

BLOCK DIAGRAM

Timing

Generator

RAS

CAS

Timing

Generator

Internal
Address
Counter

Row

Address

Buffers

Row

De-

coders

Word

Drivers

Memory

Cells

Refresh

Control Clock

Sense

Amplifiers

Column

Decoders

Write
Clock

Generator

I/O

Selector

Output

Buffers

WE

OE

4

DQ1 - DQ4

4

4

4

4

4

Input

Buffers

4

11

A0 - A10

11

1111

Column
Address

Buffers

V

CC

V

SS

On Chip

IV

CC

Generator

On Chip

V

BB

Generator

218

MSM5117400B ¡ Semiconductor

16M

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Voltage on Any Pin Relative to V

SS

Short Circuit Output Current

Power Dissipation

Operating Temperature

Storage Temperature

V

IN,VOUT

Symbol

I

OS

P

D

*

T

opr

T

stg

–0.5 to VCC + 0.5

50

1

0 to 70

–55 to 150

Rating

mA

W

°C

°C

Parameter

V

Unit

Voltage on VCC Supply Relative to V

SS

V

CC

–0.5 to 7 V

Recommended Operating Conditions

*: Ta = 25°C

Power Supply Voltage

Input High Voltage

Input Low Voltage

V

CC

Symbol

V

SS

V

IH

V

IL

5.0

0

—

—

Typ.Parameter

4.5

0

2.4

–0.5

*2

Min.

5.5

0

V

CC

+ 0.5

*1

0.8

Max.

(Ta = 0°C to 70°C)

V

Unit

V

V

V

Notes : *1. The input voltage is VCC + 2.0 V when the pulse width is less than 20 ns (the pulse width

is with respect to the point at which VCC is applied).

*2. The input voltage is VSS – 2.0 V when the pulse width is less than 20 ns (the pulse width

is with respect to the point at which VSS is applied).

Capacitance

Input Capacitance (A0 - A10)
Input Capacitance (RAS, CAS, WE, OE)

Output Capacitance (DQ1 - DQ4)

C

IN1

Symbol

C

IN2

C

I/O

5

7

7

Max.

pF

Unit

pF

pF

Parameter

(V

CC

= 5 V ±10%, Ta = 25°C, f = 1 MHz)

—

—

—

Typ.

219

¡ Semiconductor MSM5117400B

16M

DC Characteristics

Notes : 1. ICC Max. is specified as ICC for output open condition.

2. The address can be changed once or less while RAS = VIL.

3. The address can be changed once or less while CAS = VIH.

IOH = –5.0 mAOutput High Voltage

I

OL

= 4.2 mAOutput Low Voltage

0 V £ V

I

£ 6.5 V;

All other pins notInput Leakage Current

under test = 0 V

DQ disable

Output Leakage Current

0 V £ V

O

£ 5.5 V

RAS, CAS cycling,

Average Power

t

RC

= Min.

Supply Current

(Operating)

RAS, CAS = V

IH

Power Supply

RAS, CAS

Current (Standby)

RAS cycling,Average Power
CAS = V

IH

,Supply Current

t

RC

= Min.(RAS-only Refresh)

RAS = V

IH

,

Power Supply

CAS = V

IL

,

Current (Standby)

DQ = enable

Average Power

CAS before RAS

Supply Current
(CAS before RAS Refresh)

RAS = VIL,Average Power
CAS cycling,Supply Current

t

PC

= Min.(Fast Page Mode)

V

OH

V

OL

I

LI

I

LO

I

CC1

I

CC2

I

CC3

I

CC5

I

CC6

I

CC7

≥ VCC –0.2 V

RAS cycling,

Parameter Condition

MSM5117400

B-50

MSM5117400

B-60

MSM5117400

B-70

(VCC = 5 V ±10%, Ta = 0°C to 70°C)

Symbol

Min.

2.4
0

–10

–10

—

—

—

—

—

—

—

Max.

V

CC

0.4

10

10

120

2

1

120

120

110

5

Min.

2.4
0

–10

–10

—

—

—

—

—

—

—

Max.

V

CC

0.4

10

10

110

2

1

110

110

100

5

Min.

2.4
0

–10

–10

—

—

—

—

—

—

—

Max.

V

CC

0.4

10

10

100

2

1

100

100

90

5

Unit

V
V

mA

mA

mA

mA

mA

mA

mA

mA

Note

1, 2

1, 2

1, 2

1, 3

1

1

220

MSM5117400B ¡ Semiconductor

16M

AC Characteristics (1/2)

Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write

Cycle Time
Access Time from RAS
Access Time from CAS

Access Time from Column Address
Access Time from CAS Precharge

CAS to Data Output Buffer Turn-off Delay Time

Transition Time

RAS Precharge Time
RAS Pulse Width
RAS Pulse Width (Fast Page Mode)
RAS Hold Time

CAS Pulse Width
CAS Hold Time

RAS to CAS Delay Time
RAS to Column Address Delay Time

CAS to RAS Precharge Time

Row Address Set-up Time

Row Address Hold Time

Column Address Set-up Time

Column Address Hold Time

Column Address to RAS Lead Time

Read Command Set-up Time

Read Command Hold Time
Read Command Hold Time referenced to RAS

Access Time from OE

OE to Data Output Buffer Turn-off Delay Time

Refresh Period

RAS Hold Time referenced to OE

RAS Hold Time from CAS Precharge

t

RC

t

RWC

t

PC

t

PRWC

t

RAC

t

CAC

t

AA

t

CPA

t

OFF

t

T

t

RP

t

RAS

t

RASP

t

RSH

t

CAS

t

CSH

t

RCD

t

RAD

t

CRP

t

ASR

t

RAH

t

ASC

t

CAH

t

RAL

t

RCS

t

RCH

t

RRH

t

OEA

t

OEZ

t

REF

t

ROH

t

RHCP

Output Low Impedance Time from CAS t

CLZ

CAS Precharge Time (Fast Page Mode) t

CP

Parameter

MSM5117400

B-60

MSM5117400

B-70

MSM5117400

B-50

(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12

Symbol

Note

4, 5, 6

4, 5
4, 6

4

7

5
6

8

8

4

7

4

3

Max.

—
—
—

—

60

15
30

35

—

15

50

—

10,000

100,000

—

—

10,000

—

45
30

—

—

—

—

—
—

—

—

—

15

15

32

—

Unit

ns
ns
ns

ns

ns

ns
ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns
ns

ns

ns

ns

ns

ns
ns

ns

ns

ns

ns

ns

ms

ns

ns

Min.

90

131

35

76

—

—
—

—

0

0

3

30

50

50

13

7

13

50

17
12

5

0

7

0

7

25

0

0

0

—

0

—

13

30

Max.

—
—
—

—

50

13
25

30

—

13

50

—

10,000

100,000

—

—

10,000

—

37
25

—

—

—

—

—
—

—

—

—

13

13

32

—

—

Min.

130
185

45

100

—

—
—

—

0

0

3

50

70

70

20

10

20

70

20
15

5

0

10

0

15

35

0

0

0

—

0

—

20

40

Max.

—
—
—

—

70

20
35

40

—

20

50

—

10,000

100,000

—

—

10,000

—

50
35

—

—

—

—

—
—

—

—

—

20

20

32

—

—

Min.

110
155

40

85

—

—
—

—

0

0

3

40

60

60

15

10

15

60

20
15

5

0

10

0

15

30

0

0

0

—

0

—

15

35 —

221

¡ Semiconductor MSM5117400B

16M

AC Characteristics (2/2)

Write Command Pulse Width

Write Command to CAS Lead Time

Write Command to RAS Lead Time

Data-in Set-up Time

CAS to WE Delay Time

RAS to WE Delay Time

Column Address to WE Delay Time

RAS to CAS Hold Time (CAS before RAS)

CAS Active Delay Time from RAS Precharge

Data-in Hold Time

Write Command Hold Time

OE Command Hold Time

OE to Data-in Delay Time

Write Command Set-up Time

RAS to CAS Set-up Time (CAS before RAS)

WE to RAS Precharge Time (CAS before RAS)
WE Hold Time from RAS (CAS before RAS)
RAS to WE Set-up Time (Test Mode)

CAS Precharge WE Delay Time

RAS to WE Hold Time (Test Mode)

t

WP

t

CWL

t

RWL

t

DS

t

CWD

t

RWD

t

AWD

t

CSR

t

CHR

t

RPC

t

DH

t

WCH

t

OEH

t

OED

t

WCS

t

WRP

t

WRH

t

WTS

t

CPWD

t

WTH

MSM5117400

B-60

MSM5117400

B-70

MSM5117400

B-50

(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12

Parameter

Symbol

Max.

10
10
10

ns
ns
ns

10
10
10

10
10
10

Note

10

9

9

9

10

9

9

10 ns10 10

Min.

10

15

15

0

40

85

55

10
10

5

10

10

15

15

0

60

Max.

ns

ns

ns

ns

ns

ns

ns

ns
ns

ns

ns

ns

ns

ns

ns

Unit

ns

Min.

7

13

13

0

36

73

48

10
10

5

7

7

13

13

0

53

Max. Min.

10

20

20

0

50

100

65

10
10

5

15

15

20

20

0

70

—

—

—

—

—

—

—

—
—

—

—

—

—

—

—

—
—
—
—

—

—

—

—

—

—

—

—

—
—

—

—

—

—

—

—

—
—
—
—

—

—

—

—

—

—

—

—

—
—

—

—

—

—

—

—

—
—
—
—

—

222

MSM5117400B ¡ Semiconductor

16M

Notes: 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight

initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.

2. The AC characteristics assume tT = 5 ns.

3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times (tT) are measured between VIH and VIL.

4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.

5. Operation within the t

RCD

(Max.) limit ensures that t

RAC

(Max.) can be met.

t

RCD

(Max.) is specified as a reference point only. If t

RCD

is greater than the specified

t

RCD

(Max.) limit, then the access time is controlled by t

CAC

.

6. Operation within the t

RAD

(Max.) limit ensures that t

RAC

(Max.) can be met.

t

RAD

(Max.) is specified as a reference point only. If t

RAD

is greater than the specified

t

RAD

(Max.) limit, then the access time is controlled by tAA.

7. t

OFF

(Max.) and t

OEZ

(Max.) define the time at which the output achieves the open

circuit condition and are not referenced to output voltage levels.

8. t

RCH

or t

RRH

must be satisfied for a read cycle.

9. t

WCS

, t

CWD

, t

RWD

, t

AWD

and t

CPWD

are not restrictive operating parameters. They are

included in the data sheet as electrical characteristics only. If t

WCS

≥ t

WCS

(Min.), then
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If t

CWD

≥ t

CWD

(Min.) , t

RWD

≥ t

RWD

(Min.),

t

AWD

≥ t

AWD

(Min.) and t

CPWD

≥ t

CPWD

(Min.), then the cycle is a read modify write
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.

10. These parameters are referenced to the CAS leading edge in an early write cycle, and
to the WE leading edge in an OE control write cycle, or a read modify write cycle.

11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle.
This mode is latched and remains in effect until the exit cycle is generated. In a test mode
CA0 and CA1 are not used and each DQ pin now accesses 4-bit locations. Since all 4 DQ
pins are used, a total of 16 data bits can be written in parallel into the memory array.
In a read cycle, if 4 data bits are equal, the DQ pin will indicate a high level. If the 4 data
bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the
memory device returned to its normal operating state by performing a RAS-only
refresh cycle or a CAS before RAS refresh cycle.

12. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the
specified value. These parameters should be specified in test mode cycle by adding the
above value to the specified value in this data sheet.

See ADDENDUM F for AC Timing Waveforms