This NPN Silicon Epitaxial Planar Transistor is designed for general
purpose amplifier applications. This device is housed in the
SC-70/SOT-323 package which is designed for low power surface
mount applications.
Features
High h
Low V
, 210 -- 460
FE
CE(sat)
,<0.5V
Moisture Sensitivity Level 1
ESD Protection: Human Body Model > 4000 V
Machine Model > 400 V
These Devices are Pb--Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS (T
Rating
Collector-Base VoltageV
Collector-Emitter VoltageV
Emitter-Base VoltageV
Collector Current -- ContinuousI
Collector Current -- PeakI
THERMAL CHARACTERISTICS
CharacteristicSymbolMaxUnit
Power Dissipation (Note 1)P
Junction TemperatureT
Storage Temperature RangeT
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Device mounted on a FR-4 glass epoxy printed circuit board using the
minimum recommended footprint.
=25C)
A
SymbolValueUnit
(BR)CBO
(BR)CEO
(BR)EBO
C
C(P)
D
J
stg
60Vdc
50Vdc
7.0Vdc
100mAdc
200mAdc
150mW
150C
-- 55 to +150C
http://onsemi.com
COLLECTOR
3
1
BASE
1
2
SC--70 (SOT --323)
CASE 419
STYLE 3
2
EMITTER
3
MARKING DIAGRAM
ZR M G
G
1
ZR= Device Code
M= Date Code*
G= Pb--Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
ORDERING INFORMATION
DevicePackageShipping
MSD1819A--RT1GSC--70/
SOT--323
(Pb--Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
3000/Tape & Reel
†
Semiconductor Components Industries, LLC, 2010
October, 2010 -- Rev. 7
1Publication Order Number:
MSD1819A--RT1/D
Page 2
MSD1819A--RT1
ELECTRICAL CHARACTERISTICS
CharacteristicSymbolMinMaxUnit
Collector-Emitter Breakdown Voltage (IC=2.0mAdc,IB=0)V
Collector-Base Breakdown Voltage (IC=10mAdc, IE=0)
Emitter-Base Breakdown Voltage (IE=10mAdc, IE=0)
Collector-Base Cutoff Current (VCB=20Vdc,IE=0)I
Collector-Emitter Cutoff Current (VCE=10Vdc,IB=0)I
DC Current Gain (Note 2)
Collector-Emitter Saturation Voltage (Note 2)
2. Pulse Test: Pulse Width 300 ms, D.C. 2%.
=10Vdc,IC=2.0mAdc)
(V
CE
=2.0Vdc,IC= 100 mAdc)
(V
CE
= 100 mAdc, IB=10mAdc)
(I
C
(BR)CEO
V
(BR)CBO
V
(BR)EBO
CBO
CEO
h
FE1
h
FE2
V
CE(sat)
50--Vdc
60--Vdc
7.0--Vdc
--0.1
--0.1
210
90
340
--
mA
mA
--0.5Vdc
--
250
200
150
100
, POWER DISSIPATION (mW)
D
P
450
400
350
300
250
200
150
, DC CURRENT GAIN
FE
100
h
50
50
R
= 833C/W
θ
JA
0
TA, AMBIENT TEMPERATURE (C)IC, COLLECTOR CURRENT (A)
Figure 1. Derating CurveFigure 2. Collector Emitter Saturation Voltage
150C(10V)
150C(2V)
25C(10V)
25C(2V)
-- 5 5 C(10V)
-- 5 5 C(2V)
0
IC, COLLECTOR CURRENT (A)IC, COLLECTOR CURRENT (A)
Figure 3. DC Current Gain vs. Collector
Current
150100500-- 5 0
10.10.010.0010.0001
0.30
0.25
0.20
0.15
0.10
, COLLECTOR--EMITTER
SATURATION VOLTAGE (V)
0.05
CE(sat)
V
0
0.95
0.85
0.75
0.65
0.55
TION VOLTAGE (V)
0.45
, BASE --EMITTER SATURA-
0.35
BE(sat)
V
0.25
IC/IB=10
150C
25C
-- 5 5 C
vs. Collector Current
IC/IB=10
-- 5 5 C
25C
150C
Figure 4. Base Emitter Saturation Voltage vs.
Collector Current
10.10.010.0010.0001
10.10.010.0010.0001
http://onsemi.com
2
Page 3
MSD1819A--RT1
, BASE--EMITTER TURN ON VOLTAGE (V)
BE(on)
V
, INPUT CAPACITANCE (pF)
ibo
C
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
-- 5 5 C
25C
150C
IC, COLLECTOR CURRENT (A)IB, BASE CURRENT (A)
Figure 5. Base Emitter Turn--On Voltage vs.
Collector Current
18
17
16
15
14
C
13
12
11
10
9
8
7
(pF)
ibo
Veb, EMITTER BASE VOLTAGE (V)
Figure 7. Input Capacitance
1.2
1.0
0.8
0.6
0.4
0.2
, COLLECTOR--EMITTER VOLTAGE (V)
0
CE
V
10.10.010.0010.0001
500 mA
1mA
10 mA
50 mA
TA=25C
IC= 100 mA
0.010.0010.00010.000010.000001
Figure 6. Collector Saturation Region
6.0
5.5
5.0
4.5
4.0
C
(pF)
3.5
3.0
2.5
2.0
, OUTPUT CAPACITANCE (pF)
obo
1.5
C
6543210
1.0
obo
Vcb, COLLECTOR BASE VOLTAGE (V)
35
40302520151050
Figure 8. Output Capacitance
http://onsemi.com
3
Page 4
0.05 (0.002)
l
D
e1
3
H
E
12
e
A1
MSD1819A--RT1
PACKAGE DIMENSIONS
SC--70 (SOT--323)
CASE 419--04
ISSUE N
E
b
A
A2
L
SOLDERING FOOTPRINT*
0.65
0.025
NOTES:
1. DIMENS IONING AND TOLERANCING PER ANSI Y14.5M, 1982.
*For additional information on our Pb--Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor andare registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty,representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems i ntended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an
Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution C enter for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA