8,388,608-Word ¥ 32-Bit DRAM MODULE : FAST PAGE MODE TYPE WITH EDO
1
DESCRIPTION
The Oki MSC2383257A-xxBS16/DS16 is a fully decoded 8,388,608-word ¥ 32-bit CMOS dynamic
random access memory composed of sixteen 16-Mb DRAMs (4M ¥ 4) in SOJ. The mounting of
sixteen DRAMs together with decoupling capacitors on a 72-pin glass epoxy SIMM Package
supports any application where high density and large capacity of storage memory are required.
Note:Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to the conditions as detailed in the
operational sections of this data sheet. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Notes:1. ICC Max. is specified as ICC for output open condition.
2. Address can be changed once or less while RAS=VIL.
3. Address can be changed once or less while CAS=VIH.
121
Page 6
MSC2383257A-xxBS16/DS16¡ Semiconductor
AC Characteristics (1/2)
Parameter
Random Read or Write Cycle Time
Fast Page Mode Cycle Timet
Access Time from RASt
Access Time from CASt
Access Time from Column Addresst
Access Time from CAS Precharget
Output Low Impedance Time from CASt
Output Hold Time from CAS Lowt
CAS to Data Output Buffer Turn-off Delay Time
RAS to Data Output Buffer Turn-off Delay Time
WE to Data Output Buffer Turn-off Delay Time
Transition Timet
Refresh Periodt
RAS Precharge Timet
RAS Pulse Widtht
RAS Pulse Width (Fast Page Mode)t
RAS Hold Timet
CAS Precharge Timet
CAS Pulse Widtht
RAS Low to CAS High Delay Timet
CAS High to RAS Low Delay Timet
RAS Hold Time from CAS Precharget
RAS to CAS Delay Timet
RAS to Column Address Delay Timet
RAS to Second CAS Delay Timet
Row Address Set-up Timet
Row Address Hold Timet
Column Address Set-up Timet
Column Address Hold Timet
Column Address Hold Time from RASt
Column Address to RAS Lead Timet
Symbol
t
RC
HPC
RAC
CAC
AA
CPA
CLZ
DOH
t
CEZ
t
REZ
t
WEZ
T
REF
RP
RAS
RASP
RSH
CP
CAS
CSH
CRP
RHCP
RCD
RAD
RSCD
ASR
RAH
ASC
CAH
AR
RAL
(V
= 5 V ±10%, Ta = 0°C to 70°C) Note 1,2,3,10,11
CC
MSC2383257A
-60BS16/DS16
Min.
110
25
—
—
—
—
0
0
2
—
40
60
60
15
10
10
40
10
35
20
15
0
10
0
10
40
30
Max.
—
—
60
15
30
35
—
15
50
32
—
10k
100k
—
—
10k
—
—
—
45
30
—
—
—
—
—
—
MSC2383257A
-70BS16/DS16
Min.
130
30
—
—
—
—
0
0
2
—
50
70
70
20
10
10
45
10
40
20
15
0
10
0
15
45
35
Max.
—
—
70
20
35
40
—
20
50
32
—
10k
100k
—
—
10k
—
—
—
50
35
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns5—5—
ns
ns7, 8020015
ns7020015
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns70—60—
ns
ns
ns
ns
ns
ns
Note
4, 5, 6
4, 5
4, 6
4
4
7, 8
3
5
6
122
Page 7
¡ Semiconductor
MSC2383257A-xxBS16/DS16
AC Characteristics (2/2)
Parameter
Read Command Set-up Time
Read Command Hold Time
Read Command Hold Time referenced to RAS
Write Command Set-up Time
Write Command Hold Time
Write Command Hold Time from RAS
Write Command Pulse Width
Write Command Pulse Width (Output Disable)
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Set-up Time
Data-in Hold Time
Data-in Hold Time from RAS
CAS Active Delay Time from RAS Precharge
RAS to CAS Set-up Time (CAS before RAS)
RAS to CAS Hold Time (CAS before RAS)ns
WE to RAS Precharge Time (CAS before RAS)
WE Hold Time from RAS (CAS before RAS)
RAS to WE Set-up Time (Test Mode)
RAS to WE Hold Time (Test Mode)
Symbol
RCS
t
RCH
t
RRH
t
WCS
t
WCH
t
WCR
t
WP
t
WPE
t
RWL
t
CWL
t
DS
t
DH
t
DHR
t
RPC
t
CSR
t
CHR
t
WRP
t
WRH
t
WTS
t
WTH
(V
= 5 V ±10%, Ta = 0°C to 70°C) Note 1,2,3,10,11
CC
MSC2383257A
-60BS16/DS16
Min.
0
0
0
0
10
45
10
15
15
0
15
40
10
10
20
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MSC2383257A
-70BS16/DS16
Min.
0
0
0
0
15
50
10
20
20
0
15
45
10
10
20
Max.
—t
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns10—5—
ns
ns
ns
ns
ns
ns
ns
ns10—10—
ns10—10—
ns10—10—
ns20—20—
Note
1
9
9
123
Page 8
MSC2383257A-xxBS16/DS16¡ Semiconductor
Notes:1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume tT = 5 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the t
t
(Max.) is specified as a reference point only. If t
RCD
t
(Max.) limit, access time is controlled by t
RCD
6. Operation within the t
t
(Max.) is specified as a reference point only. If t
RAD
t
(Max.) limit, access time is controlled by tAA.
RAD
7. t
CEZ
(Max.), t
(Max.) and t
REZ
(Max.) limit ensures that t
RCD
(Max.) limit ensures that t
RAD
(Max.) define the time at which the output achieves
WEZ
CAC
(Max.) can be met.
RAC
is greater than the specified
RCD
.
(Max.) can be met.
RAC
is greater than the specified
RAD
the open circuit condition and are not referenced to output voltage levels.
8. t
9. t
CEZ
RCH
and t
or t
must be satisfied for open circuit condition.
REZ
must be satisfied for a read cycle.
RRH
10. The test mode is initiated by performing a WE and CAS before RAS refresh cycle.
This mode is latched and remains in effect until the exit cycle is generated.
The test mode specified in this data sheet is an 8-bit parallel test function. CA0, CA1
and CA10 are not used. In a read cycle, if all internal bits are equal, the DQ pin will
indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low
level. The test mode is cleared and the memory device returned to its normal
operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh
cycle.
The 4M ¥ 32 module can be tested as a 512K ¥ 32 module in this test mode.
124
11. In a test mode read cycle, the access time parameters are delayed by 5 ns. The test
mode parameters are obtained by adding 5 ns to the normal read cycle values.
See ADDENDUM I for AC Timing Waveforms
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