Datasheet MSC23436C-70DS10, MSC23436C-60BS10, MSC23436C-60DS10, MSC23436C-70BS10 Datasheet (OKI)

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Semiconductor
MSC23436C-xxBS10/DS10
4,194,304-wo rd x 36-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE
This vers i on: Apr. 7. 1999
DESCRIPTION
The MSC23436C-xxBS10/DS10 is a 4,194,304-word x 36-bit CMOS dynamic random access memory module which is composed of ei ght 16Mb(4Mx 4) DRAMs in SO J packages and two 8Mb(4Mx2) DRAMs in S OJ packages mounted with t en decoupl i ng capaci tor s. Thi s i s a 72-pin si ngle i n-l i ne m em ory m odul e. T hi s modul e supports any applicat ion where high density and l ar ge c apac ity of stor age memory ar e r equired.
FEATURES
· 4,194,304-word x 36- bit organization
· 72-pin Single In-Li ne M emory Module MSC23436C-xxBS10 : Gold tab MSC23436C-xxDS10 : Solder tab
· Singl e 5V power supply, ±10% tolerance
· Input : TTL compatibl e
· Output : TTL compatible, 3-state
· Refresh : 2048cycles/32ms
· /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability
· Fast page mode c apability
· Multi-bit t est mode capability
PRODUCT FAMILY
Access Time (Max. ) Power Dissipation (M ax.)
Family
t
RAC
t
AA
t
CAC
Cycle
Time
(Min.)
Operating Standby
MSC23436C-60BS10/DS10 60ns 30ns 15ns 110ns 5720mW MSC23436C-70BS10/DS10 70ns 35ns 20ns 130ns 5225mW
55mW
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Semiconductor MSC23436C
MODULE OUTLINE
1 72
R1.57
6.35
1.04Typ.
1.27±0.1
95.25
2.03Typ.
6.35Typ.
Typ.
6.35
Typ.
10.16
φ
3.18
25.4±0.2
101.19Typ.
107.95±0.2
*1
3.38Typ.
3.17Min.
5.28Max.
+0.1
-0.08
1.27
(Uni t : mm)
MSC23436C-xxBS10/DS10
*1 Tolerance over 14.5mm from bottom edge is ±0.5.
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Semiconductor MSC23436C
PIN C ONFIGURATION
Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name
1VSS19 A10 37DQ1755DQ12 2 DQ0 20 DQ4 38DQ3556DQ30 3 DQ1821DQ2239 VSS57 DQ13 4 DQ1 22 DQ5 40 /CAS0 58 DQ31 5 DQ1923DQ2341/CAS259 V
CC
6 DQ2 24 DQ6 42 /CAS3 60 DQ32 7 DQ2025DQ2443/CAS161DQ14 8 DQ3 26 DQ7 44 /RAS0 62 DQ33 9 DQ2127DQ2545 NC 63DQ15
10 V
CC
28 A7 46 NC 64 DQ 34 11 NC 29 NC 47 /WE 65 DQ16 12 A0 30 V
CC
48 NC 66 NC 13 A1 31 A8 49 DQ9 67 PD1 14 A2 32 A9 50 DQ27 68 PD2 15 A3 33 NC 51 DQ 10 69 PD3 16 A4 34 /RAS2 52 DQ28 70 PD4 17 A5 35 DQ26 53 DQ11 71 NC 18 A6 36 DQ8 54 DQ29 72 V
SS
Presence Detect Pins
Pin No. Pin Name -60 -70
67 PD1 V
SS
V
SS
68 PD2 NC NC 69 PD3 NC V
SS
70 PD4 NC NC
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Semiconductor MSC23436C
BLOCK DIAGRAM
/WE
/CAS0
/RAS0
A0-A10
/CAS1
DQ0
A0-A10DQDQDQDQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
DQ1
DQ2
DQ3
DQ8
A0-A10
DQ1
DQ2
/OE
V
CC
/RAS
/CAS1
/WE
V
SS
DQ17
/CAS2
V
CC
VSSC1-C10
A0-A10
DQ
DQ
DQDQ/OE
VCC/RAS
/CAS
/WE
V
SS
DQ4
DQ5
DQ6
DQ7
A0-A10DQDQDQDQ
/OE
V
CC
/RAS
/CAS
/WE
VSSDQ9
DQ10
DQ11
DQ12
A0-A10
DQ
DQ
DQDQ/OE
/RAS
/CAS
/WE
DQ13
DQ14
DQ15
DQ16
DQ18
A0-A10
DQ
DQDQDQ
/OE
/RAS
/CAS
/WE
DQ19
DQ20
DQ21
VCCVSSVCCV
SS
DQ22
A0-A10
DQ
DQ
DQDQ/OE
/RAS
/CAS
/WE
DQ23
DQ24
DQ25
VCCVSSDQ26
A0-A10
DQ1
DQ2
/OE
V
CC
/RAS
/CAS1
/WE
V
SS
DQ35
/CAS2
DQ27
A0-A10
DQ
DQDQDQ
/OE
/RAS
/CAS
/WE
DQ28
DQ29
DQ30
VCCV
SS
DQ31
A0-A10
DQ
DQ
DQDQ/OE
/RAS
/CAS
/WE
DQ32
DQ33
DQ34
VCCVSS/CAS2
/RAS2
/CAS3
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Semiconductor MSC23436C
ELECTRICAL CHARAC TERISTICS
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Voltage on Any Pin Relative to V
SS
VIN, V
OUT
-0.5 to 7.0 V
Voltage on VCC Supply Relative t o V
SS
V
CC
-0.5 to 7.0 V
Short Circuit Out put Current I
OS
50 mA Power Dissipation PD *10W Operating Temperature T
OPR
0 to 70 °C
Storage Temperature T
STG
-40 to 125 °C
* Ta = 25° C
Recommended Operating Conditions
( Ta = 0°C t o 70°C )
Parameter Symbol Min. Typ. Max. Unit
V
CC
4.5 5.0 5.5 V
Power Supply Voltage
V
SS
000V
Input High Voltage V
IH
2.4 - VCC + 0.5 V
Input Low Voltage V
IL
-0.5 - 0.8 V
Capacitance
( V
CC
= 5V ± 10% , Ta = 25° C, f = 1 MHz )
Parameter Symbol Typ. Max. Unit
Input Capacit ance (A0 - A10) C
IN1
-70pF
Input Capacit ance (/WE) C
IN2
-80pF
Input Capacitance (/ RAS0, /RAS2) C
IN3
-43pF
Input Capacitance (/ CAS0 - / CAS3) C
IN4
-28pF
I/O Capacitance (DQ0 - DQ35) C
I/O
-16pF
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Semiconductor MSC23436C
DC Characteristics
(V
CC
= 5V ± 10% , Ta = 0°C t o 70°C )
-60 -70
Parameter Symbol Condition
Min. Max. Min. Max.
Unit Note
Output High Voltage V
OH
IOH = -5.0mA 2.4 V
CC
2.4 V
CC
V
Output Low Voltage V
OL
IOL = 4.2mA 0 0. 4 0 0. 4 V
Input Leakage Current I
LI
0V ≤ VIN ≤ 6.5V; All other pins not under test = 0V
-100 100 -100 100
µ
A
Output Leakage Current I
LO
DQ disable 0V ≤ V
OUT
≤ V
CC
-10 10 -10 10
µ
A
Average Power Supply Current (Operating)
I
CC1
/RAS, /CAS cycling, t
RC
= Min.
- 1040 - 950 mA 1, 2
/RAS, /CAS = V
IH
-20-20mA
Power supply current (Standby)
I
CC2
/RAS, /CAS
V
CC
-0.2V
-10-10mA
1
Average Power Supply Current (/RAS only refresh)
I
CC3
/RAS cycling, /CAS = V
IH
,
t
RC
= Min.
- 1040 - 950 mA 1, 2
Average Power Supply Current (/CAS before /RAS refresh)
I
CC6
/RAS cycling, /CAS before /RAS
- 1040 - 950 mA 1, 2
Average Power Supply Current (Fast Page Mode)
I
CC7
/RAS = VIL, /CAS cycling, t
PC
= Min.
- 860 - 770 mA 1, 3
Notes: 1. ICC Max. is specified as ICC for output open conditi on.
2. The address can be changed once or less while /RAS = V
IL
.
3. The address can be changed once or less while /CAS = V
IH
.
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Semiconductor MSC23436C
AC Characteristics (1/2)
(V
CC
= 5V ± 10% , Ta = 0° C to 70°C ) Note: 1, 2, 3, 9, 10
-60 -70
Parameter Symbol
Min. Max. Min. Max.
Unit Note
Random Read or Write Cycle Time t
RC
110 - 130 - ns
Fast Page Mode Cycle Time t
PC
40 - 45 - ns
Access Time from /RAS t
RAC
- 60 - 70 ns 4, 5, 6
Access Time from /CAS t
CAC
- 15 - 20 ns 4, 5
Access Time from Column Address t
AA
- 30 - 35 ns 4, 6
Access Time from /CAS Precharge t
CPA
- 35 - 40 ns 4
Output Low Im pedance Time f rom / C AS t
CLZ
0-0-ns4
/CAS to Data Output Buffer Turn-off Delay Time t
OFF
0 15 0 20 ns 7
Transition Time t
T
3 50 3 50 ns 3
Refresh Period t
REF
-32-32ms
/RAS Precharge Time t
RP
40 - 50 - ns
/RAS Pulse Width t
RAS
60 10K 70 10K ns
/RAS Pulse Widt h (Fast Page M ode) t
RASP
60 100K 70 100K ns
/RAS Hold Time t
RSH
15 - 20 - ns
/CAS Precharge Time (Fast Page Mode) t
CP
10 - 10 - ns
/CAS Pulse Width t
CAS
15 10K 20 10K ns
/CAS Hold Time t
CSH
60 - 70 - ns
/CAS to /RAS Precharge Time t
CRP
10 - 10 - ns
/RAS Hold Time from /CAS Precharge t
RHCP
35 - 40 - ns
/RAS to /CAS Delay Time t
RCD
20 45 20 50 ns 5
/RAS to Column Address Delay Time t
RAD
15 30 15 35 ns 6
Row Address Set-up Time t
ASR
0-0-ns
Row Address Hold Time t
RAH
10 - 10 - ns
Column Address Set-up Time t
ASC
0-0-ns
Column Address Hold Time t
CAH
15 - 15 - ns
Column Address to /RAS Lead Time t
RAL
30 - 35 - ns
Read Command Set-up Time t
RCS
0-0-ns
Read Command Hold Time t
RCH
0-0-ns8
Read Command Hold Time referenced to /R AS t
RRH
0-0-ns8
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Semiconductor MSC23436C
AC Characteristics (2/2)
(V
CC
= 5V ± 10% , Ta = 0° C to 70°C ) Note: 1, 2, 3, 9, 10
-60 -70
Parameter Symbol
Min. Max. Min. Max.
Unit Note
Write Command Set-up Time t
WCS
0-0-ns
Write Command Hold Time t
WCH
10 - 15 - ns
Write Command Pulse W i dt h t
WP
10 - 10 - ns
Write Command to /RAS Lead Time t
RWL
15 - 20 - ns
Write Command to /CAS Lead Time t
CWL
15 - 20 - ns
Data-in Set-up Time t
DS
0-0-ns
Data-in Hold Time t
DH
15 - 15 - ns
/CAS Active Delay Time from /RAS Precharge t
RPC
10 - 10 - ns
/RAS to /CAS Set-up Time (/CAS before /RAS) t
CSR
10 - 10 - ns
/RAS to /CAS Hold Time (/CAS before /RAS) t
CHR
20 - 20 - ns
/WE to /RAS Precharge Time (/CAS before /RAS) t
WRP
10 - 10 - ns
/WE Hold Time from /RAS (/CAS before /RAS) t
WRH
10 - 10 - ns
/RAS to /WE Set-up Time (Test Mode) t
WTS
10 - 10 - ns
/RAS to /WE Hold Time (Test Mode) t
WTH
20 - 20 - ns
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Semiconductor MSC23436C
Notes: 1. A start-up delay of 200µs is required after power-up, fol lowed by a minimum of eight ini tializ at ion cycles
(/RAS only r efresh or /CAS before /RAS refresh) befor e pr oper devic e oper ation is achieved.
2. The AC characteristic s assume t
T
= 5ns.
3. V
IH
(Min.) and VIL(Max.) are refer enc e levels for measuring input timing signals. Transition times (tT) are
measured between V
IH
and VIL.
4. This parameter is m easured wit h a load circuit equivalent t o 2TTL loads and 100pF.
5. Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified t
RCD
(Max.) limit, then
the access tim e is controll ed by t
CAC
.
6. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RAD
(Max.) is specified as a reference point only. If t
RAD
is greater than the specified t
RAD
(Max.) limit, then
the access tim e is controll ed by t
AA
.
7. t
OFF
(Max.) defi ne the t i m e at which the out put achi eves the open circui t c ondit i on and is not ref erenc ed
to output voltage levels.
8. t
RCH
or t
RRH
must be satisfi ed for a read cycle.
9. The test mode is initiated by perf orming a /WE and /CAS before /RAS ref resh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 4-bit parallel test f unct ion. CA0 and CA1 are not used. I n a read cycle, if all i nt ernal bi ts are equal, the D Q p in w ill indica t e a hig h level. If a n y intern al bits are not equal, the DQ pin will indicate a low le vel. The test mode is cl eared and t he mem ory devic e retur ned to i ts norm al operati ng state by a / RAS onl y refresh or /CAS before /RAS refresh cycle.
10. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value. These parameters should be specifi ed in test m ode cycle by adding the abov e v alue t o the specif ied value in this data sheet.
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