Semiconductor MSC23432D
Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles
(/RAS only r efresh or /CAS before /RAS refresh) befor e pr oper devic e oper ation is achieved.
2. The AC characteristic s assumes t
T
= 5ns.
3. V
IH
(Min.) and VIL(Max.) are ref erence lev els f or m easuring input tim ing signals. Transiti on ti me (tT) are
measured between V
IH
and VIL.
4. This parameter is m easured wit h a load circuit equivalent t o 2TTL loads and 100pF.
5. Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified t
RCD
(Max.) limit, then
the access tim e is controll ed by t
CAC
.
6. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RAD
(Max.) is specified as a reference point only. If t
RAD
is greater than the specified t
RAD
(Max.) limit, then
the access tim e is controll ed by t
AA
.
7. t
OFF
(Max.) define the time at which the output achieves the open circuit condition and are not referenced
to output voltage levels.
8. t
RCH
or t
RRH
must be satisfi ed for a read cycle.
9. The test mode is initiated by perf orming a /WE and /CAS before /RAS ref resh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet
is an 8-bit parallel test function. CA0, CA1 and CA10 are not used. In a read cycle, if all int ernal bits are
equal, the DQ pin will indica te a h igh le vel. If an y in ter na l b its ar e n o t equal, the DQ pin will indicat e a low
level. The test mode is cleared and the memory devic e retur ned to its normal operating state by a /RAS
only refresh or /CAS before /RAS refresh cycle.
10. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value.
These parameters should be specifi ed in test m ode cycle by adding the abov e v alue t o the specif ied
value in this data sheet.