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查询MSC23432D供应商
This vers i on: Mar. 8. 1999
Semiconductor
MSC23432D-xxBS8/DS8
4,194,304-wo rd x 32-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE
DESCRIPTION
The MSC23432D-xx BS8/ DS8 i s a ful ly decoded, 4,194, 304-word x 32-bi t CMOS dy nam ic random acc ess mem ory
module com posed of ei ght 16M b DRAMs (4Mx 4) i n SO J pack ages mount ed with ei ght dec oupli ng capac it ors on a
72-pin glass epoxy single in-line package. This module supports any application where high density and large
capacity of storage memory are requi r ed.
FEATURES
· 4,194,304-word x 32- bit organization
· 72-pin Single In-Li ne M emory Module
MSC23432D-xxBS8 : Gold tab
MSC23432D-xxDS8 : Solder tab
· Singl e +5V supply ± 10% tolerance
· Input : TTL compatibl e
· Output : TTL compatible, 3-state
· Refresh : 2048cycles/32ms
· /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability
· Fast page mode c apability
· Multi-bit t est mode capability
PRODUCT FAMILY
Family
MSC23432D-60BS8/DS8 60ns 30ns 15ns 110ns 4840mW
MSC23432D-70BS8/DS8 70ns 35ns 20ns 130ns 4400mW
Access Time (Max. ) Power Dissipation
t
RAC
t
AA
t
CAC
Cycle
Time
(Min.)
Operating (Max.) Standby (Max.)
44mW
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Semiconductor MSC23432D
1
72
R1.57
6.35
1.04Typ.
1.27±0.1
95.25
2.03Typ.
6.35Typ.
Typ.
Typ.
25.4±0.2
101.19Typ.
107.95±0.2
3.38Typ.
3.17Min.
5.28Max.
+0.1
-0.08
1.27
(Unit : mm )
MSC23432D-xxBS8/DS8
*1 The common size difference of the board width 12.5mm of its height is specified as ±0.2.
MODULE OUTLINE
3.18
φ
6.35
10.16
The value above 12.5mm is specified as ±0.5.
*1
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Semiconductor MSC23432D
PIN C ONFIGURATION
Pin No. Pin Name Pin No. Pin Nam e Pin No. Pin Nam e Pin No. Pin Nam e
1VSS19 A10 37 NC 55 DQ11
2 DQ0 20 DQ4 38 NC 56 DQ27
3 DQ16 21 DQ20 39 V
SS
57 DQ12
4 DQ1 22 DQ5 40 /CAS0 58 DQ28
5 DQ17 23 DQ21 41 /CAS2 59 V
CC
6 DQ2 24 DQ6 42 /CAS3 60 DQ29
7 DQ18 25 DQ22 43 /CAS1 61 DQ13
8 DQ3 26 DQ7 44 /RAS0 62 DQ30
9 DQ19 27 DQ23 45 NC 63 DQ14
10 V
CC
28 A7 46 NC 64 DQ31
11 NC 29 NC 47 /WE 65 DQ 1 5
12 A0 30 V
CC
48 NC 66 NC
13 A1 31 A8 49 DQ8 67 PD1
14 A2 32 A9 50 DQ24 68 PD2
15 A3 33 NC 51 DQ9 69 PD3
16 A4 34 /RAS2 52 DQ25 70 PD4
17 A5 35 NC 53 DQ10 71 NC
18 A6 36 NC 54 DQ26 72 V
SS
Presence Detect Pins
Pin No. Pin Name
67 PD1 V
68 PD2 NC NC
69 PD3 NC V
70 PD4 NC NC
MSC23432D
-60BS8/DS8
SS
MSC23432D
-70BS8/DS8
V
SS
SS
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Semiconductor MSC23432D
/WE
/CAS0
/RAS0
A0-A10
/CAS1
DQ0
A0-A10
DQ
DQDQDQ
/OE
V
/RAS
/CAS
/WE
V
DQ1
DQ2
DQ3
V
VSSC1-C8
A0-A10
DQ
DQ
DQDQ/OE
VCC/RAS
/CAS
/WE
V
DQ4
DQ5
DQ6
DQ7
A0-A10
DQDQDQDQ/OE
V
/RAS
/CAS
/WE
V
DQ8
DQ9
DQ10
DQ11
A0-A10
DQ
DQDQDQ
/OE
/RAS
/CAS
/WE
DQ12
DQ13
DQ14
DQ15
DQ16
A0-A10
DQ
DQDQDQ
/OE
/RAS
/CAS
/WE
DQ17
DQ18
DQ19
VCCVSSVCCV
DQ20
A0-A10
DQ
DQ
DQDQ/OE
/RAS
/CAS
/WE
DQ21
DQ22
DQ23
VCCVSSDQ24
A0-A10
DQDQDQDQ/OE
/RAS
/CAS
/WE
DQ25
DQ26
DQ27
VCCV
DQ28
A0-A10
DQ
DQDQDQ
/OE
/RAS
/CAS
/WE
DQ29
DQ30
DQ31
VCCVSS/CAS2
/RAS2
/CAS3
BLOCK DIAGRAM
CC
SS
SS
CC
SS
SS
CC
SS
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Semiconductor MSC23432D
ELECTRICAL CHARAC TERISTICS
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Voltage on Any Pin Relative to V
Voltage on VCC Supply Relative to V
SS
SS
Short Circuit Output Curr ent I
VIN, V
V
OS
CC
OUT
-0.5 to +7.0 V
-0.5 to +7.0 V
50 mA
Power Dissipation PD *8W
Operating Temperature T
Storage Temperature T
OPR
STG
0 to +70 °C
-40 to +125 °C
* Ta = 25°C
Recommended Operating Conditions
( Ta = 0°C to +70°C )
Paramete r Symbol Min. Typ. Max. Unit
Power Supply Voltage
Input High Voltage V
Input Low Voltage V
V
CC
V
SS
IH
IL
4.5 5.0 5.5 V
000V
2.4 - VCC + 0.5 V
-0.5 - 0.8 V
Capacitance
Paramete r Symbol Typ. Max. Uni t
Input Capacitance (A0 - A10) C
Input Capacitance (/WE) C
Input Capacitance (/RAS0, /RAS2) C
Input Capacitance (/CAS0- /CAS3) C
I/O Capacitance (DQ0 - DQ31) C
( VCC = 5V ± 10%, Ta = 25°C, f = 1 MHz )
IN1
IN2
IN3
IN4
DQ
-57pF
-65pF
-35pF
-20pF
-16pF
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Semiconductor MSC23432D
DC CHARACTERISTICS
(VCC = 5V ± 10%, Ta = 0°C to +70°C )
Paramete r Symbol Conditi on
Input Leakage Current I
Output Leakage Current I
Output High Voltage V
Output Low Voltage V
Average Power
Supply Current
(Operating)
Power supply current
(Standby)
Average Power
Supply Current
(/RAS only refresh)
I
I
I
LO
CC1
CC2
CC3
LI
OH
OL
MSC23432D
-60BS8/DS8
MSC23432D
-70BS8/DS8
Unit Note
Min. Max. Min. Max.
0V ≤ VIN ≤ 6.5V;
All other pins not
-80 80 -80 80 µA
under test = 0V
DQ disable
OUT
≤ 5.5V
0V ≤ V
IOH = -5.0mA 2.4 V
-10 10 -10 10 µA
CC
2.4 V
CC
IOL = 4.2mA 0 0.4 0 0.4 V
/RAS, /CAS cy cling,
= Min.
t
RC
/RAS, /CAS = V
IH
/RAS, /CAS
-0.2V
≥ V
CC
- 880 - 800 mA 1, 2
-16-16mA1
-8-8mA1
/RAS cycling,
/CAS = V
= Min.
t
RC
,
IH
- 880 - 800 mA 1, 2
V
Average Power
Supply Current
(/CAS before /RAS refresh)
Average Power
Supply Current
(Fast Page Mode)
I
I
CC6
CC7
/RAS cycling,
/CAS before /RAS
/RAS = VIL,
/CAS cycling,
= Min.
t
PC
Notes: 1. ICC Max. is specified as ICC for output open conditi on.
2. Address can be changed once or less while /RA S = V
3. Address can be changed once or less while /CA S = V
- 880 - 800 mA 1, 2
- 720 - 640 mA 1, 3
.
IL
.
IH
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Semiconductor MSC23432D
AC CHARACTERISTICS (1/ 2)
Paramete r Symbol
(VCC = 5V ± 10%, Ta = 0°C to +70°C ) Note: 1, 2, 3, 9, 10
MSC23432D
-60BS8/DS8
MSC23432D
-70BS8/DS8
Unit Note
Min. Max. Min. Max.
Random Read or Writ e Cycle Time t
Fast Page Mode Cycle Time t
Access Time from /RAS t
Access Time from /CAS t
Access Time from Column Address t
Access Time from /CAS Precharge t
Output Low Impedance Time from /CAS t
/CAS to Data Output Buffer Turn-off Delay Time t
Transition Time t
Refresh Period t
/RAS Precharge Tim e t
/RAS Pulse Width t
/RAS Pulse Width ( Fast Page Mode) t
/RAS Hold Time t
/CAS Precharge Time (Fast Page Mode) t
/CAS Pulse Width t
/CAS Hold Time t
RC
PC
RAC
CAC
AA
CPA
CLZ
OFF
T
REF
RP
RAS
RASP
RSH
CP
CAS
CSH
110 - 130 - ns
40 - 45 - ns
- 60 - 70 ns 4, 5, 6
- 15 - 20 ns 4, 5
- 30 - 35 ns 4, 6
- 35 - 40 ns 4
0-0-ns4
0 15 0 20 ns 7
3 50 3 50 ns 3
-32-32ms
40 - 50 - ns
60 10K 70 10K ns
60 100K 70 100K ns
15 - 20 - ns
10 - 10 - ns
15 10K 20 10K ns
60 - 70 - ns
/CAS to /RAS Pr echarge Time t
/RAS Hold Time from /CAS Precharge t
/RAS to /CAS Delay Time t
/RAS to Column Address Delay Time t
Row Address Set-up Time t
Row Address Hol d Time t
Column Address Set-up Time t
Column Address Hol d Time t
Column Address to /RAS Lead Time t
Read Command Set-up Time t
Read Command Hold Time t
Read Command Hold Time referenced to /RAS t
CRP
RHCP
RCD
RAD
ASR
RAH
ASC
CAH
RAL
RCS
RCH
RRH
5-5-ns
35 - 40 - ns
20 45 20 50 ns 5
15 30 15 35 ns 6
0-0-ns
10 - 10 - ns
0-0-ns
15 - 15 - ns
30 - 35 - ns
0-0-ns
0-0-ns8
0-0-ns8
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Semiconductor MSC23432D
AC Characteristics (2/2)
Paramete r Symbol
(VCC = 5V ± 10%, Ta = 0°C to +70°C ) Note: 1, 2, 3, 9, 10
MSC23432D
-60BS8/DS8
MSC23432D
-70BS8/DS8
Unit Note
Min. Max. Min. Max.
Writ e Command Set-up Time t
Writ e Command Hold Time t
Writ e Command Pulse Wi dth t
Writ e Command to /RAS Lead Time t
Writ e Command to /CAS Lead Time t
Data-in Set-up Time t
Data-i n Ho ld Time t
/CAS Active Delay Time from /RAS Precharge t
/RAS to /CAS Set-up Time
(/CAS before /RAS)
/RAS to /CAS Hold Time
(/CAS before /RAS)
/WE to /RAS Precharge Time
(/CAS before /RAS)
/WE Hold Time from /RAS
(/CAS before /RAS)
/RAS to /WE Set-up Time
(Test Mode)
WCS
WCH
WP
RWL
CWL
RPC
t
CSR
t
CHR
t
WRP
t
WRH
t
WTS
DS
DH
0-0-ns
10 - 15 - ns
10 - 10 - ns
15 - 20 - ns
15 - 20 - ns
0-0-ns
10 - 15 - ns
5-5-ns
10 - 10 - ns
10 - 10 - ns
10 - 10 - ns
10 - 10 - ns
10 - 10 - ns
/RAS to /WE Hold Time
(Test Mode)
t
WTH
10 - 10 - ns
Page 9
Semiconductor MSC23432D
Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles
(/RAS only r efresh or /CAS before /RAS refresh) befor e pr oper devic e oper ation is achieved.
2. The AC characteristic s assumes t
3. V
(Min.) and VIL(Max.) are ref erence lev els f or m easuring input tim ing signals. Transiti on ti me (tT) are
IH
measured between V
and VIL.
IH
= 5ns.
T
4. This parameter is m easured wit h a load circuit equivalent t o 2TTL loads and 100pF.
5. Operation within the t
(Max.) is specified as a reference point only. If t
t
RCD
RCD
the access tim e is controll ed by t
6. Operation within the t
(Max.) is specified as a reference point only. If t
t
RAD
RAD
the access tim e is controll ed by t
7. t
(Max.) define the time at which the output achieves the open circuit condition and are not referenced
OFF
(Max.) limit ensures that t
.
CAC
(Max.) limit ensures that t
.
AA
(Max.) can be met.
RAC
is greater than the specified t
RCD
(Max.) can be met.
RAC
is greater than the specified t
RAD
(Max.) limit, then
RCD
(Max.) limit, then
RAD
to output voltage levels.
8. t
RCH
or t
must be satisfi ed for a read cycle.
RRH
9. The test mode is initiated by perf orming a /WE and /CAS before /RAS ref resh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet
is an 8-bit parallel test function. CA0, CA1 and CA10 are not used. In a read cycle, if all int ernal bits are
equal, the DQ pin will indica te a h igh le vel. If an y in ter na l b its ar e n o t equal, the DQ pin will indicat e a low
level. The test mode is cleared and the memory devic e retur ned to its normal operating state by a /RAS
only refresh or /CAS before /RAS refresh cycle.
10. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value.
These parameters should be specifi ed in test m ode cycle by adding the abov e v alue t o the specif ied
value in this data sheet.
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