Datasheet MS8870 Datasheet (MOSA)

MOSA ELECTRONICS

Features

•

Complete DTMF receiver

•

Low power consumption

• Adjustable guard time

• Central Office Quality

• CMOS, Single 5V operation

O

MS8870
DTMF Receiver

rdering Information

MS8870 : 18 PIN DIP PACKAGE

Description

The MS8870 is a complete DTMF receiver integrating
both the bandsplit filter and digital decoder functions,
fabricated in double poly technology and is pin and
function compatible with MITEL8870. The filter section
uses switched capacitor techniques for high and low group

filters; the decoder uses digital counting techniques to
detect and decode all 16 DTMF tone-pairs into a 4-bit code.
External component count is minimized by on chip
provision of a differential input amplifier, clock oscillator
and latched 3-state bus interface.

Figure 1. Functional Block Diagram

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MOSA ELECTRONICS

MS8870
DTMF Receiver

Pin Description

Pin # Name Description

1 IN + Non-inverting op-amp input.
2 IN - Inverting op-amp input.
3 GS Gain select. Gives access to output of front end differential amplifier for connection

4 V

5 IC Internal connection. Must be tied to Vss.
6 IC Internal connection. Must be tied to Vss.
7 OSC1 Clock input.
8 OSC2 Clock output. A 3.5795 MHz crystal connected between OSC1 and OSC2 completes

9 Vss Negative power supply input.

10 TOE 3-state output enable (input). Logic high enables the outputs Q1-Q4 Internal pull up.

11-14 Q1-Q4 3-state data output. When enable by TOE, provide the code corresponding to the last

15 StD Delayed steering output. Presents a logic high when a received tone-pair has been

16 ESt Early steering output. Presents a logic high once the digital algorithm has detected a

17 St/GT

18 VDD Positive power supply input.

of feedback resistor.

REF

Reference vo ltage outp ut , nomi nall y VDD /2 is used to bias inputs at mid-rail (see Fig.

2).

the internal oscillator circuit.

valid tone-pair received (see Fig. 5).

registered and the output latch updated; return to logic low when the voltage on St/GT

TS

falls below V

valid tone pair (signal condition). Any momentar y loss of signal condition will cau se
ESt to return to a logic low.
Steering input/guard time output (bi-directional). A voltage greater than V
at St causes the device to register the detected tone pair and update the output latch. A
Voltage less than V
to reset the external steering time-constant; its state is a function of ESt and the
voltage on St.

.

t

TS

frees the device to accept a new tone pair. The GT output acts

t

TS

detected

t

Absolute Maximum Ratings

1 Power supply voltage VDD-Vss 6 V
2 Voltage on any pin Vss - 0.3 VDD + 0.3 V
3 Current at any pin 10 mA
4 Operating temperature -40 +85

5 Storage temperature -65 +150
6 Package power dissipation 1000 mW

Parameter Min Max Units

℃
℃

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MS8870

MOSA ELECTRONICS

DTMF Receiver

DC Electrical Characteristics

1 S Operating supply voltage 4.75 5.0 5.25 V

U

2 P Operating supply current IDD 3.0 9.0 mA

P

3 L Power consumption PO 15 45 mW f = 3.58 MHz; VDD= 5V

Y

4 I High level input VIH 3.5 V
5 N Low level input voltage VIL 1.5 V
6 P Input leakage current IIH/IIL 0.1 µA VIN = Vss or VDD
7 U Pull up (source) current ISO 7.5 µA T OE (pin 10) = 0 V
8 T Input impedance (IN+, IN-) RIN 10 MΩ @ 1 KHz
9 S Steering threshold voltage

10 O Low level output voltage VOL 0.03 V No load

11 U Hi gh level output voltage VOH 4.97 V No load

12 T Output low (sink) current IOL 1 2.5 mA V

13 P

14 U

15 T

Output high (
V
V

S

Characteristics Sym Min Typ Max Units Test Conditions

2.2 2.5 V

TS

V

t

OUT

= 0.4V

source

) current

R

output voltage V

ef

R

output resistance

ef

OH

I

0.4 0.8 mA V

2.4 2.8 V No load

R

ef

OR

10 KΩ

R

OUT

= 4.6V

Operating Characteristics
Gain Setting Amplifier

Characteristics Sym Min Typ Max Units Test Conditions

Input leakage current IIN 100 nA Vss ≤ VIN ≤ VDD
Input resistance RIN 10 MΩ
Input offset voltage Vos 25 mV
Power supply rejection PSRR 60 dB 1 KHz
Common mode rejection CMRR 60 dB -3.0V ≤ VIN ≤ 3.0V
DC open loop voltage gain A
Open loop unity gain bandwidth fc 1.5 MHz
Output voltage swing Vo 4.5 Vpp RL ≥ 100KΩ to Vss
Maximum capacitive load (GS) CL 100 pF
Maximum resistive load (GS) RL 50 KΩ
Common mode range VCM 3.0 Vpp No Load

Notes : 1. All voltages referenced to Vss unless otherwise noted.

2. Vcc = 5.0V, Vss = 0V, T

VOL

65 dB

A

= 25 ℃

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MOSA ELECTRONICS

MS8870
DTMF Receiver

AC Electrical Characteristics *

S -29 dBm 1,2,3,5,6,9

I Valid input signal levels 27.5 mV
G (each tone of composite signal) +1 dBm 1,2,3,5,6,9
N 883 mV
A Positive twist accept 10 dB 2,3,6,9

L Negative twist accept 10 dB 2,3,6,9

Freq. deviation accept

C Freq. deviation reject
O Third tone tolerance -16 dB 2,3,4,5,9,10
N Noise tolerance -12 dB 2,3,4,5,7,9,10

D. Dial tone tolerance +22 dB 2,3,4,5,8,9,11

T Tone present detect time tDP 5 11 14 ms Refer to Fig. 3

I Tone absent detect time tDA 0.5 4 8.5 ms Refer to Fig. 3

M Tone duration accept t

I Tone duration reject /t
N Interdigit pause accept tID 40 ms User adjustable
G Interdigit pause reject tDO 20 ms User adjustable
O Propagation delay (St to Q) tPQ 8 11 µs TOE = VDD
U Propagation delay (St to StD) t

T Output data set up ( Q to StD) t
P Pr opagation delay (TOE to Q t

U ENABLE) CL = 50 pF

T Propagation delay (TOE to Q t
S DISABLE) CL = 50 pF

C Crystal / clock frequency fc 3.5759 3.5795 3.5831 MHz
L Clock input rise time t

O Clock input fall time t

C Clock input duty cycle DCDL 40 50 60 % Ext. clock

K Capacitive load (OSC2) CLO 30 pF

* All voltages referenced to Vss unless otherwise noted. Vcc = 5.0V, Vss = 0V, TA = 25℃, Fc = 3.579545 MHz, using

test circuit shown in Figure 2

Characteristics Sym Min Typ Max Units Notes

RMS

1,2,3,5,6,9

RMS

1,2,3,5,6,9

±

1.5%±2Hz Nom. 2,3,5,9

±

3.5% Nom. 2,3,5,9

REC

40 ms User adjustable

REC

20 ms User adjustable

PStD

12 µs TOE = VDD

QStD

3.4 µs TOE = VDD

PTE

50 ns RL = 10KΩ

PTD

300 ns RL = 10KΩ

LHCL

110 ns Ext. clock

HLCL

110 ns Ext. clock

NOTES

1. dBm = decibels above or below a reference power of 1 mW into a 600 ohm load.

2. Digit sequence consists of all 16 DTMF to nes.

3. Tone duration = 40 ms, tone pause = 40 ms.

4. Signal condition consists of nominal DTMF frequencies.

5. Bo th tones in composite signal have an equal amplitude.

6. Tone pair is deviated by ± 1.5% ± 2 Hz.

7. Bandwidth limited (3 KHz) Gaussian noise.

8. The precise dial tone frequencies are ( 350 Hz and 440 Hz) ± 2%.

9. For an error rate of better than 1 in 10,000.

10. Referenced to lowest level frequency component in DTMF signal.

11. Referenced to the minimum valid accept level.

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MOSA ELECTRONICS

Figure 2. Single Ended Input Configuration

MS8870
DTMF Receiver

NOTES :

R1, R2 = 100K 1%
R3 = 300K 1%
C1, C2 = 100nF 5%
X1 = 3.579545 MHz

Figure 3. Timing Diagram

EXPLANATION OF EVENTS

A ) Short tone bursts: detected . Tone duration is invalid.
B ) Tone #n is detected. T one duration is valid. Decoded to outputs.
C ) End of Tone #n is detected and validated.
D ) 3-State outputs disable ( high impedance).
E ) Tone #n + 1 is detected. Tone duration is valid. Decoded to outputs.
F ) Tristate outputs are enabled. Acceptable drop out of Tone #n + 1 does not register at outputs.
G ) End of Tone #n + 1 is detected and validated.

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MOSA ELECTRONICS

MS8870
DTMF Receiver

Functional Description

The MS8870 monolithic DTMF receiver offers small
size, low power consumption and high performance. Its
architecture consists of a bandsplit filter section, which
separates the high and low group tones, followed by digital
counting sec tion which ver ifie s the fre quenc y and dur ation
of the received tones before passing the corresponding
code to the output bus.

Filter Section

Separation of the low-group and high-group tones is
achieved by applying the DTMF signal to the inputs of two
filters － a sixth order for the high group and an eighth
order for the low group. The bandwidths of which
correspond to the low and high group frequencies. The
filter section also incorporates notches at 350 and 440 Hz
for exceptional dial tone rejection (see Fig. 4). Each filter
output is followed by a single order switched capacitor
filter section which smoothes the signals prio r to limiting.
Limiting is performed by high-gain comparators which are
provided with hysteresis to prevent detection of unwanted
low-level signals. The outputs of the comparators provide
full rail logic swings at the frequencies of the incoming
DTMF signals.

Decoder Section

F

LOW FHIGH

697 1209 1 H 0 0 0 1
697 1336 2 H 0 0 1 0
697 1477 3 H 0 0 1 1
770 1209 4 H 0 1 0 0
770 1336 5 H 0 1 0 1
770 1477 6 H 0 1 1 0

NO TOE Q4 Q3 Q2 Q1

Figure 4. 6TH Order Bandpass

The decoder uses digital counting techniques to
determine the frequencies of limited tones and to verify
that they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals, such as voice, while
providing tolerance to small frequency deviations and
variations. This averaging algorithm has been developed to
ensure an optimum combination of immunity to "talk-off"
and tolerance to the presence of interfering signals ("third
tones") and noise. When the detector recognizes the
simultaneous presence of two valid tone (referred to as
"signal condition" in some industry specifications), it
raises the "early steering" flag (ESt). Any subsequent loss
of signal-condition will cause ESt to fall.

852 1209 7 H 0 1 1 1
852 1336 8 H 1 0 0 0
852 1477 9 H 1 0 0 1
941 1336 0 H 1 0 1 0
941 1209 * H 1 0 1 1
941 1477 # H 1 1 0 0
697 1633 A H 1 1 0 1
770 1633 B H 1 1 1 0

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MOSA ELECTRONICS

852 1633 C H 1 1 1 1
941 1633 D H 0 0 0 0

ANY L Z Z Z Z

L = LOGIC LOW, H = LOGIC HIGH, Z = HIGH IMPEDANCE

Figure 5. Functional Decode Table

shown in Fig. 6 is applicable. Component values are
chosen according to the formula : t

The value of t

REC

t

is the minimum signal duration to be recognized by
the receiver. A value for C of 0.1
for most applications, leaving R to be selected by the
designer.

MS8870
DTMF Receiver

REC

= tPD + t

ID

= tDA + t

t

DP

is a device parameter (see table) and

GTA

µ

F is recommended

GPT

Figure 6. Basic St eering Circuit

Steering Circuit

Before registration of a decoded tone pair, the receiver
checks for a valid signal duration (referred to as character
recognition condition). This check is performed by an
external RC time constant driven by ESt. A logic high on
ESt causes Vc (see Fig. 6) to rise as the capacitor
discharges.

Provided signal condition is maintained (ESt remains
high) for the validation period (t

TSt

threshold (V

) of the steering logic to register the tone

GTP

), Vc reaches the

pair, latching its corresponding 4-bit code (see Fig. 5) into
the output latch. At this point the GT output is activated
and drives Vc to VDD. GT continues to drive high as long
as ESt remains high. Finally, after a short dela y to allow
the output latch to settle, the delayed steering output flag
(StD) goes high, signaling that a received tone pair has
been registered. The contents of the output latch are made
available on the 4-bit output bus by raising the three state
control input (TOE) to a logic high. The steering circuit
works in reverse to validate the interdigit pause between
signals. Thus, as well as rejecting signals too short to be
considered valid, the receiver will tolerate signal
interruptions (drop out) too short to be considered a valid
pause. This facility, together with the capability of
selecting the steering time constants externally, allows the
designer to tailor performance to meet a wide variety of
system requirements.

Figure 7. Guard Time Adjustment

Different steering arrangements may be used to select
independently the guard times for tone present (t
tone absent (t

GTA

). This may be necessary to meet system

GTP

specifications which place both accept and reject limits on
both tone duration and interdigital pause. Guard time
adjustment also allows the designer to tailor system
parameters such as talk off and noise immunity. Increasing
t

REC

improves talk-off performance since it reduces the
probability that tones simulated by speech will maintain
signal condition long enough to be registered.
Alternatively, a relatively short tREC with noisy
environments where fast acquisition time and immunity to
tone drop-outs are required. Design information for guard
time adjustment is shown in Figure 7.

Differential Input Configuration

) and

Guard Time Adjustment

In many situations not requiring selection of tone

duration and interdigital pause, the simple steering circuit

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MOSA ELECTRONICS

The input arrangement of the MS8870 provides a
differential-input operational amplifier as well as a bias

Ref

) which is used to bias the inputs at mid-rail.

biasing the input at ½VDD. Fig. 8 shows the

DIFFERENTIAL INPUT AMPUT AMPLIFIER

C1 = C2 = 10nF

Ω

R2 x R5

R3 =

R2 + R5

VOLTAGE GAIN (Av diff) =

INPUT IMPEDENCE

= 2

INDIFF

( Z

)

All resistors are +/- 1% tolerenceR1 = R4 = R5 = 100 K

Ω

All capacitors are +/- 5% tolerenceR2 = 60 K , R3 = 37.5K

Ω

R5
R1

2

1

2

+

R

ω

1

C

Figure 8. Differential Input Configuration

source (V
Provision is made for connection of a feedback resistor to
the op-amp output (GS) for adjustment of gain. In a single­ended configuration, the input pins are connected as shown
in Fig. 2 with the op-amp connected for unity gain and
V

Ref

differential configuration, which permits the adjustment of
gain with the feedback resistor R

MS8870
DTMF Receiver

5

.

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