Page 1
SEMICONDUCTOR TECHNICAL DATA
The MRFIC Line
Order this document
by MRFIC1818/D
Designed specifically for application in Pan European digital 1.0 watt DCS1800
handheld radios, the MRFIC1818 is specified for 33 dBm output power with power
gain over 30 dB from a 4.8 volt supply . With minor tuning changes, the MRFIC1818
can be used for PCS1900 as well as PCS CDMA. To achieve this superior
performance, Motorola’s planar GaAs MESFET process is employed. The device
is packaged in the PFP–16 Power Flat Package which gives excellent thermal
and electrical performance through a solderable backside contact while allowing
the convenience and cost benefits of reflow soldering.
• Minimum Output Power Capabilities
33 dBm @ 4.8 Volts
32 dBm @ 4.0 Volts
• Specified 4.8 Volt Characteristics
RF Input Power = 3.0 dBm
RF Output Power = 33 dBm
Minimum PAE = 35%
• Low Current required from Negative Supply – 2 mA max
• Guaranteed Stability and Ruggedness
• Order MRFIC1818R2 for Tape and Reel.
R2 Suffix = 1,500 Units per 16 mm, 13 inch Reel.
• Device Marking = M1818
ABSOLUTE MAXIMUM RATINGS
DC Positive Supply Voltage V
DC Negative Supply Voltage V
RF Input Power P
RF Output Power P
Operating Case Temperature Range T
Storage Temperature Range T
Thermal Resistance, Junction to Case R
(TA = 25°C, ZO = 50 Ω, unless otherwise noted)
Rating
Symbol Value Unit
D1, 2, 3
stg
θJC
SS
in
out
C
1700–1900 MHz MMIC
DCS1800/PCS1900
INTEGRATED POWER AMPLIFIER
GaAs MONOLITHIC
INTEGRATED CIRCUIT
CASE 978–02
(PFP–16)
7.5 Vdc
–5 Vdc
10 dBm
36 dBm
–35 to +85 °C
–55 to +150 °C
10 °C/W
REV 2
Motorola, Inc. 1997
GND
V
D2
V
D2
V
D1
N/C
GND
RF IN
N/C
9
10
11
12
13
14
15
16
8
7
6
5
4
3
2
1
Pin Connections and Functional Block Diagram
V
G
V
D3
RF OUT
RF OUT
RF OUT
RF OUT
N/C
GND
MRFIC1818MOTOROLA RF DEVICE DATA
1
Page 2
RECOMMENDED OPERATING RANGES
Parameter Symbol Value Unit
Supply Voltage V
Gate Voltage V
RF Frequency Range f
RF Input Power P
D1, 2, 3
SS
RF
RF
2.7 to 6 Vdc
–3.5 to –4.5 Vdc
1700 to 1900 MHz
0 to 6 dBm
ELECTRICAL CHARACTERISTICS (V
= 4.8 V, VSS = –4 V, Pin = 3 dBm, Peak Measurement at 12.5% Duty Cycle, 4.6 ms
D1, 2, 3
Period, TA = 25°C unless otherwise noted. Measured in Reference Circuit Shown in Figure 1.)
Characteristic
Min Typ Max Unit
Frequency Range 1710 — 1785 MHz
Output Power 33 34.5 — dBm
Power Added Efficiency 35 42 — %
Output Power (Tuned for PCS Band, 1850 to 1910 MHz) — 34.5 — dBm
Power Added Efficiency (Tuned for PCS Band, 1850 to 1910 MHz) — 42 — %
Input VSWR — 2:1 — VSWR
Harmonic Output (2nd and 3rd) — –35 –30 dBc
Output Power at Low voltage (VD1, VD2, VD3= 4.0 V) 32 33 — dBm
Output Power, Isolation (VD1, VD2, VD3 = 0 V) — –40 –35 dBm
Noise Power (In 100 kHz, 1805 to 1880 MHz) — –85 –80 dBm
Stability – Spurious Output (Pin = 5 dBm, P
VSWR = 6:1 at any Phase Angle, Source VSWR = 3:1, at any Phase Angle)
Load Mismatch stress (P
any Phase Angle)
= 33 dBm, Load VSWR = 10:1 at
out
(1)
= 0 to 33 dBm, Load
out
(1)
— — –60 dBc
No Degradation in Output Power after Returning to
Standard Conditions
3 dB VDD Bandwidth — 2 — MHz
Negative Supply Current — 0.7 2 mA
(1) Adjust V
(0 to 4.8 V) for specified P
D1, 2, 3
; Duty Cycle = 12.5%, Period = 4.6 ms.
out
V
V
D2
D1
C9 C8
C7 C6
RF IN
L2
C1 6.8 nF
C2, C6, C8 22 pF, NPO/COG
C3, C7, C9 47 nF
C4 27 pF , NPO/COG
T2
NC
NC
9
10
11
12
13
14
15
16
T4
T3
C5 3.9 pF, NPO/COG
L1 18 nH, Coilcraft
L2 1.8 nH, Toko 2012
R1, R2 = 2.7 KΩ
8
7
6
5
4
3
2
1
C10
C10 0.5 pF
NOTE: For PCS/DCS1900 applications, the following components are used.
C5 = 2.7 pF, 0603 NPO/COG
L2 = 1.5 nH, Toko 2012
T3 = 1 mm 50 Ω Microstrip Line
Figure 1. Reference Circuit Configuration
V
L1
D3
R1
V
SS
R2
C1
C3C2
T1
C4
RF OUT
NC
C5
T1 1.4 mm 25 Ω Microstrip Line
T2 5 mm 50 Ω Microstrip Line
T3 4 mm 50 Ω Microstrip Line
T4 0.5 mm 50 Ω Microstrip Line
Board Material: Glass/Epoxy,
Thickness = 0.5 mm
ε
= 4.45,
r
MRFIC1818
2
MOTOROLA RF DEVICE DATA
Page 3
0 V
0 V
C13
CR1
C15
C14
3.0 V
3.0 V
1
2
3
4
5
6
7
VRAMP
U2
V
reg
IDLE
R4
RF IN
D
5
6
7
8
R3
V
BAT
C18
14
13
C16
12
C17
11
10
9
8
C12
C19
C10
C9
L2
T2
T4
T3
R5
NC
NC
C11
9
10
11
12
13
14
15
16
IN
G
4
D
S
3
D
S
2
D
1
Q1
–4.0 V
R2R1
VG TUNE
8
L1
7
6
5
4
3
2
1
T1
NC
C1
C3C2
C4
RF
OUT
C6
C1 6.8 nF
C2, C9, C10 22 pF, 0603 NPO/COG
C3, C11 47 nF
C4 27 pF, 0603 NPO/COG
C14, C15 1 µF
C18 1 µF
CR1 MMBD701L T1
L1 18 nH, Coilcraft or 20 mm
C6 3.9 pF, 0603 NPO/COG
C12 220 nF
L2 1.8 nH, Toko 2012
C13, C16, C17, C19 1 µF
Q1 MMSF4N01HD
R1, R2 2.7 kΩ
NOTE: For PCS/DCS1900 applications, the following
component values are changed.
C6 = 2.7 pF, 0603 NPO/COG
L2 = 1.5 nH, Toko 2012
T3 = 1 mm 50 Ω Microstrip Line
Figure 2. DCS1800 Applications Circuit Configuration
50 Ω Microstrip Line
or 5 mm 50 Ω Line
U1
R3, R4 100 Ω
R5 470 Ω
T1 2 mm 25 Ω Microstrip Line
T2 5 mm 50 Ω Microstrip Line
T3 8 mm 40 Ω Microstrip Line
T4 1 mm 40 Ω Microstrip Line
U1 MRFIC1818
U2 MC33169 (–4 V Version)
Board Material: Glass/Epoxy,
Thickness = 0.5 mm
ε
= 4.45,
r
MRFIC1818MOTOROLA RF DEVICE DATA
3
Page 4
T ypical Characteristics
35
34
TA = –35°C
33
32
out
P , OUTPUT POWER (dBm)
Pin = 3 dBm
31
VD1, V
VSS = –4 V
30
1.7 1.72 1.74 1.76 1.78 1.8
D2, VD3
= 4 V
f, FREQUENCY (GHz)
25°C
85°C
46
44
42
40
38
Pin = 3 dBm
36
PAE, POWER ADDED EFFICIENCY (%)
VD1, V
VSS = –4 V
34
1.7 1.72 1.74 1.76 1.78 1.8
D2, VD3
= 4.8 V
f, FREQUENCY (GHz)
Figure 3. Output Power versus Frequency Figure 4. Power Added Efficiency
versus Frequency
36
35
TA = –35°C
44
42
TA = –35°C
25°C
85°C
VD1 = VD2 = 5.6 V
4.8 V
34
85°C
out
33
P , OUTPUT POWER (dBm)
Pin = 3 dBm
VD1, V
VSS = –4 V
32
1.7 1.72 1.74 1.76 1.78 1.8
D2, VD3
= 4.8 V
f, FREQUENCY (GHz)
Figure 5. Output Power versus Frequency Figure 6. Power Added Efficiency
37
36
25°C
35
out
P , OUTPUT POWER (dBm)
Pin = 3 dBm
VD1, V
VSS = –4 V
34
1.7 1.72 1.74 1.76 1.78 1.8
D2, VD3
= 5.6 V
f, FREQUENCY (GHz)
TA = –35°C
85°C
Figure 7. Output Power versus Frequency Figure 8. Output Power versus Drain Voltage
25°C
4 V
40
Pin = 3 dBm
TA = 25
°
PAE, POWER ADDED EFFICIENCY (%)
38
1.7 1.72 1.74 1.76 1.78 1.8
C
VSS = –4 V
f, FREQUENCY (GHz)
versus Frequency
40
25°C AND 85°C
30
20
10
–10
–20
–30
out
P , OUTPUT POWER (dBm)
–40
–50
–60
0
TA = –35°C
f = 1.75 GHz
Pin = 3 dBm
VSS = –4 V
01 3 456
2
V
, VD2, DRAIN VOLTAGE (VOLTS)
D1
MRFIC1818
4
MOTOROLA RF DEVICE DATA
Page 5
T ypical Characteristics
45
40
35
TA = –35°C
30
25
20
15
10
PAE, POWER ADDED EFFICIENCY (%)
5
0
01 3456
V
D1
25
2
, VD2, DRAIN VOLTAGE (VOLTS)
85°C
°
C
f = 1.75 GHz
Pin = 3 dBm
VSS = –4 V
Figure 9. Power Added Efficiency versus
Drain Voltage
45
40
35
30
25
20
15
10
PAE, POWER ADDED EFFICIENCY (%)
5
0
–20 –15 –10 –5 0 10
TA = –35°C
25°C
85°C
f = 1.75 GHz
VD1, V
VSS = –4 V
Pin, INPUT POWER (dBm)
D2, VD3
5
= 4.8 V
Figure 11. Power Added Efficiency versus
Input Power
35
33
31
29
27
25
23
21
out
P , OUTPUT POWER (dBm)
19
17
15
–20 –15 –10 –5 0 10
TA = –35°C
25°C
85°C
Pin, INPUT POWER (dBm)
f = 1.75 GHz
VD1, V
D2, VD3
VSS = –4 V
= 4.8 V
5
Figure 10. Output Power versus Input Power
50
48
46
44
42
40
38
36
, SECOND HARMONIC (dBc)
2
34
H
32
30
0246
TA = –35°C
V
, VD2, DRAIN VOLTAGE (VOLTS)
D1
25°C
85°C
f = 1.75 GHz
Pin = 3 dBm
VSS = –4 V
Figure 12. Second Harmonic versus
Drain Voltage
41
39
37
35
33
31
, THIRD HARMONIC (dBc)
3
29
H
27
25
0246
V
, VD2, DRAIN VOLTAGE (VOLTS)
D1
TA = –35°C
25°C
85°C
f = 1.75 GHz
Pin = 3 dBm
VSS = –4 V
Figure 13. Third Harmonic versus
36
35.5
35
34.5
out
P , OUTPUT POWER (dBm)
34
33.5
1.85 1.86 1.88 1.89 1.9 1.91
Figure 14. Output Power Versus Frequency –
Drain Voltage
TA = –35°C
25°C
85°C
Pin = 3 dBm
VD1, VD2, VD3 = 4.8 V
VSS = –4 V
1.87
f, FREQUENCY (GHz)
PCS Band
MRFIC1818MOTOROLA RF DEVICE DATA
5
Page 6
T ypical Characteristics
47
TA = –35°C
45
°
C
25
43
85°C
41
PAE, POWER ADDED EFFICIENCY (%)
39
1.85 1.86 1.88 1.89 1.9 1.91
1.87
f, FREQUENCY (GHz)
Pin = 3 dBm
VD1, V
D2, VD3
VSS = –4 V
= 4.8 V
Figure 15. Power Added Efficiency versus
Frequency – PCS Band
50
VD1, VD2, VD3 = 5.6 V
49
4.8 V
48
f = 1880 MHz
47
Carrier BW = 30 kHz
Channel BW = 30 kHz
Temp = 25
ACPR, ADJACENT CHANNEL POWER (dBc)
46
10 15 20 25 30
°
C
P
, OUTPUT POWER (dBm)
out
Figure 17. CDMA ACPR at 1980 kHz Offset
versus Output Power
35
50
5.6 V
45
VD1, VD2, VD3 = 4.8 V
40
35
f = 1880 MHz
Carrier BW = 30 kHz
30
Channel BW = 30 kHz
ACPR, ADJACENT CHANNEL POWER (dBc)
Temp = 25
25
10 15 20 25 30
°
C
P
, OUTPUT POWER (dBm)
out
Figure 16. CDMA ACPR at 885 kHz Offset versus
Output Power
T able 1. Optimum Loads Derived from
Circuit Characterization
Z
in
9.19
9.35
9.50
9.65
9.60
9.42
9.11
8.77
8.54
OHMS
jXRjXR
–30.10
–29.60
–29.30
–29.10
–29.00
–28.79
–28.60
–28.30
–28.15
f
MHz
1710
1720
1730
1740
1750
1760
1770
1780
1785
Zin represents the input impedance of the device.
ZOL* represents the conjugate of the optimum output load to present
to the device.
6.00
5.96
5.88
5.80
5.75
5.67
5.60
5.51
5.45
ZOL*
OHMS
3.80
3.71
3.60
3.46
3.33
3.20
3.07
2.93
2.79
35
MRFIC1818
6
T able 2. Optimum Loads Derived from
Circuit Characterization – PCS Board
Z
in
3.92
4.01
4.08
4.19
4.29
4.31
4.37
OHMS
jXRjXR
–43.30
–43.56
–43.78
–44.00
–44.29
–44.49
–44.81
f
MHz
1850
1860
1870
1880
1890
1900
1910
Zin represents the input impedance of the device.
ZOL* represents the conjugate of the optimum output load to present
to the device.
7.70
7.64
7.57
7.51
7.50
7.44
7.35
ZOL*
OHMS
0.39
0.23
0.15
0.07
–0.04
–0.06
–0.19
MOTOROLA RF DEVICE DATA
Page 7
APPLICATIONS INFORMATION
Design Philosophy
The MRFIC1818 is a 3–stage Integrated Power Amplifier
designed for use in cellular phones, especially for those used
in DCS1800 (PCN) 4.8 V operation. With matching circuit
modifications, it is also applicable for use in DCS1900 (PCS)
equipment. Due to the fact that the input, output and some of
the interstage matching is accomplished off chip, the device
can be tuned to operate anywhere within the 1500 to
2000 MHz frequency range. Typical performance at different
battery voltages is:
• 36 dBm @ 6.0 V
• 34.5 dBm @ 4.8 V
• 32.0 dBm @ 3.6 V
This capability makes the MRFIC1818 suitable for portable
cellular applications such as:
• 6V and 4.8 V DCS1800 Class I
• 6V and 4.8 V PCS tag5
• 3.6 V DCS1800 Class II
RF Circuit Considerations
The MRFIC1818 can be tuned by changing the values
and/or positions of the appropriate external components. Refer to Figure 2, a typical DCS1800 Class I applications circuit.
The input match is a shunt–L, series–C, High–pass structure
and can be retuned as desired with the only limitation being
the on–chip 6 pF blocking capacitor. For saturated applications such as DCS1800 and DCS1900, the input match
should be optimized at the rated RF input power. Interstage
matching can be optimized by changing the value and/or
position of the decoupling capacitor on the VD1 and VD2 supply lines. Moving the capacitor closer to the device or reducing the value increases the frequency of resonance with the
in–ductance of the device’s wirebonds and leadframe pin.
Output matching is accomplished with a one–stage low–
pass network as a compromise between bandwidth and harmonic rejection. Implementation is through chip capacitors
mounted along a 30 or 50 W microstrip transmission line. V alues and positions are chosen to present a 2.5 W loadline to
the device while conjugating the device output parasitics.
The network must also properly terminate the second and
third harmonics to optimize efficiency and reduce harmonic
output. Low–Q commercial chip capacitors are used for the
shunt capacitors, as shown in Figure 2. Loss in circuit traces
must also be considered. The output transmission line and
the bias supply lines should be at least 0.6 mm in width to
accommodate the peak circulating currents which can be as
high as 2 amperes under worst case conditions. The bias
supply line which supplies the output should include an RF
choke of at least 18 nH, surface mount solenoid inductors or
quarter wave microstrip lines. Discrete inductors will usually
give better efficiency and conserve board space. The DC
blocking capacitor required at the output of the device is best
mounted at the 50 W impedance point in the circuit where the
RF current is at a minimum and the capacitor loss will have
less effect.
Biasing Considerations
Gate bias lines are tied together and connected to the V
voltage, allowing gate biasing through use of external resistors or positive voltages. This allows setting the quiescent
current of all stage in the same time while saving some board
SS
space. For applications where the amplifier is operated close
to saturation, such as TDMA amplifiers, the gate bias can be
set with resistors. Variations in process and tempera–ture
will not affect amplifier performance significantly in these applications. The values shown in the Figure 1 will set quies–
cent currents of 20 to 40 mA for the first stage, 150 to 300 for
the second stage and 400 to 800 mA for the final stage. For
linear modes of operation which are required for CDMA amplifiers, the quiescent current must be more carefully controlled. For these applications, the VG pins can be referenced
to some tunable voltage which is set at the time of radio
manufacturing. Less than 1 mA is required in the divider network so a DAC can be used as the voltage source.
Power Control Using the MC33169
The MC33169 is a dedicated GaAs power amplifier support IC which provides the –4 V required for VSS, an N–MOS
drain switch interface and driver and power supply sequencing. The MC33169 can be used for power control in applications where the amplifier is operated in saturation since the
output power in non–linear operation is proportional to VD2.
This provides a very linear and repeatable power control
transfer function. This technique can be used open loop to
achieve 40–45 dB dynamic range over process and temperature variation. With careful design and selection of calibration points, this technique can be used for DCS1800 control
where 30 dB dynamic range is required, eliminating the need
for the complexity and cost of closed–loop control. The transmit waveform ramping function required for systems such as
DCS1800 can be implemented with a simple Sallen and Key
filter on the MC33169 control loop. The amplifier is then
ramped on as the V
plement the different power steps required for DCS1800, the
V
age between 0 V and 3 V for the desired output power. For
closed–loop configurations using the MC33169,
MMSF4N01HD N–MOS switch and the MRFIC1818 provide
a typical 1 MHz 3 dB loop bandwidth. The STANDBY pin
must be enabled (3 V) at least 800 µs before the V
goes high and disabled (0 V) at least 20 µs before the V
pin goes low. This STANDBY function allows for the enabling
of the MC33169 one burst before the active burst thus reducing power consumption.
Conclusion
and gate biasing required for portable cellular applications.
Together with the MC33169 support IC, the device offers an
efficient system solution for TDMA applications such as
DCS1800 where saturated amplifier operation is used.
MC33169, refer to application note AN1599, “Power Control
with the MRFIC0913 GaAs Integrated Power Amplifier and
MC33169 Support IC.”
Evaluation Boards
available. Order MRFIC1818DCSTF for the 1.8 GHz version
and order MRFIC1818PCSTF for the 1.9 GHz version. For a
complete list of currently available boards and ones in development for newly introduced product, please contact your local Motorola Distributor or Sales Office.
pin is ramped between 0 V and the appropriate volt-
RAMP
The MRFIC1818 offers the flexibility in matching circuitry
For more information about the power control using the
Two versions of the MRFIC1818 evaluation board are
pin is taken from 0 V to 3 V . To im-
RAMP
RAMP
RAMP
pin
MRFIC1818MOTOROLA RF DEVICE DATA
7
Page 8
P ACKAGE DIMENSIONS
X 45
h
_
A
E2
e
14 x
A
A2
e/2
1
8
E1
8X E
M
bbb C
DETAIL Y
ccc C
16
D
9
B
S
B
DATUM
H
PLANE
BOTTOM VIEW
b1
c
c1
b
S
A
C
SEATING
PLANE
M
aaa C
SECT W–W
L1
q
L
1.000
0.039
W
W
GAUGE
PLANE
A1
D1
NOTES:
1. CONTROLLING DIMENSION: MILLIMETER.
2. DIMENSIONS AND TOLERANCES PER ASME
Y14.5M, 1994.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 PER SIDE. DIMENSIONS D AND E1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION IS 0.127 TOTAL IN EXCESS OF THE
b DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. DATUMS –A– AND –B– TO BE DETERMINED AT
DATUM PLANE –H–.
MILLIMETERS
DIM MIN MAX
A 2.000 2.350
A1 0.025 0.152
A2 1.950 2.100
D 6.950 7.100
D1 4.372 5.180
E 8.850 9.150
E1 6.950 7.100
E2 4.372 5.180
L 0.466 0.720
L1 0.250 BSC
b 0.300 0.432
b1 0.300 0.375
c 0.180 0.279
c1 0.180 0.230
e 0.800 BSC
h ––– 0.600
q
0 7
__
aaa 0.200
bbb 0.200
ccc 0.100
DETAIL Y
CASE 978–02
ISSUE A
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1,
P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488
Mfax: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
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INTERNET: http://motorola.com/sps
Mfax is a trademark of Motorola, Inc.
MRFIC1818
8
◊
MOTOROLA RF DEVICE DATA
MRFIC1818/D
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