Designed for broadband commercial and military applications using single
ended circuits at frequencies to 500 MHz. The high power, high gain and
broadband performance of this device makes possible solid state transmitters
for FM broadcast or TV channel frequency bands.
• Guaranteed Performance @ 500 MHz, 28 Vdc
Output Power — 100 Watts
Power Gain — 8.8 dB Typ
Efficiency — 55% Typ
• 100% Ruggedness Tested At Rated Output Power
• Low Thermal Resistance
• Low C
— 17 pF Typ @ VDS = 28 Volts
rss
G
D
S
Order this document
by MRF275L/D
MRF275L
100 W, 28 V, 500 MHz
N–CHANNEL
BROADBAND
RF POWER FET
CASE 333–04, STYLE 2
MAXIMUM RATINGS
RatingSymbolValueUnit
Drain–Source VoltageV
Gate–Source VoltageV
Drain Current — ContinuousI
Total Device Dissipation @ TC = 25°C
Derate above 25°C
Storage Temperature RangeT
Operating Junction TemperatureT
THERMAL CHARACTERISTICS
CharacteristicSymbolMaxUnit
Thermal Resistance, Junction to CaseR
ELECTRICAL CHARACTERISTICS (T
Characteristic
= 25°C unless otherwise noted)
C
SymbolMinTypMaxUnit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0, ID = 50 mA)
Zero Gate Voltage Drain Current
(VDS = 28 V, VGS = 0)
Gate–Body Leakage Current
(VGS = 20 V, VDS = 0)
V
(BR)DSS
I
DSS
I
GSS
DSS
GS
D
P
D
stg
J
θJC
65——Vdc
——2.5mAdc
——1.0µAdc
65Vdc
±20Vdc
13Adc
270
1.54
–65 to +150°C
200°C
0.65°C/W
Watts
W/°C
NOTE – CAUTION – MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and
packaging MOS devices should be observed.
REV2
1
Page 2
ELECTRICAL CHARACTERISTICS — continued (T
CharacteristicSymbolMinTypMaxUnit
= 25°C unless otherwise noted)
C
ON CHARACTERISTICS
Gate Threshold Voltage (VDS = 10 V, ID = 100 mA)V
Drain–Source On–Voltage (VGS = 10 V, ID = 5.0 A)V
Forward Transconductance (VDS = 10 V, ID = 2.5 A)g
DYNAMIC CHARACTERISTICS
Input Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz)C
Output Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz)C
Reverse Transfer Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz)C
RFC18 Turns AWG #18, 0.25″I.D., Enameled
RFC2, RFC3Ferroxcube VK200 19/4B
Z1,0.250″ x 0.800″, Microstrip Line
Z2, Z30.250″ x 0.400″,Microstrip Line
Z40.250″ x 1.25″, Microstrip Line
Board Material0.062″ Glass Teflon,
Z4
C9
2 oz. Copper, Double Clad Copper
Board, εr = 2.55
C10
RFC3
C14
RF
OUTPUT
+
+28 V
C15
REV2
2
Figure 1. 500 MHz Test Circuit
Page 3
TYPICAL CHARACTERISTICS
160
140
120
100
, OUTPUT POWER (WATTS)
out
P
80
60
40
20
0
412
f = 225 MHz
8
10614218
Pin, INPUT POWER (WA TTS)
Figure 2. Output Power versus Input Power
10
VDS = 10 V
9
V
= 2.5 V
GS(th)
8
7
6
5
4
3
, DRAIN CURRENT (AMPS)
D
I
2
1
0
0
VGS, GATE–SOURCE VOLTAGE (VOLTS)
2
315
400 MHz
VDD = 28 V
IDQ = 100 mA
500 MHz
16
4
100
90
80
70
60
50
40
30
, OUTPUT POWER (WATTS)
out
20
P
10
0
20
–1000
–6–4
–8
VGS, GATE–SOURCE VOLTAGE (VOLTS)
–2
VDS = 28 V
IDQ = 100 mA
Pin = Constant
f = 500 MHz
42
Figure 3. Output Power versus Gate Voltage
140
0
IDQ = 100 mA
f = 500 MHz
141612
182028
VDD, SUPPLY VOLTAGE (VOLTS)
Pin = 13.5 W
10 W
6 W
24
2226
120
100
80
60
, OUTPUT POWER (WATTS)
40
out
P
20
4.52.50.53.51.5
Figure 4. Drain Current versus Gate Voltage
(Transfer Characteristics)
160
80
60
40
20
IDQ = 100 mA
f = 400 MHz
0
141612182028242226
VDD, SUPPLY VOLTAGE (VOLTS)
140
120
100
, OUTPUT POWER (WATTS)
out
P
Figure 6. Output Power versus Supply Voltage
REV2
3
Pin = 14 W
10 W
6 W
Figure 5. Output Power versus Supply Voltage
160
80
60
40
20
IDQ = 100 mA
f = 225 MHz
0
141612182028242226
VDD, SUPPLY VOLTAGE (VOLTS)
, OUTPUT POWER (WATTS)
out
P
140
120
100
Figure 7. Output Power versus Supply Voltage
Pin = 8 W
4 W
2 W
Page 4
TYPICAL CHARACTERISTICS
1000
C
oss
C, CAPACITANCE (pF)
100
10
1
0
515
10
VDS, DRAIN–SOURCE VOLTAGE (VOLTS)
C
iss
C
rss
VGS = 0 V
f = 1.0 MHz
20110025
Figure 8. Capacitance versus Drain–Source V oltage
100
10
, DRAIN CURRENT (AMPS)
D
I
TC = 25°C
30
1
VDS, DRAIN–SOURCE VOLTAGE (VOLTS)
10
Figure 9. DC Safe Operating Area
REV2
4
Page 5
f = 500 MHz
400
225
f = 500 MHz
Z
Zo = 10 Ω
in
400
225
ZOL*
Zo = 10 Ω
VDD = 28 V, IDQ = 100 mA, P
f
(MHz)
225
400
500
ZOL* = Conjugate of the optimum load impedance into which the device
Z
Ohms
1.1 – j1.7
1.08 – j1.5
1.0 – j0.5
operates at a given output power, voltage and frequency.
Figure 10. Series Equivalent Input/Output Impedance
L212 Turns #18 Wire, 0.450″ ID
L3Ferroxcube VK200 20/4B
Figure 12. 400 MHz T est Circuit
C7C6C5
R110 k, 1/4 W Resistor
R21 k, 1/4 W Resistor
R31.5 k, 1/4 W Resistor
Z10.950″ x 0.250″, Microstrip Line
Z21.25″ x 0.250″, Microstrip Line
Z30.300″ x 0.250″, Microstrip Line
Board Material 0.062″ Teflon,
Fiberglass, 1 oz. Copper,
Clad Both Sides, εr = 2.56
Page 7
+
C3
RFC2
C12C13
BEADS
C11C14
RFC1
C4
C1
R1
C2
R2
C5C7
C6C8C9
Figure 13. MRF275L Component Location (500 MHz)
RFC3
C15
+
C10
(Not to Scale)
+
REV2
7
MRF275L
(Scale 1:1)
Figure 14. MRF275L T est Circuit Photomaster
(Reduced 18% in printed data book, DL110/D)
Page 8
T able 1. Common Source S–Parameters (VDS = 12.5 V, ID = 4.5 A)
The physical structure of a MOSFET results in capacitors
between the terminals. The metal oxide gate structure determines the capacitors from gate–to–drain (Cgd), and gate–to–
source (Cgs). The PN junction formed during the fabrication
of the FET results in a junction capacitance from drain–to–
source (Cds).
These capacitances are characterized as input (C
put (C
) and reverse transfer (C
oss
) capacitances on data
rss
iss
), out-
sheets. The relationships between the inter–terminal capacitances and those given on data sheets are shown below. The
C
can be specified in two ways:
iss
1. Drain shorted to source and positive voltage at the gate.
2. Positive voltage of the drain in respect to source and zero
volts at the gate. In the latter case the numbers are lower.
However, neither method represents the actual operating conditions in RF applications.
DRAIN
C
ds
SOURCE
C
iss
C
oss
C
rss
= Cgd + C
= Cgd + C
= C
gd
gs
ds
GATE
C
gd
C
gs
DRAIN CHARACTERISTICS
One figure of merit for a FET is its static resistance in the
full–on condition. This on–resistance, V
DS(on)
, occurs in the
linear region of the output characteristic and is specified under specific test conditions for gate–source voltage and drain
current. For MOSFETs, V
has a positive temperature
DS(on)
coefficient and constitutes an important design consideration
at high temperatures, because it contributes to the power
dissipation within the device.
GATE CHARACTERISTICS
The gate of the FET is a polysilicon material, and is electrically isolated from the source by a layer of oxide. The input
resistance is very high — on the order of 109 ohms — resulting in a leakage current of a few nanoamperes.
Gate control is achieved by applying a positive voltage
slightly in excess of the gate–to–source threshold voltage,
V
GS(th)
.
Gate Voltage Rating — Never exceed the gate voltage
rating. Exceeding the rated VGS can result in permanent
damage to the oxide layer in the gate region.
Gate Termination — The gates of these devices are
essentially capacitors. Circuits that leave the gate open–circuited or floating should be avoided. These conditions can
result in turn–on of the devices due to voltage build–up on
the input capacitor due to leakage currents or pickup.
Gate Protection — These devices do not have an internal
monolithic zener diode from gate–to–source. If gate protection is required, an external zener diode is recommended.
Using a resistor to keep the gate–to–source impedance
low also helps damp transients and serves another important
function. Voltage transients on the drain can be coupled to
the gate through the parasitic gate–drain capacitance. If the
gate–to–source impedance and the rate of voltage change
on the drain are both high, then the signal coupled to the gate
may be large enough to exceed the gate–threshold voltage
and turn the device on.
HANDLING CONSIDERATIONS
When shipping, the devices should be transported only in
antistatic bags or conductive foam. Upon removal from the
packaging, careful handling procedures should be adhered
to. Those handling the devices should wear grounding straps
and devices not in the antistatic packaging should be kept in
metal tote bins. MOSFETs should be handled by the case
and not by the leads, and when testing the device, all leads
should make good electrical contact before voltage is applied. As a final note, when placing the FET into the system it
is designed for, soldering should be done with a grounded
iron.
DESIGN CONSIDERATIONS
The MRF275L is a RF power N–channel enhancement
mode field–effect transistor (FETs) designed for HF, VHF and
UHF power amplifier applications. M/A-COM FETs feature a
vertical structure with a planar design.
M/A-COM Application Note AN211A, FETs in Theory and
Practice, is suggested reading for those not familiar with the
construction and characteristics of FETs.
The major advantages of RF power FETs include high
gain, low noise, simple bias systems, relative immunity from
thermal runaway, and the ability to withstand severely mismatched loads without suffering damage. Power output can
be varied over a wide range with a low power dc control signal.
DC BIAS
The MRF275L is an enhancement mode FET and, therefore, does not conduct when drain voltage is applied. Drain
current flows when a positive voltage is applied to the gate.
RF power FETs require forward bias for optimum performance. The value of quiescent drain current (IDQ) is not critical for many applications. The MRF275L was characterized
at IDQ = 100 mA, each side, which is the suggested minimum
value of IDQ. For special applications such as linear amplification, IDQ may have to be selected to optimize the critical
parameters.
The gate is a dc open circuit and draws no current. Therefore, the gate bias circuit may be just a simple resistive divider network. Some applications may require a more elaborate
bias system.
GAIN CONTROL
Power output of the MRF275L may be controlled from its
rated value down to zero (negative gain) by varying the dc
gate voltage. This feature facilitates the design of manual
gain control, AGC/ALC and modulation systems.
REV2
12
Page 13
P ACKAGE DIMENSIONS
–A–
L
D
2
1
3
P
4
K
–B–
K
Q 2 PL
M
0.13 (0.005)B
A
T
M
M
F
G
J
H
N
E
C
SEATING
–T–
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIM MINMAXMINMAX
A0.965 0.985 24.51 25.02
B 0.390 0.4109.91 10.41
C 0.250 0.2906.737.36
D 0.190 0.2104.835.33
E 0.095 0.1152.422.92
F 0.215 0.2355.475.96
G0.725 BSC18.42 BSC
H 0.155 0.1753.944.44
J0.004 0.0060.100.15
K 0.195 0.2054.955.21
L 0.740 0.770 18.80 19.55
N 0.415 0.425 10.54 10.80
P 0.390 0.4009.91 10.16
Q 0.120 0.1353.053.42
STYLE 2:
PIN 1. SOURCE
2. DRAIN
3. SOURCE
4. GATE
MILLIMETERSINCHES
CASE 333–04
ISSUE E
Specifications subject to change without notice.
n
North America: Tel. (800) 366-2266, Fax (800) 618-8883
n Asia/Pacific: Tel.+81-44-844-8296, Fax +81-44-844-8298
n